1 /* 2 * Copyright (C) 2010 3 * Rob Emanuele <rob@emanuele.us> 4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de> 5 * 6 * Original Driver: 7 * Copyright (C) 2004-2006 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <mmc.h> 14 #include <part.h> 15 #include <malloc.h> 16 #include <asm/io.h> 17 #include <asm/errno.h> 18 #include <asm/byteorder.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/hardware.h> 21 #include "atmel_mci.h" 22 23 #ifndef CONFIG_SYS_MMC_CLK_OD 24 # define CONFIG_SYS_MMC_CLK_OD 150000 25 #endif 26 27 #define MMC_DEFAULT_BLKLEN 512 28 29 #if defined(CONFIG_ATMEL_MCI_PORTB) 30 # define MCI_BUS 1 31 #else 32 # define MCI_BUS 0 33 #endif 34 35 static int initialized = 0; 36 37 /* Read Atmel MCI IP version */ 38 static unsigned int atmel_mci_get_version(struct atmel_mci *mci) 39 { 40 return readl(&mci->version) & 0x00000fff; 41 } 42 43 /* 44 * Print command and status: 45 * 46 * - always when DEBUG is defined 47 * - on command errors 48 */ 49 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) 50 { 51 printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n", 52 cmdr, cmdr&0x3F, arg, status, msg); 53 } 54 55 /* Setup for MCI Clock and Block Size */ 56 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) 57 { 58 atmel_mci_t *mci = mmc->priv; 59 u32 bus_hz = get_mci_clk_rate(); 60 u32 clkdiv = 255; 61 62 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n", 63 bus_hz, hz, blklen); 64 if (hz > 0) { 65 /* find lowest clkdiv yielding a rate <= than requested */ 66 for (clkdiv=0; clkdiv<255; clkdiv++) { 67 if ((bus_hz / (clkdiv+1) / 2) <= hz) 68 break; 69 } 70 } 71 printf("mci: setting clock %u Hz, block size %u\n", 72 (bus_hz / (clkdiv+1)) / 2, blklen); 73 74 blklen &= 0xfffc; 75 /* On some platforms RDPROOF and WRPROOF are ignored */ 76 writel((MMCI_BF(CLKDIV, clkdiv) 77 | MMCI_BF(BLKLEN, blklen) 78 | MMCI_BIT(RDPROOF) 79 | MMCI_BIT(WRPROOF)), &mci->mr); 80 /* 81 * On some new platforms BLKLEN in mci->mr is ignored. 82 * Should use the BLKLEN in the block register. 83 */ 84 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr); 85 initialized = 1; 86 } 87 88 /* Return the CMDR with flags for a given command and data packet */ 89 static u32 mci_encode_cmd( 90 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags) 91 { 92 u32 cmdr = 0; 93 94 /* Default Flags for Errors */ 95 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) | 96 MMCI_BIT(RINDE) | MMCI_BIT(RTOE)); 97 98 /* Default Flags for the Command */ 99 cmdr |= MMCI_BIT(MAXLAT); 100 101 if (data) { 102 cmdr |= MMCI_BF(TRCMD, 1); 103 if (data->blocks > 1) 104 cmdr |= MMCI_BF(TRTYP, 1); 105 if (data->flags & MMC_DATA_READ) 106 cmdr |= MMCI_BIT(TRDIR); 107 } 108 109 if (cmd->resp_type & MMC_RSP_CRC) 110 *error_flags |= MMCI_BIT(RCRCE); 111 if (cmd->resp_type & MMC_RSP_136) 112 cmdr |= MMCI_BF(RSPTYP, 2); 113 else if (cmd->resp_type & MMC_RSP_BUSY) 114 cmdr |= MMCI_BF(RSPTYP, 3); 115 else if (cmd->resp_type & MMC_RSP_PRESENT) 116 cmdr |= MMCI_BF(RSPTYP, 1); 117 118 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx); 119 } 120 121 /* Entered into function pointer in mci_send_cmd */ 122 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags) 123 { 124 u32 status; 125 126 do { 127 status = readl(&mci->sr); 128 if (status & (error_flags | MMCI_BIT(OVRE))) 129 goto io_fail; 130 } while (!(status & MMCI_BIT(RXRDY))); 131 132 if (status & MMCI_BIT(RXRDY)) { 133 *data = readl(&mci->rdr); 134 status = 0; 135 } 136 io_fail: 137 return status; 138 } 139 140 /* Entered into function pointer in mci_send_cmd */ 141 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags) 142 { 143 u32 status; 144 145 do { 146 status = readl(&mci->sr); 147 if (status & (error_flags | MMCI_BIT(UNRE))) 148 goto io_fail; 149 } while (!(status & MMCI_BIT(TXRDY))); 150 151 if (status & MMCI_BIT(TXRDY)) { 152 writel(*data, &mci->tdr); 153 status = 0; 154 } 155 io_fail: 156 return status; 157 } 158 159 /* 160 * Entered into mmc structure during driver init 161 * 162 * Sends a command out on the bus and deals with the block data. 163 * Takes the mmc pointer, a command pointer, and an optional data pointer. 164 */ 165 static int 166 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 167 { 168 atmel_mci_t *mci = mmc->priv; 169 u32 cmdr; 170 u32 error_flags = 0; 171 u32 status; 172 173 if (!initialized) { 174 puts ("MCI not initialized!\n"); 175 return COMM_ERR; 176 } 177 178 /* Figure out the transfer arguments */ 179 cmdr = mci_encode_cmd(cmd, data, &error_flags); 180 181 /* For multi blocks read/write, set the block register */ 182 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) 183 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) 184 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len), 185 &mci->blkr); 186 187 /* Send the command */ 188 writel(cmd->cmdarg, &mci->argr); 189 writel(cmdr, &mci->cmdr); 190 191 #ifdef DEBUG 192 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG"); 193 #endif 194 195 /* Wait for the command to complete */ 196 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY))); 197 198 if ((status & error_flags) & MMCI_BIT(RTOE)) { 199 dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out"); 200 return TIMEOUT; 201 } else if (status & error_flags) { 202 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed"); 203 return COMM_ERR; 204 } 205 206 /* Copy the response to the response buffer */ 207 if (cmd->resp_type & MMC_RSP_136) { 208 cmd->response[0] = readl(&mci->rspr); 209 cmd->response[1] = readl(&mci->rspr1); 210 cmd->response[2] = readl(&mci->rspr2); 211 cmd->response[3] = readl(&mci->rspr3); 212 } else 213 cmd->response[0] = readl(&mci->rspr); 214 215 /* transfer all of the blocks */ 216 if (data) { 217 u32 word_count, block_count; 218 u32* ioptr; 219 u32 sys_blocksize, dummy, i; 220 u32 (*mci_data_op) 221 (atmel_mci_t *mci, u32* data, u32 error_flags); 222 223 if (data->flags & MMC_DATA_READ) { 224 mci_data_op = mci_data_read; 225 sys_blocksize = mmc->read_bl_len; 226 ioptr = (u32*)data->dest; 227 } else { 228 mci_data_op = mci_data_write; 229 sys_blocksize = mmc->write_bl_len; 230 ioptr = (u32*)data->src; 231 } 232 233 status = 0; 234 for (block_count = 0; 235 block_count < data->blocks && !status; 236 block_count++) { 237 word_count = 0; 238 do { 239 status = mci_data_op(mci, ioptr, error_flags); 240 word_count++; 241 ioptr++; 242 } while (!status && word_count < (data->blocksize/4)); 243 #ifdef DEBUG 244 if (data->flags & MMC_DATA_READ) 245 { 246 printf("Read Data:\n"); 247 print_buffer(0, data->dest, 1, 248 word_count*4, 0); 249 } 250 #endif 251 #ifdef DEBUG 252 if (!status && word_count < (sys_blocksize / 4)) 253 printf("filling rest of block...\n"); 254 #endif 255 /* fill the rest of a full block */ 256 while (!status && word_count < (sys_blocksize / 4)) { 257 status = mci_data_op(mci, &dummy, 258 error_flags); 259 word_count++; 260 } 261 if (status) { 262 dump_cmd(cmdr, cmd->cmdarg, status, 263 "Data Transfer Failed"); 264 return COMM_ERR; 265 } 266 } 267 268 /* Wait for Transfer End */ 269 i = 0; 270 do { 271 status = readl(&mci->sr); 272 273 if (status & error_flags) { 274 dump_cmd(cmdr, cmd->cmdarg, status, 275 "DTIP Wait Failed"); 276 return COMM_ERR; 277 } 278 i++; 279 } while ((status & MMCI_BIT(DTIP)) && i < 10000); 280 if (status & MMCI_BIT(DTIP)) { 281 dump_cmd(cmdr, cmd->cmdarg, status, 282 "XFER DTIP never unset, ignoring"); 283 } 284 } 285 286 return 0; 287 } 288 289 /* Entered into mmc structure during driver init */ 290 static void mci_set_ios(struct mmc *mmc) 291 { 292 atmel_mci_t *mci = mmc->priv; 293 int bus_width = mmc->bus_width; 294 unsigned int version = atmel_mci_get_version(mci); 295 int busw; 296 297 /* Set the clock speed */ 298 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); 299 300 /* 301 * set the bus width and select slot for this interface 302 * there is no capability for multiple slots on the same interface yet 303 */ 304 if ((version & 0xf00) >= 0x300) { 305 switch (bus_width) { 306 case 8: 307 busw = 3; 308 break; 309 case 4: 310 busw = 2; 311 break; 312 default: 313 busw = 0; 314 break; 315 } 316 317 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); 318 } else { 319 busw = (bus_width == 4) ? 1 : 0; 320 321 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); 322 } 323 } 324 325 /* Entered into mmc structure during driver init */ 326 static int mci_init(struct mmc *mmc) 327 { 328 atmel_mci_t *mci = mmc->priv; 329 330 /* Initialize controller */ 331 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ 332 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */ 333 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */ 334 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */ 335 336 /* This delay can be optimized, but stick with max value */ 337 writel(0x7f, &mci->dtor); 338 /* Disable Interrupts */ 339 writel(~0UL, &mci->idr); 340 341 /* Set default clocks and blocklen */ 342 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); 343 344 return 0; 345 } 346 347 static const struct mmc_ops atmel_mci_ops = { 348 .send_cmd = mci_send_cmd, 349 .set_ios = mci_set_ios, 350 .init = mci_init, 351 }; 352 353 /* 354 * This is the only exported function 355 * 356 * Call it with the MCI register base address 357 */ 358 int atmel_mci_init(void *regs) 359 { 360 struct mmc *mmc; 361 struct mmc_config *cfg; 362 struct atmel_mci *mci; 363 unsigned int version; 364 365 cfg = malloc(sizeof(*cfg)); 366 if (cfg == NULL) 367 return -1; 368 memset(cfg, 0, sizeof(*cfg)); 369 370 mci = (struct atmel_mci *)regs; 371 372 cfg->name = "mci"; 373 cfg->ops = &atmel_mci_ops; 374 375 /* need to be able to pass these in on a board by board basis */ 376 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 377 version = atmel_mci_get_version(mci); 378 if ((version & 0xf00) >= 0x300) 379 cfg->host_caps = MMC_MODE_8BIT; 380 381 cfg->host_caps |= MMC_MODE_4BIT; 382 383 /* 384 * min and max frequencies determined by 385 * max and min of clock divider 386 */ 387 cfg->f_min = get_mci_clk_rate() / (2*256); 388 cfg->f_max = get_mci_clk_rate() / (2*1); 389 390 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 391 392 mmc = mmc_create(cfg, regs); 393 394 if (mmc == NULL) { 395 free(cfg); 396 return -1; 397 } 398 /* NOTE: possibly leaking the cfg structure */ 399 400 return 0; 401 } 402