1 /* 2 * Copyright (C) 2010 3 * Rob Emanuele <rob@emanuele.us> 4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de> 5 * 6 * Original Driver: 7 * Copyright (C) 2004-2006 Atmel Corporation 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <mmc.h> 30 #include <part.h> 31 #include <malloc.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 #include <asm/byteorder.h> 35 #include <asm/arch/clk.h> 36 #include <asm/arch/hardware.h> 37 #include "atmel_mci.h" 38 39 #ifndef CONFIG_SYS_MMC_CLK_OD 40 # define CONFIG_SYS_MMC_CLK_OD 150000 41 #endif 42 43 #define MMC_DEFAULT_BLKLEN 512 44 45 #if defined(CONFIG_ATMEL_MCI_PORTB) 46 # define MCI_BUS 1 47 #else 48 # define MCI_BUS 0 49 #endif 50 51 static int initialized = 0; 52 53 /* 54 * Print command and status: 55 * 56 * - always when DEBUG is defined 57 * - on command errors 58 */ 59 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) 60 { 61 printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n", 62 cmdr, cmdr&0x3F, arg, status, msg); 63 } 64 65 /* Setup for MCI Clock and Block Size */ 66 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) 67 { 68 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; 69 u32 bus_hz = get_mci_clk_rate(); 70 u32 clkdiv = 255; 71 72 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n", 73 bus_hz, hz, blklen); 74 if (hz > 0) { 75 /* find lowest clkdiv yielding a rate <= than requested */ 76 for (clkdiv=0; clkdiv<255; clkdiv++) { 77 if ((bus_hz / (clkdiv+1) / 2) <= hz) 78 break; 79 } 80 } 81 printf("mci: setting clock %u Hz, block size %u\n", 82 (bus_hz / (clkdiv+1)) / 2, blklen); 83 84 blklen &= 0xfffc; 85 /* On some platforms RDPROOF and WRPROOF are ignored */ 86 writel((MMCI_BF(CLKDIV, clkdiv) 87 | MMCI_BF(BLKLEN, blklen) 88 | MMCI_BIT(RDPROOF) 89 | MMCI_BIT(WRPROOF)), &mci->mr); 90 /* 91 * On some new platforms BLKLEN in mci->mr is ignored. 92 * Should use the BLKLEN in the block register. 93 */ 94 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr); 95 initialized = 1; 96 } 97 98 /* Return the CMDR with flags for a given command and data packet */ 99 static u32 mci_encode_cmd( 100 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags) 101 { 102 u32 cmdr = 0; 103 104 /* Default Flags for Errors */ 105 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) | 106 MMCI_BIT(RINDE) | MMCI_BIT(RTOE)); 107 108 /* Default Flags for the Command */ 109 cmdr |= MMCI_BIT(MAXLAT); 110 111 if (data) { 112 cmdr |= MMCI_BF(TRCMD, 1); 113 if (data->blocks > 1) 114 cmdr |= MMCI_BF(TRTYP, 1); 115 if (data->flags & MMC_DATA_READ) 116 cmdr |= MMCI_BIT(TRDIR); 117 } 118 119 if (cmd->resp_type & MMC_RSP_CRC) 120 *error_flags |= MMCI_BIT(RCRCE); 121 if (cmd->resp_type & MMC_RSP_136) 122 cmdr |= MMCI_BF(RSPTYP, 2); 123 else if (cmd->resp_type & MMC_RSP_BUSY) 124 cmdr |= MMCI_BF(RSPTYP, 3); 125 else if (cmd->resp_type & MMC_RSP_PRESENT) 126 cmdr |= MMCI_BF(RSPTYP, 1); 127 128 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx); 129 } 130 131 /* Entered into function pointer in mci_send_cmd */ 132 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags) 133 { 134 u32 status; 135 136 do { 137 status = readl(&mci->sr); 138 if (status & (error_flags | MMCI_BIT(OVRE))) 139 goto io_fail; 140 } while (!(status & MMCI_BIT(RXRDY))); 141 142 if (status & MMCI_BIT(RXRDY)) { 143 *data = readl(&mci->rdr); 144 status = 0; 145 } 146 io_fail: 147 return status; 148 } 149 150 /* Entered into function pointer in mci_send_cmd */ 151 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags) 152 { 153 u32 status; 154 155 do { 156 status = readl(&mci->sr); 157 if (status & (error_flags | MMCI_BIT(UNRE))) 158 goto io_fail; 159 } while (!(status & MMCI_BIT(TXRDY))); 160 161 if (status & MMCI_BIT(TXRDY)) { 162 writel(*data, &mci->tdr); 163 status = 0; 164 } 165 io_fail: 166 return status; 167 } 168 169 /* 170 * Entered into mmc structure during driver init 171 * 172 * Sends a command out on the bus and deals with the block data. 173 * Takes the mmc pointer, a command pointer, and an optional data pointer. 174 */ 175 static int 176 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 177 { 178 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; 179 u32 cmdr; 180 u32 error_flags = 0; 181 u32 status; 182 183 if (!initialized) { 184 puts ("MCI not initialized!\n"); 185 return COMM_ERR; 186 } 187 188 /* Figure out the transfer arguments */ 189 cmdr = mci_encode_cmd(cmd, data, &error_flags); 190 191 /* For multi blocks read/write, set the block register */ 192 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) 193 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) 194 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len), 195 &mci->blkr); 196 197 /* Send the command */ 198 writel(cmd->cmdarg, &mci->argr); 199 writel(cmdr, &mci->cmdr); 200 201 #ifdef DEBUG 202 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG"); 203 #endif 204 205 /* Wait for the command to complete */ 206 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY))); 207 208 if (status & error_flags) { 209 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed"); 210 return COMM_ERR; 211 } 212 213 /* Copy the response to the response buffer */ 214 if (cmd->resp_type & MMC_RSP_136) { 215 cmd->response[0] = readl(&mci->rspr); 216 cmd->response[1] = readl(&mci->rspr1); 217 cmd->response[2] = readl(&mci->rspr2); 218 cmd->response[3] = readl(&mci->rspr3); 219 } else 220 cmd->response[0] = readl(&mci->rspr); 221 222 /* transfer all of the blocks */ 223 if (data) { 224 u32 word_count, block_count; 225 u32* ioptr; 226 u32 sys_blocksize, dummy, i; 227 u32 (*mci_data_op) 228 (atmel_mci_t *mci, u32* data, u32 error_flags); 229 230 if (data->flags & MMC_DATA_READ) { 231 mci_data_op = mci_data_read; 232 sys_blocksize = mmc->read_bl_len; 233 ioptr = (u32*)data->dest; 234 } else { 235 mci_data_op = mci_data_write; 236 sys_blocksize = mmc->write_bl_len; 237 ioptr = (u32*)data->src; 238 } 239 240 status = 0; 241 for (block_count = 0; 242 block_count < data->blocks && !status; 243 block_count++) { 244 word_count = 0; 245 do { 246 status = mci_data_op(mci, ioptr, error_flags); 247 word_count++; 248 ioptr++; 249 } while (!status && word_count < (data->blocksize/4)); 250 #ifdef DEBUG 251 if (data->flags & MMC_DATA_READ) 252 { 253 printf("Read Data:\n"); 254 print_buffer(0, data->dest, 1, 255 word_count*4, 0); 256 } 257 #endif 258 #ifdef DEBUG 259 if (!status && word_count < (sys_blocksize / 4)) 260 printf("filling rest of block...\n"); 261 #endif 262 /* fill the rest of a full block */ 263 while (!status && word_count < (sys_blocksize / 4)) { 264 status = mci_data_op(mci, &dummy, 265 error_flags); 266 word_count++; 267 } 268 if (status) { 269 dump_cmd(cmdr, cmd->cmdarg, status, 270 "Data Transfer Failed"); 271 return COMM_ERR; 272 } 273 } 274 275 /* Wait for Transfer End */ 276 i = 0; 277 do { 278 status = readl(&mci->sr); 279 280 if (status & error_flags) { 281 dump_cmd(cmdr, cmd->cmdarg, status, 282 "DTIP Wait Failed"); 283 return COMM_ERR; 284 } 285 i++; 286 } while ((status & MMCI_BIT(DTIP)) && i < 10000); 287 if (status & MMCI_BIT(DTIP)) { 288 dump_cmd(cmdr, cmd->cmdarg, status, 289 "XFER DTIP never unset, ignoring"); 290 } 291 } 292 293 return 0; 294 } 295 296 /* Entered into mmc structure during driver init */ 297 static void mci_set_ios(struct mmc *mmc) 298 { 299 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; 300 int busw = (mmc->bus_width == 4) ? 1 : 0; 301 302 /* Set the clock speed */ 303 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); 304 305 /* 306 * set the bus width and select slot for this interface 307 * there is no capability for multiple slots on the same interface yet 308 * Bitfield SCDBUS needs to be expanded to 2 bits for 8-bit buses 309 */ 310 writel(MMCI_BF(SCDBUS, busw) | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); 311 } 312 313 /* Entered into mmc structure during driver init */ 314 static int mci_init(struct mmc *mmc) 315 { 316 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; 317 318 /* Initialize controller */ 319 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ 320 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */ 321 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */ 322 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */ 323 324 /* This delay can be optimized, but stick with max value */ 325 writel(0x7f, &mci->dtor); 326 /* Disable Interrupts */ 327 writel(~0UL, &mci->idr); 328 329 /* Set default clocks and blocklen */ 330 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); 331 332 return 0; 333 } 334 335 /* 336 * This is the only exported function 337 * 338 * Call it with the MCI register base address 339 */ 340 int atmel_mci_init(void *regs) 341 { 342 struct mmc *mmc = malloc(sizeof(struct mmc)); 343 344 if (!mmc) 345 return -1; 346 strcpy(mmc->name, "mci"); 347 mmc->priv = regs; 348 mmc->send_cmd = mci_send_cmd; 349 mmc->set_ios = mci_set_ios; 350 mmc->init = mci_init; 351 mmc->getcd = NULL; 352 353 /* need to be able to pass these in on a board by board basis */ 354 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 355 mmc->host_caps = MMC_MODE_4BIT; 356 /* 357 * min and max frequencies determined by 358 * max and min of clock divider 359 */ 360 mmc->f_min = get_mci_clk_rate() / (2*256); 361 mmc->f_max = get_mci_clk_rate() / (2*1); 362 363 mmc->b_max = 0; 364 365 mmc_register(mmc); 366 367 return 0; 368 } 369