xref: /openbmc/u-boot/drivers/mmc/ftsdc010_mci.h (revision e8f80a5a)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2252185f2SRick Chen /*
3252185f2SRick Chen  * Faraday FTSDC010 Secure Digital Memory Card Host Controller
4252185f2SRick Chen  *
5252185f2SRick Chen  * Copyright (C) 2011 Andes Technology Corporation
6252185f2SRick Chen  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
7252185f2SRick Chen  */
8252185f2SRick Chen #include <mmc.h>
9252185f2SRick Chen 
10252185f2SRick Chen #ifndef __FTSDC010_MCI_H
11252185f2SRick Chen #define __FTSDC010_MCI_H
12252185f2SRick Chen 
13252185f2SRick Chen struct ftsdc010_chip {
14252185f2SRick Chen 	void __iomem *regs;
15252185f2SRick Chen 	uint32_t wprot;   /* write protected (locked) */
16252185f2SRick Chen 	uint32_t rate;    /* actual SD clock in Hz */
17252185f2SRick Chen 	uint32_t sclk;    /* FTSDC010 source clock in Hz */
18252185f2SRick Chen 	uint32_t fifo;    /* fifo depth in bytes */
19252185f2SRick Chen 	uint32_t acmd;
20252185f2SRick Chen 	struct mmc_config cfg;	/* mmc configuration */
21252185f2SRick Chen 	const char *name;
22252185f2SRick Chen 	void *ioaddr;
23252185f2SRick Chen 	unsigned int caps;
24252185f2SRick Chen 	unsigned int version;
25252185f2SRick Chen 	unsigned int clock;
26252185f2SRick Chen 	unsigned int bus_hz;
27252185f2SRick Chen 	unsigned int div;
28252185f2SRick Chen 	int dev_index;
29252185f2SRick Chen 	int dev_id;
30252185f2SRick Chen 	int buswidth;
31252185f2SRick Chen 	u32 fifoth_val;
32252185f2SRick Chen 	struct mmc *mmc;
33252185f2SRick Chen 	void *priv;
34252185f2SRick Chen 	bool fifo_mode;
35252185f2SRick Chen };
36252185f2SRick Chen 
37252185f2SRick Chen #endif /* __FTSDC010_MCI_H */
38