1 /* 2 * Faraday MMC/SD Host Controller 3 * 4 * (C) Copyright 2010 Faraday Technology 5 * Dante Su <dantesu@faraday-tech.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <part.h> 13 #include <mmc.h> 14 15 #include <asm/io.h> 16 #include <asm/errno.h> 17 #include <asm/byteorder.h> 18 #include <faraday/ftsdc010.h> 19 20 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ 21 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ 22 23 struct ftsdc010_chip { 24 void __iomem *regs; 25 uint32_t wprot; /* write protected (locked) */ 26 uint32_t rate; /* actual SD clock in Hz */ 27 uint32_t sclk; /* FTSDC010 source clock in Hz */ 28 uint32_t fifo; /* fifo depth in bytes */ 29 uint32_t acmd; 30 }; 31 32 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) 33 { 34 struct ftsdc010_chip *chip = mmc->priv; 35 struct ftsdc010_mmc __iomem *regs = chip->regs; 36 int ret = TIMEOUT; 37 uint32_t ts, st; 38 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); 39 uint32_t arg = mmc_cmd->cmdarg; 40 uint32_t flags = mmc_cmd->resp_type; 41 42 cmd |= FTSDC010_CMD_CMD_EN; 43 44 if (chip->acmd) { 45 cmd |= FTSDC010_CMD_APP_CMD; 46 chip->acmd = 0; 47 } 48 49 if (flags & MMC_RSP_PRESENT) 50 cmd |= FTSDC010_CMD_NEED_RSP; 51 52 if (flags & MMC_RSP_136) 53 cmd |= FTSDC010_CMD_LONG_RSP; 54 55 writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND, 56 ®s->clr); 57 writel(arg, ®s->argu); 58 writel(cmd, ®s->cmd); 59 60 if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) { 61 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { 62 if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) { 63 writel(FTSDC010_STATUS_CMD_SEND, ®s->clr); 64 ret = 0; 65 break; 66 } 67 } 68 } else { 69 st = 0; 70 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { 71 st = readl(®s->status); 72 writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr); 73 if (st & FTSDC010_STATUS_RSP_MASK) 74 break; 75 } 76 if (st & FTSDC010_STATUS_RSP_CRC_OK) { 77 if (flags & MMC_RSP_136) { 78 mmc_cmd->response[0] = readl(®s->rsp3); 79 mmc_cmd->response[1] = readl(®s->rsp2); 80 mmc_cmd->response[2] = readl(®s->rsp1); 81 mmc_cmd->response[3] = readl(®s->rsp0); 82 } else { 83 mmc_cmd->response[0] = readl(®s->rsp0); 84 } 85 ret = 0; 86 } else { 87 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n", 88 mmc_cmd->cmdidx, st); 89 } 90 } 91 92 if (ret) { 93 debug("ftsdc010: cmd timeout (op code=%d)\n", 94 mmc_cmd->cmdidx); 95 } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) { 96 chip->acmd = 1; 97 } 98 99 return ret; 100 } 101 102 static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) 103 { 104 struct ftsdc010_chip *chip = mmc->priv; 105 struct ftsdc010_mmc __iomem *regs = chip->regs; 106 uint32_t div; 107 108 for (div = 0; div < 0x7f; ++div) { 109 if (rate >= chip->sclk / (2 * (div + 1))) 110 break; 111 } 112 chip->rate = chip->sclk / (2 * (div + 1)); 113 114 writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr); 115 116 if (IS_SD(mmc)) { 117 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD); 118 119 if (chip->rate > 25000000) 120 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); 121 else 122 clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); 123 } 124 } 125 126 static inline int ftsdc010_is_ro(struct mmc *mmc) 127 { 128 struct ftsdc010_chip *chip = mmc->priv; 129 const uint8_t *csd = (const uint8_t *)mmc->csd; 130 131 return chip->wprot || (csd[1] & 0x30); 132 } 133 134 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) 135 { 136 int ret = TIMEOUT; 137 uint32_t st, ts; 138 139 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { 140 st = readl(®s->status); 141 if (!(st & mask)) 142 continue; 143 writel(st & mask, ®s->clr); 144 ret = 0; 145 break; 146 } 147 148 if (ret) 149 debug("ftsdc010: wait st(0x%x) timeout\n", mask); 150 151 return ret; 152 } 153 154 /* 155 * u-boot mmc api 156 */ 157 158 static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, 159 struct mmc_data *data) 160 { 161 int ret = UNUSABLE_ERR; 162 uint32_t len = 0; 163 struct ftsdc010_chip *chip = mmc->priv; 164 struct ftsdc010_mmc __iomem *regs = chip->regs; 165 166 if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) { 167 printf("ftsdc010: the card is write protected!\n"); 168 return ret; 169 } 170 171 if (data) { 172 uint32_t dcr; 173 174 len = data->blocksize * data->blocks; 175 176 /* 1. data disable + fifo reset */ 177 writel(FTSDC010_DCR_FIFO_RST, ®s->dcr); 178 179 /* 2. clear status register */ 180 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN 181 | FTSDC010_STATUS_FIFO_ORUN, ®s->clr); 182 183 /* 3. data timeout (1 sec) */ 184 writel(chip->rate, ®s->dtr); 185 186 /* 4. data length (bytes) */ 187 writel(len, ®s->dlr); 188 189 /* 5. data enable */ 190 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN; 191 if (data->flags & MMC_DATA_WRITE) 192 dcr |= FTSDC010_DCR_DATA_WRITE; 193 writel(dcr, ®s->dcr); 194 } 195 196 ret = ftsdc010_send_cmd(mmc, cmd); 197 if (ret) { 198 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx); 199 return ret; 200 } 201 202 if (!data) 203 return ret; 204 205 if (data->flags & MMC_DATA_WRITE) { 206 const uint8_t *buf = (const uint8_t *)data->src; 207 208 while (len > 0) { 209 int wlen; 210 211 /* wait for tx ready */ 212 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN); 213 if (ret) 214 break; 215 216 /* write bytes to ftsdc010 */ 217 for (wlen = 0; wlen < len && wlen < chip->fifo; ) { 218 writel(*(uint32_t *)buf, ®s->dwr); 219 buf += 4; 220 wlen += 4; 221 } 222 223 len -= wlen; 224 } 225 226 } else { 227 uint8_t *buf = (uint8_t *)data->dest; 228 229 while (len > 0) { 230 int rlen; 231 232 /* wait for rx ready */ 233 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN); 234 if (ret) 235 break; 236 237 /* fetch bytes from ftsdc010 */ 238 for (rlen = 0; rlen < len && rlen < chip->fifo; ) { 239 *(uint32_t *)buf = readl(®s->dwr); 240 buf += 4; 241 rlen += 4; 242 } 243 244 len -= rlen; 245 } 246 247 } 248 249 if (!ret) { 250 ret = ftsdc010_wait(regs, 251 FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR); 252 } 253 254 return ret; 255 } 256 257 static void ftsdc010_set_ios(struct mmc *mmc) 258 { 259 struct ftsdc010_chip *chip = mmc->priv; 260 struct ftsdc010_mmc __iomem *regs = chip->regs; 261 262 ftsdc010_clkset(mmc, mmc->clock); 263 264 clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK); 265 switch (mmc->bus_width) { 266 case 4: 267 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT); 268 break; 269 case 8: 270 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT); 271 break; 272 default: 273 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT); 274 break; 275 } 276 } 277 278 static int ftsdc010_init(struct mmc *mmc) 279 { 280 struct ftsdc010_chip *chip = mmc->priv; 281 struct ftsdc010_mmc __iomem *regs = chip->regs; 282 uint32_t ts; 283 284 if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT) 285 return NO_CARD_ERR; 286 287 if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) { 288 printf("ftsdc010: write protected\n"); 289 chip->wprot = 1; 290 } 291 292 chip->fifo = (readl(®s->feature) & 0xff) << 2; 293 294 /* 1. chip reset */ 295 writel(FTSDC010_CMD_SDC_RST, ®s->cmd); 296 for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) { 297 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) 298 continue; 299 break; 300 } 301 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) { 302 printf("ftsdc010: reset failed\n"); 303 return UNUSABLE_ERR; 304 } 305 306 /* 2. enter low speed mode (400k card detection) */ 307 ftsdc010_clkset(mmc, 400000); 308 309 /* 3. interrupt disabled */ 310 writel(0, ®s->int_mask); 311 312 return 0; 313 } 314 315 int ftsdc010_mmc_init(int devid) 316 { 317 struct mmc *mmc; 318 struct ftsdc010_chip *chip; 319 struct ftsdc010_mmc __iomem *regs; 320 #ifdef CONFIG_FTSDC010_BASE_LIST 321 uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST; 322 323 if (devid < 0 || devid >= ARRAY_SIZE(base_list)) 324 return -1; 325 regs = (void __iomem *)base_list[devid]; 326 #else 327 regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20)); 328 #endif 329 330 mmc = malloc(sizeof(struct mmc)); 331 if (!mmc) 332 return -ENOMEM; 333 memset(mmc, 0, sizeof(struct mmc)); 334 335 chip = malloc(sizeof(struct ftsdc010_chip)); 336 if (!chip) { 337 free(mmc); 338 return -ENOMEM; 339 } 340 memset(chip, 0, sizeof(struct ftsdc010_chip)); 341 342 chip->regs = regs; 343 mmc->priv = chip; 344 345 sprintf(mmc->name, "ftsdc010"); 346 mmc->send_cmd = ftsdc010_request; 347 mmc->set_ios = ftsdc010_set_ios; 348 mmc->init = ftsdc010_init; 349 350 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; 351 switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { 352 case FTSDC010_BWR_CAPS_4BIT: 353 mmc->host_caps |= MMC_MODE_4BIT; 354 break; 355 case FTSDC010_BWR_CAPS_8BIT: 356 mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 357 break; 358 default: 359 break; 360 } 361 362 #ifdef CONFIG_SYS_CLK_FREQ 363 chip->sclk = CONFIG_SYS_CLK_FREQ; 364 #else 365 chip->sclk = clk_get_rate("SDC"); 366 #endif 367 368 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 369 mmc->f_max = chip->sclk / 2; 370 mmc->f_min = chip->sclk / 0x100; 371 mmc->block_dev.part_type = PART_TYPE_DOS; 372 373 mmc_register(mmc); 374 375 return 0; 376 } 377