1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 char reserved1[8]; 62 uint fevt; 63 char reserved2[168]; 64 uint hostver; 65 char reserved3[780]; 66 uint scr; 67 }; 68 69 /* Return the XFERTYP flags for a given command and data packet */ 70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 71 { 72 uint xfertyp = 0; 73 74 if (data) { 75 xfertyp |= XFERTYP_DPSEL; 76 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 77 xfertyp |= XFERTYP_DMAEN; 78 #endif 79 if (data->blocks > 1) { 80 xfertyp |= XFERTYP_MSBSEL; 81 xfertyp |= XFERTYP_BCEN; 82 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 83 xfertyp |= XFERTYP_AC12EN; 84 #endif 85 } 86 87 if (data->flags & MMC_DATA_READ) 88 xfertyp |= XFERTYP_DTDSEL; 89 } 90 91 if (cmd->resp_type & MMC_RSP_CRC) 92 xfertyp |= XFERTYP_CCCEN; 93 if (cmd->resp_type & MMC_RSP_OPCODE) 94 xfertyp |= XFERTYP_CICEN; 95 if (cmd->resp_type & MMC_RSP_136) 96 xfertyp |= XFERTYP_RSPTYP_136; 97 else if (cmd->resp_type & MMC_RSP_BUSY) 98 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 99 else if (cmd->resp_type & MMC_RSP_PRESENT) 100 xfertyp |= XFERTYP_RSPTYP_48; 101 102 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 103 } 104 105 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 106 /* 107 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 108 */ 109 static void 110 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 111 { 112 struct fsl_esdhc *regs = mmc->priv; 113 uint blocks; 114 char *buffer; 115 uint databuf; 116 uint size; 117 uint irqstat; 118 uint timeout; 119 120 if (data->flags & MMC_DATA_READ) { 121 blocks = data->blocks; 122 buffer = data->dest; 123 while (blocks) { 124 timeout = PIO_TIMEOUT; 125 size = data->blocksize; 126 irqstat = esdhc_read32(®s->irqstat); 127 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 128 && --timeout); 129 if (timeout <= 0) { 130 printf("\nData Read Failed in PIO Mode."); 131 return; 132 } 133 while (size && (!(irqstat & IRQSTAT_TC))) { 134 udelay(100); /* Wait before last byte transfer complete */ 135 irqstat = esdhc_read32(®s->irqstat); 136 databuf = in_le32(®s->datport); 137 *((uint *)buffer) = databuf; 138 buffer += 4; 139 size -= 4; 140 } 141 blocks--; 142 } 143 } else { 144 blocks = data->blocks; 145 buffer = (char *)data->src; 146 while (blocks) { 147 timeout = PIO_TIMEOUT; 148 size = data->blocksize; 149 irqstat = esdhc_read32(®s->irqstat); 150 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 151 && --timeout); 152 if (timeout <= 0) { 153 printf("\nData Write Failed in PIO Mode."); 154 return; 155 } 156 while (size && (!(irqstat & IRQSTAT_TC))) { 157 udelay(100); /* Wait before last byte transfer complete */ 158 databuf = *((uint *)buffer); 159 buffer += 4; 160 size -= 4; 161 irqstat = esdhc_read32(®s->irqstat); 162 out_le32(®s->datport, databuf); 163 } 164 blocks--; 165 } 166 } 167 } 168 #endif 169 170 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 171 { 172 int timeout; 173 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 174 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 175 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 176 uint wml_value; 177 178 wml_value = data->blocksize/4; 179 180 if (data->flags & MMC_DATA_READ) { 181 if (wml_value > 0x10) 182 wml_value = 0x10; 183 184 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 185 esdhc_write32(®s->dsaddr, (u32)data->dest); 186 } else { 187 if (wml_value > 0x80) 188 wml_value = 0x80; 189 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 190 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 191 return TIMEOUT; 192 } 193 194 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 195 wml_value << 16); 196 esdhc_write32(®s->dsaddr, (u32)data->src); 197 } 198 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 199 if (!(data->flags & MMC_DATA_READ)) { 200 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 201 printf("\nThe SD card is locked. " 202 "Can not write to a locked card.\n\n"); 203 return TIMEOUT; 204 } 205 esdhc_write32(®s->dsaddr, (u32)data->src); 206 } else 207 esdhc_write32(®s->dsaddr, (u32)data->dest); 208 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 209 210 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 211 212 /* Calculate the timeout period for data transactions */ 213 timeout = fls(mmc->tran_speed/10) - 1; 214 timeout -= 13; 215 216 if (timeout > 14) 217 timeout = 14; 218 219 if (timeout < 0) 220 timeout = 0; 221 222 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 223 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 224 timeout++; 225 #endif 226 227 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 228 229 return 0; 230 } 231 232 233 /* 234 * Sends a command out on the bus. Takes the mmc pointer, 235 * a command pointer, and an optional data pointer. 236 */ 237 static int 238 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 239 { 240 uint xfertyp; 241 uint irqstat; 242 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 243 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 244 245 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 246 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 247 return 0; 248 #endif 249 250 esdhc_write32(®s->irqstat, -1); 251 252 sync(); 253 254 /* Wait for the bus to be idle */ 255 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 256 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 257 ; 258 259 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 260 ; 261 262 /* Wait at least 8 SD clock cycles before the next command */ 263 /* 264 * Note: This is way more than 8 cycles, but 1ms seems to 265 * resolve timing issues with some cards 266 */ 267 udelay(1000); 268 269 /* Set up for a data transfer if we have one */ 270 if (data) { 271 int err; 272 273 err = esdhc_setup_data(mmc, data); 274 if(err) 275 return err; 276 } 277 278 /* Figure out the transfer arguments */ 279 xfertyp = esdhc_xfertyp(cmd, data); 280 281 /* Send the command */ 282 esdhc_write32(®s->cmdarg, cmd->cmdarg); 283 esdhc_write32(®s->xfertyp, xfertyp); 284 285 /* Wait for the command to complete */ 286 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) 287 ; 288 289 irqstat = esdhc_read32(®s->irqstat); 290 esdhc_write32(®s->irqstat, irqstat); 291 292 if (irqstat & CMD_ERR) 293 return COMM_ERR; 294 295 if (irqstat & IRQSTAT_CTOE) 296 return TIMEOUT; 297 298 /* Copy the response to the response buffer */ 299 if (cmd->resp_type & MMC_RSP_136) { 300 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 301 302 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 303 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 304 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 305 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 306 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 307 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 308 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 309 cmd->response[3] = (cmdrsp0 << 8); 310 } else 311 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 312 313 /* Wait until all of the blocks are transferred */ 314 if (data) { 315 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 316 esdhc_pio_read_write(mmc, data); 317 #else 318 do { 319 irqstat = esdhc_read32(®s->irqstat); 320 321 if (irqstat & DATA_ERR) 322 return COMM_ERR; 323 324 if (irqstat & IRQSTAT_DTOE) 325 return TIMEOUT; 326 } while (!(irqstat & IRQSTAT_TC) && 327 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); 328 #endif 329 } 330 331 esdhc_write32(®s->irqstat, -1); 332 333 return 0; 334 } 335 336 void set_sysctl(struct mmc *mmc, uint clock) 337 { 338 int sdhc_clk = gd->sdhc_clk; 339 int div, pre_div; 340 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 341 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 342 uint clk; 343 344 if (clock < mmc->f_min) 345 clock = mmc->f_min; 346 347 if (sdhc_clk / 16 > clock) { 348 for (pre_div = 2; pre_div < 256; pre_div *= 2) 349 if ((sdhc_clk / pre_div) <= (clock * 16)) 350 break; 351 } else 352 pre_div = 2; 353 354 for (div = 1; div <= 16; div++) 355 if ((sdhc_clk / (div * pre_div)) <= clock) 356 break; 357 358 pre_div >>= 1; 359 div -= 1; 360 361 clk = (pre_div << 8) | (div << 4); 362 363 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 364 365 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 366 367 udelay(10000); 368 369 clk = SYSCTL_PEREN | SYSCTL_CKEN; 370 371 esdhc_setbits32(®s->sysctl, clk); 372 } 373 374 static void esdhc_set_ios(struct mmc *mmc) 375 { 376 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 377 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 378 379 /* Set the clock speed */ 380 set_sysctl(mmc, mmc->clock); 381 382 /* Set the bus width */ 383 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 384 385 if (mmc->bus_width == 4) 386 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 387 else if (mmc->bus_width == 8) 388 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 389 390 } 391 392 static int esdhc_init(struct mmc *mmc) 393 { 394 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 395 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 396 int timeout = 1000; 397 int ret = 0; 398 u8 card_absent; 399 400 /* Reset the entire host controller */ 401 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 402 403 /* Wait until the controller is available */ 404 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 405 udelay(1000); 406 407 /* Enable cache snooping */ 408 if (cfg && !cfg->no_snoop) 409 esdhc_write32(®s->scr, 0x00000040); 410 411 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 412 413 /* Set the initial clock speed */ 414 mmc_set_clock(mmc, 400000); 415 416 /* Disable the BRR and BWR bits in IRQSTAT */ 417 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 418 419 /* Put the PROCTL reg back to the default */ 420 esdhc_write32(®s->proctl, PROCTL_INIT); 421 422 /* Set timout to the maximum value */ 423 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 424 425 /* Check if there is a callback for detecting the card */ 426 if (board_mmc_getcd(&card_absent, mmc)) { 427 timeout = 1000; 428 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && 429 --timeout) 430 udelay(1000); 431 432 if (timeout <= 0) 433 ret = NO_CARD_ERR; 434 } else { 435 if (card_absent) 436 ret = NO_CARD_ERR; 437 } 438 439 return ret; 440 } 441 442 static void esdhc_reset(struct fsl_esdhc *regs) 443 { 444 unsigned long timeout = 100; /* wait max 100 ms */ 445 446 /* reset the controller */ 447 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 448 449 /* hardware clears the bit when it is done */ 450 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 451 udelay(1000); 452 if (!timeout) 453 printf("MMC/SD: Reset never completed.\n"); 454 } 455 456 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 457 { 458 struct fsl_esdhc *regs; 459 struct mmc *mmc; 460 u32 caps, voltage_caps; 461 462 if (!cfg) 463 return -1; 464 465 mmc = malloc(sizeof(struct mmc)); 466 467 sprintf(mmc->name, "FSL_ESDHC"); 468 regs = (struct fsl_esdhc *)cfg->esdhc_base; 469 470 /* First reset the eSDHC controller */ 471 esdhc_reset(regs); 472 473 mmc->priv = cfg; 474 mmc->send_cmd = esdhc_send_cmd; 475 mmc->set_ios = esdhc_set_ios; 476 mmc->init = esdhc_init; 477 478 voltage_caps = 0; 479 caps = regs->hostcapblt; 480 481 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 482 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 483 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 484 #endif 485 if (caps & ESDHC_HOSTCAPBLT_VS18) 486 voltage_caps |= MMC_VDD_165_195; 487 if (caps & ESDHC_HOSTCAPBLT_VS30) 488 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 489 if (caps & ESDHC_HOSTCAPBLT_VS33) 490 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 491 492 #ifdef CONFIG_SYS_SD_VOLTAGE 493 mmc->voltages = CONFIG_SYS_SD_VOLTAGE; 494 #else 495 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 496 #endif 497 if ((mmc->voltages & voltage_caps) == 0) { 498 printf("voltage not supported by controller\n"); 499 return -1; 500 } 501 502 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 503 504 if (caps & ESDHC_HOSTCAPBLT_HSS) 505 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 506 507 mmc->f_min = 400000; 508 mmc->f_max = MIN(gd->sdhc_clk, 52000000); 509 510 mmc_register(mmc); 511 512 return 0; 513 } 514 515 int fsl_esdhc_mmc_init(bd_t *bis) 516 { 517 struct fsl_esdhc_cfg *cfg; 518 519 cfg = malloc(sizeof(struct fsl_esdhc_cfg)); 520 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); 521 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 522 return fsl_esdhc_initialize(bis, cfg); 523 } 524 525 #ifdef CONFIG_OF_LIBFDT 526 void fdt_fixup_esdhc(void *blob, bd_t *bd) 527 { 528 const char *compat = "fsl,esdhc"; 529 530 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 531 if (!hwconfig("esdhc")) { 532 do_fixup_by_compat(blob, compat, "status", "disabled", 533 8 + 1, 1); 534 return; 535 } 536 #endif 537 538 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 539 gd->sdhc_clk, 1); 540 541 do_fixup_by_compat(blob, compat, "status", "okay", 542 4 + 1, 1); 543 } 544 #endif 545