1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 4 * Andy Fleming 5 * 6 * Based vaguely on the pxa mmc code: 7 * (C) Copyright 2003 8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <command.h> 14 #include <errno.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <power/regulator.h> 19 #include <malloc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 #include <dm.h> 24 #include <asm-generic/gpio.h> 25 #include <dm/pinctrl.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 30 IRQSTATEN_CINT | \ 31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 34 IRQSTATEN_DINT) 35 #define MAX_TUNING_LOOP 40 36 37 struct fsl_esdhc { 38 uint dsaddr; /* SDMA system address register */ 39 uint blkattr; /* Block attributes register */ 40 uint cmdarg; /* Command argument register */ 41 uint xfertyp; /* Transfer type register */ 42 uint cmdrsp0; /* Command response 0 register */ 43 uint cmdrsp1; /* Command response 1 register */ 44 uint cmdrsp2; /* Command response 2 register */ 45 uint cmdrsp3; /* Command response 3 register */ 46 uint datport; /* Buffer data port register */ 47 uint prsstat; /* Present state register */ 48 uint proctl; /* Protocol control register */ 49 uint sysctl; /* System Control Register */ 50 uint irqstat; /* Interrupt status register */ 51 uint irqstaten; /* Interrupt status enable register */ 52 uint irqsigen; /* Interrupt signal enable register */ 53 uint autoc12err; /* Auto CMD error status register */ 54 uint hostcapblt; /* Host controller capabilities register */ 55 uint wml; /* Watermark level register */ 56 uint mixctrl; /* For USDHC */ 57 char reserved1[4]; /* reserved */ 58 uint fevt; /* Force event register */ 59 uint admaes; /* ADMA error status register */ 60 uint adsaddr; /* ADMA system address register */ 61 char reserved2[4]; 62 uint dllctrl; 63 uint dllstat; 64 uint clktunectrlstatus; 65 char reserved3[4]; 66 uint strobe_dllctrl; 67 uint strobe_dllstat; 68 char reserved4[72]; 69 uint vendorspec; 70 uint mmcboot; 71 uint vendorspec2; 72 uint tuning_ctrl; /* on i.MX6/7/8 */ 73 char reserved5[44]; 74 uint hostver; /* Host controller version register */ 75 char reserved6[4]; /* reserved */ 76 uint dmaerraddr; /* DMA error address register */ 77 char reserved7[4]; /* reserved */ 78 uint dmaerrattr; /* DMA error attribute register */ 79 char reserved8[4]; /* reserved */ 80 uint hostcapblt2; /* Host controller capabilities register 2 */ 81 char reserved9[8]; /* reserved */ 82 uint tcr; /* Tuning control register */ 83 char reserved10[28]; /* reserved */ 84 uint sddirctl; /* SD direction control register */ 85 char reserved11[712];/* reserved */ 86 uint scr; /* eSDHC control register */ 87 }; 88 89 struct fsl_esdhc_plat { 90 struct mmc_config cfg; 91 struct mmc mmc; 92 }; 93 94 struct esdhc_soc_data { 95 u32 flags; 96 u32 caps; 97 }; 98 99 /** 100 * struct fsl_esdhc_priv 101 * 102 * @esdhc_regs: registers of the sdhc controller 103 * @sdhc_clk: Current clk of the sdhc controller 104 * @bus_width: bus width, 1bit, 4bit or 8bit 105 * @cfg: mmc config 106 * @mmc: mmc 107 * Following is used when Driver Model is enabled for MMC 108 * @dev: pointer for the device 109 * @non_removable: 0: removable; 1: non-removable 110 * @wp_enable: 1: enable checking wp; 0: no check 111 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 112 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h 113 * @caps: controller capabilities 114 * @tuning_step: tuning step setting in tuning_ctrl register 115 * @start_tuning_tap: the start point for tuning in tuning_ctrl register 116 * @strobe_dll_delay_target: settings in strobe_dllctrl 117 * @signal_voltage: indicating the current voltage 118 * @cd_gpio: gpio for card detection 119 * @wp_gpio: gpio for write protection 120 */ 121 struct fsl_esdhc_priv { 122 struct fsl_esdhc *esdhc_regs; 123 unsigned int sdhc_clk; 124 unsigned int clock; 125 unsigned int mode; 126 unsigned int bus_width; 127 #if !CONFIG_IS_ENABLED(BLK) 128 struct mmc *mmc; 129 #endif 130 struct udevice *dev; 131 int non_removable; 132 int wp_enable; 133 int vs18_enable; 134 u32 flags; 135 u32 caps; 136 u32 tuning_step; 137 u32 tuning_start_tap; 138 u32 strobe_dll_delay_target; 139 u32 signal_voltage; 140 #if IS_ENABLED(CONFIG_DM_REGULATOR) 141 struct udevice *vqmmc_dev; 142 struct udevice *vmmc_dev; 143 #endif 144 #ifdef CONFIG_DM_GPIO 145 struct gpio_desc cd_gpio; 146 struct gpio_desc wp_gpio; 147 #endif 148 }; 149 150 /* Return the XFERTYP flags for a given command and data packet */ 151 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 152 { 153 uint xfertyp = 0; 154 155 if (data) { 156 xfertyp |= XFERTYP_DPSEL; 157 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 158 xfertyp |= XFERTYP_DMAEN; 159 #endif 160 if (data->blocks > 1) { 161 xfertyp |= XFERTYP_MSBSEL; 162 xfertyp |= XFERTYP_BCEN; 163 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 164 xfertyp |= XFERTYP_AC12EN; 165 #endif 166 } 167 168 if (data->flags & MMC_DATA_READ) 169 xfertyp |= XFERTYP_DTDSEL; 170 } 171 172 if (cmd->resp_type & MMC_RSP_CRC) 173 xfertyp |= XFERTYP_CCCEN; 174 if (cmd->resp_type & MMC_RSP_OPCODE) 175 xfertyp |= XFERTYP_CICEN; 176 if (cmd->resp_type & MMC_RSP_136) 177 xfertyp |= XFERTYP_RSPTYP_136; 178 else if (cmd->resp_type & MMC_RSP_BUSY) 179 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 180 else if (cmd->resp_type & MMC_RSP_PRESENT) 181 xfertyp |= XFERTYP_RSPTYP_48; 182 183 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 184 xfertyp |= XFERTYP_CMDTYP_ABORT; 185 186 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 187 } 188 189 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 190 /* 191 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 192 */ 193 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 194 struct mmc_data *data) 195 { 196 struct fsl_esdhc *regs = priv->esdhc_regs; 197 uint blocks; 198 char *buffer; 199 uint databuf; 200 uint size; 201 uint irqstat; 202 ulong start; 203 204 if (data->flags & MMC_DATA_READ) { 205 blocks = data->blocks; 206 buffer = data->dest; 207 while (blocks) { 208 start = get_timer(0); 209 size = data->blocksize; 210 irqstat = esdhc_read32(®s->irqstat); 211 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { 212 if (get_timer(start) > PIO_TIMEOUT) { 213 printf("\nData Read Failed in PIO Mode."); 214 return; 215 } 216 } 217 while (size && (!(irqstat & IRQSTAT_TC))) { 218 udelay(100); /* Wait before last byte transfer complete */ 219 irqstat = esdhc_read32(®s->irqstat); 220 databuf = in_le32(®s->datport); 221 *((uint *)buffer) = databuf; 222 buffer += 4; 223 size -= 4; 224 } 225 blocks--; 226 } 227 } else { 228 blocks = data->blocks; 229 buffer = (char *)data->src; 230 while (blocks) { 231 start = get_timer(0); 232 size = data->blocksize; 233 irqstat = esdhc_read32(®s->irqstat); 234 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { 235 if (get_timer(start) > PIO_TIMEOUT) { 236 printf("\nData Write Failed in PIO Mode."); 237 return; 238 } 239 } 240 while (size && (!(irqstat & IRQSTAT_TC))) { 241 udelay(100); /* Wait before last byte transfer complete */ 242 databuf = *((uint *)buffer); 243 buffer += 4; 244 size -= 4; 245 irqstat = esdhc_read32(®s->irqstat); 246 out_le32(®s->datport, databuf); 247 } 248 blocks--; 249 } 250 } 251 } 252 #endif 253 254 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 255 struct mmc_data *data) 256 { 257 int timeout; 258 struct fsl_esdhc *regs = priv->esdhc_regs; 259 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 260 defined(CONFIG_MX8M) 261 dma_addr_t addr; 262 #endif 263 uint wml_value; 264 265 wml_value = data->blocksize/4; 266 267 if (data->flags & MMC_DATA_READ) { 268 if (wml_value > WML_RD_WML_MAX) 269 wml_value = WML_RD_WML_MAX_VAL; 270 271 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 272 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 273 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 274 defined(CONFIG_MX8M) 275 addr = virt_to_phys((void *)(data->dest)); 276 if (upper_32_bits(addr)) 277 printf("Error found for upper 32 bits\n"); 278 else 279 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 280 #else 281 esdhc_write32(®s->dsaddr, (u32)data->dest); 282 #endif 283 #endif 284 } else { 285 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 286 flush_dcache_range((ulong)data->src, 287 (ulong)data->src+data->blocks 288 *data->blocksize); 289 #endif 290 if (wml_value > WML_WR_WML_MAX) 291 wml_value = WML_WR_WML_MAX_VAL; 292 if (priv->wp_enable) { 293 if ((esdhc_read32(®s->prsstat) & 294 PRSSTAT_WPSPL) == 0) { 295 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 296 return -ETIMEDOUT; 297 } 298 } 299 300 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 301 wml_value << 16); 302 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 303 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 304 defined(CONFIG_MX8M) 305 addr = virt_to_phys((void *)(data->src)); 306 if (upper_32_bits(addr)) 307 printf("Error found for upper 32 bits\n"); 308 else 309 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 310 #else 311 esdhc_write32(®s->dsaddr, (u32)data->src); 312 #endif 313 #endif 314 } 315 316 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 317 318 /* Calculate the timeout period for data transactions */ 319 /* 320 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 321 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 322 * So, Number of SD Clock cycles for 0.25sec should be minimum 323 * (SD Clock/sec * 0.25 sec) SD Clock cycles 324 * = (mmc->clock * 1/4) SD Clock cycles 325 * As 1) >= 2) 326 * => (2^(timeout+13)) >= mmc->clock * 1/4 327 * Taking log2 both the sides 328 * => timeout + 13 >= log2(mmc->clock/4) 329 * Rounding up to next power of 2 330 * => timeout + 13 = log2(mmc->clock/4) + 1 331 * => timeout + 13 = fls(mmc->clock/4) 332 * 333 * However, the MMC spec "It is strongly recommended for hosts to 334 * implement more than 500ms timeout value even if the card 335 * indicates the 250ms maximum busy length." Even the previous 336 * value of 300ms is known to be insufficient for some cards. 337 * So, we use 338 * => timeout + 13 = fls(mmc->clock/2) 339 */ 340 timeout = fls(mmc->clock/2); 341 timeout -= 13; 342 343 if (timeout > 14) 344 timeout = 14; 345 346 if (timeout < 0) 347 timeout = 0; 348 349 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 350 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 351 timeout++; 352 #endif 353 354 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 355 timeout = 0xE; 356 #endif 357 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 358 359 return 0; 360 } 361 362 static void check_and_invalidate_dcache_range 363 (struct mmc_cmd *cmd, 364 struct mmc_data *data) { 365 unsigned start = 0; 366 unsigned end = 0; 367 unsigned size = roundup(ARCH_DMA_MINALIGN, 368 data->blocks*data->blocksize); 369 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 370 defined(CONFIG_MX8M) 371 dma_addr_t addr; 372 373 addr = virt_to_phys((void *)(data->dest)); 374 if (upper_32_bits(addr)) 375 printf("Error found for upper 32 bits\n"); 376 else 377 start = lower_32_bits(addr); 378 #else 379 start = (unsigned)data->dest; 380 #endif 381 end = start + size; 382 invalidate_dcache_range(start, end); 383 } 384 385 /* 386 * Sends a command out on the bus. Takes the mmc pointer, 387 * a command pointer, and an optional data pointer. 388 */ 389 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, 390 struct mmc_cmd *cmd, struct mmc_data *data) 391 { 392 int err = 0; 393 uint xfertyp; 394 uint irqstat; 395 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; 396 struct fsl_esdhc *regs = priv->esdhc_regs; 397 398 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 399 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 400 return 0; 401 #endif 402 403 esdhc_write32(®s->irqstat, -1); 404 405 sync(); 406 407 /* Wait for the bus to be idle */ 408 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 409 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 410 ; 411 412 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 413 ; 414 415 /* Wait at least 8 SD clock cycles before the next command */ 416 /* 417 * Note: This is way more than 8 cycles, but 1ms seems to 418 * resolve timing issues with some cards 419 */ 420 udelay(1000); 421 422 /* Set up for a data transfer if we have one */ 423 if (data) { 424 err = esdhc_setup_data(priv, mmc, data); 425 if(err) 426 return err; 427 428 if (data->flags & MMC_DATA_READ) 429 check_and_invalidate_dcache_range(cmd, data); 430 } 431 432 /* Figure out the transfer arguments */ 433 xfertyp = esdhc_xfertyp(cmd, data); 434 435 /* Mask all irqs */ 436 esdhc_write32(®s->irqsigen, 0); 437 438 /* Send the command */ 439 esdhc_write32(®s->cmdarg, cmd->cmdarg); 440 #if defined(CONFIG_FSL_USDHC) 441 esdhc_write32(®s->mixctrl, 442 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 443 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 444 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 445 #else 446 esdhc_write32(®s->xfertyp, xfertyp); 447 #endif 448 449 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 450 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) 451 flags = IRQSTAT_BRR; 452 453 /* Wait for the command to complete */ 454 while (!(esdhc_read32(®s->irqstat) & flags)) 455 ; 456 457 irqstat = esdhc_read32(®s->irqstat); 458 459 if (irqstat & CMD_ERR) { 460 err = -ECOMM; 461 goto out; 462 } 463 464 if (irqstat & IRQSTAT_CTOE) { 465 err = -ETIMEDOUT; 466 goto out; 467 } 468 469 /* Switch voltage to 1.8V if CMD11 succeeded */ 470 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 471 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 472 473 printf("Run CMD11 1.8V switch\n"); 474 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 475 udelay(5000); 476 } 477 478 /* Workaround for ESDHC errata ENGcm03648 */ 479 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 480 int timeout = 6000; 481 482 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 483 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 484 PRSSTAT_DAT0)) { 485 udelay(100); 486 timeout--; 487 } 488 489 if (timeout <= 0) { 490 printf("Timeout waiting for DAT0 to go high!\n"); 491 err = -ETIMEDOUT; 492 goto out; 493 } 494 } 495 496 /* Copy the response to the response buffer */ 497 if (cmd->resp_type & MMC_RSP_136) { 498 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 499 500 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 501 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 502 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 503 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 504 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 505 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 506 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 507 cmd->response[3] = (cmdrsp0 << 8); 508 } else 509 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 510 511 /* Wait until all of the blocks are transferred */ 512 if (data) { 513 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 514 esdhc_pio_read_write(priv, data); 515 #else 516 flags = DATA_COMPLETE; 517 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 518 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) { 519 flags = IRQSTAT_BRR; 520 } 521 522 do { 523 irqstat = esdhc_read32(®s->irqstat); 524 525 if (irqstat & IRQSTAT_DTOE) { 526 err = -ETIMEDOUT; 527 goto out; 528 } 529 530 if (irqstat & DATA_ERR) { 531 err = -ECOMM; 532 goto out; 533 } 534 } while ((irqstat & flags) != flags); 535 536 /* 537 * Need invalidate the dcache here again to avoid any 538 * cache-fill during the DMA operations such as the 539 * speculative pre-fetching etc. 540 */ 541 if (data->flags & MMC_DATA_READ) 542 check_and_invalidate_dcache_range(cmd, data); 543 #endif 544 } 545 546 out: 547 /* Reset CMD and DATA portions on error */ 548 if (err) { 549 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 550 SYSCTL_RSTC); 551 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 552 ; 553 554 if (data) { 555 esdhc_write32(®s->sysctl, 556 esdhc_read32(®s->sysctl) | 557 SYSCTL_RSTD); 558 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 559 ; 560 } 561 562 /* If this was CMD11, then notify that power cycle is needed */ 563 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 564 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 565 } 566 567 esdhc_write32(®s->irqstat, -1); 568 569 return err; 570 } 571 572 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 573 { 574 struct fsl_esdhc *regs = priv->esdhc_regs; 575 int div = 1; 576 #ifdef ARCH_MXC 577 #ifdef CONFIG_MX53 578 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 579 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; 580 #else 581 int pre_div = 1; 582 #endif 583 #else 584 int pre_div = 2; 585 #endif 586 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 587 int sdhc_clk = priv->sdhc_clk; 588 uint clk; 589 590 if (clock < mmc->cfg->f_min) 591 clock = mmc->cfg->f_min; 592 593 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 594 pre_div *= 2; 595 596 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 597 div++; 598 599 pre_div >>= 1; 600 div -= 1; 601 602 clk = (pre_div << 8) | (div << 4); 603 604 #ifdef CONFIG_FSL_USDHC 605 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 606 #else 607 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 608 #endif 609 610 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 611 612 udelay(10000); 613 614 #ifdef CONFIG_FSL_USDHC 615 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 616 #else 617 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 618 #endif 619 620 priv->clock = clock; 621 } 622 623 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 624 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 625 { 626 struct fsl_esdhc *regs = priv->esdhc_regs; 627 u32 value; 628 u32 time_out; 629 630 value = esdhc_read32(®s->sysctl); 631 632 if (enable) 633 value |= SYSCTL_CKEN; 634 else 635 value &= ~SYSCTL_CKEN; 636 637 esdhc_write32(®s->sysctl, value); 638 639 time_out = 20; 640 value = PRSSTAT_SDSTB; 641 while (!(esdhc_read32(®s->prsstat) & value)) { 642 if (time_out == 0) { 643 printf("fsl_esdhc: Internal clock never stabilised.\n"); 644 break; 645 } 646 time_out--; 647 mdelay(1); 648 } 649 } 650 #endif 651 652 #ifdef MMC_SUPPORTS_TUNING 653 static int esdhc_change_pinstate(struct udevice *dev) 654 { 655 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 656 int ret; 657 658 switch (priv->mode) { 659 case UHS_SDR50: 660 case UHS_DDR50: 661 ret = pinctrl_select_state(dev, "state_100mhz"); 662 break; 663 case UHS_SDR104: 664 case MMC_HS_200: 665 case MMC_HS_400: 666 ret = pinctrl_select_state(dev, "state_200mhz"); 667 break; 668 default: 669 ret = pinctrl_select_state(dev, "default"); 670 break; 671 } 672 673 if (ret) 674 printf("%s %d error\n", __func__, priv->mode); 675 676 return ret; 677 } 678 679 static void esdhc_reset_tuning(struct mmc *mmc) 680 { 681 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 682 struct fsl_esdhc *regs = priv->esdhc_regs; 683 684 if (priv->flags & ESDHC_FLAG_USDHC) { 685 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 686 esdhc_clrbits32(®s->autoc12err, 687 MIX_CTRL_SMPCLK_SEL | 688 MIX_CTRL_EXE_TUNE); 689 } 690 } 691 } 692 693 static void esdhc_set_strobe_dll(struct mmc *mmc) 694 { 695 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 696 struct fsl_esdhc *regs = priv->esdhc_regs; 697 u32 val; 698 699 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { 700 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl); 701 702 /* 703 * enable strobe dll ctrl and adjust the delay target 704 * for the uSDHC loopback read clock 705 */ 706 val = ESDHC_STROBE_DLL_CTRL_ENABLE | 707 (priv->strobe_dll_delay_target << 708 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 709 writel(val, ®s->strobe_dllctrl); 710 /* wait 1us to make sure strobe dll status register stable */ 711 mdelay(1); 712 val = readl(®s->strobe_dllstat); 713 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) 714 pr_warn("HS400 strobe DLL status REF not lock!\n"); 715 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 716 pr_warn("HS400 strobe DLL status SLV not lock!\n"); 717 } 718 } 719 720 static int esdhc_set_timing(struct mmc *mmc) 721 { 722 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 723 struct fsl_esdhc *regs = priv->esdhc_regs; 724 u32 mixctrl; 725 726 mixctrl = readl(®s->mixctrl); 727 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); 728 729 switch (mmc->selected_mode) { 730 case MMC_LEGACY: 731 case SD_LEGACY: 732 esdhc_reset_tuning(mmc); 733 writel(mixctrl, ®s->mixctrl); 734 break; 735 case MMC_HS_400: 736 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; 737 writel(mixctrl, ®s->mixctrl); 738 esdhc_set_strobe_dll(mmc); 739 break; 740 case MMC_HS: 741 case MMC_HS_52: 742 case MMC_HS_200: 743 case SD_HS: 744 case UHS_SDR12: 745 case UHS_SDR25: 746 case UHS_SDR50: 747 case UHS_SDR104: 748 writel(mixctrl, ®s->mixctrl); 749 break; 750 case UHS_DDR50: 751 case MMC_DDR_52: 752 mixctrl |= MIX_CTRL_DDREN; 753 writel(mixctrl, ®s->mixctrl); 754 break; 755 default: 756 printf("Not supported %d\n", mmc->selected_mode); 757 return -EINVAL; 758 } 759 760 priv->mode = mmc->selected_mode; 761 762 return esdhc_change_pinstate(mmc->dev); 763 } 764 765 static int esdhc_set_voltage(struct mmc *mmc) 766 { 767 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 768 struct fsl_esdhc *regs = priv->esdhc_regs; 769 int ret; 770 771 priv->signal_voltage = mmc->signal_voltage; 772 switch (mmc->signal_voltage) { 773 case MMC_SIGNAL_VOLTAGE_330: 774 if (priv->vs18_enable) 775 return -EIO; 776 #ifdef CONFIG_DM_REGULATOR 777 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 778 ret = regulator_set_value(priv->vqmmc_dev, 3300000); 779 if (ret) { 780 printf("Setting to 3.3V error"); 781 return -EIO; 782 } 783 /* Wait for 5ms */ 784 mdelay(5); 785 } 786 #endif 787 788 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 789 if (!(esdhc_read32(®s->vendorspec) & 790 ESDHC_VENDORSPEC_VSELECT)) 791 return 0; 792 793 return -EAGAIN; 794 case MMC_SIGNAL_VOLTAGE_180: 795 #ifdef CONFIG_DM_REGULATOR 796 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 797 ret = regulator_set_value(priv->vqmmc_dev, 1800000); 798 if (ret) { 799 printf("Setting to 1.8V error"); 800 return -EIO; 801 } 802 } 803 #endif 804 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 805 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) 806 return 0; 807 808 return -EAGAIN; 809 case MMC_SIGNAL_VOLTAGE_120: 810 return -ENOTSUPP; 811 default: 812 return 0; 813 } 814 } 815 816 static void esdhc_stop_tuning(struct mmc *mmc) 817 { 818 struct mmc_cmd cmd; 819 820 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 821 cmd.cmdarg = 0; 822 cmd.resp_type = MMC_RSP_R1b; 823 824 dm_mmc_send_cmd(mmc->dev, &cmd, NULL); 825 } 826 827 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) 828 { 829 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 830 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 831 struct fsl_esdhc *regs = priv->esdhc_regs; 832 struct mmc *mmc = &plat->mmc; 833 u32 irqstaten = readl(®s->irqstaten); 834 u32 irqsigen = readl(®s->irqsigen); 835 int i, ret = -ETIMEDOUT; 836 u32 val, mixctrl; 837 838 /* clock tuning is not needed for upto 52MHz */ 839 if (mmc->clock <= 52000000) 840 return 0; 841 842 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ 843 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 844 val = readl(®s->autoc12err); 845 mixctrl = readl(®s->mixctrl); 846 val &= ~MIX_CTRL_SMPCLK_SEL; 847 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); 848 849 val |= MIX_CTRL_EXE_TUNE; 850 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; 851 852 writel(val, ®s->autoc12err); 853 writel(mixctrl, ®s->mixctrl); 854 } 855 856 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ 857 mixctrl = readl(®s->mixctrl); 858 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); 859 writel(mixctrl, ®s->mixctrl); 860 861 writel(IRQSTATEN_BRR, ®s->irqstaten); 862 writel(IRQSTATEN_BRR, ®s->irqsigen); 863 864 /* 865 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 866 * of loops reaches 40 times. 867 */ 868 for (i = 0; i < MAX_TUNING_LOOP; i++) { 869 u32 ctrl; 870 871 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { 872 if (mmc->bus_width == 8) 873 writel(0x7080, ®s->blkattr); 874 else if (mmc->bus_width == 4) 875 writel(0x7040, ®s->blkattr); 876 } else { 877 writel(0x7040, ®s->blkattr); 878 } 879 880 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ 881 val = readl(®s->mixctrl); 882 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); 883 writel(val, ®s->mixctrl); 884 885 /* We are using STD tuning, no need to check return value */ 886 mmc_send_tuning(mmc, opcode, NULL); 887 888 ctrl = readl(®s->autoc12err); 889 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && 890 (ctrl & MIX_CTRL_SMPCLK_SEL)) { 891 /* 892 * need to wait some time, make sure sd/mmc fininsh 893 * send out tuning data, otherwise, the sd/mmc can't 894 * response to any command when the card still out 895 * put the tuning data. 896 */ 897 mdelay(1); 898 ret = 0; 899 break; 900 } 901 902 /* Add 1ms delay for SD and eMMC */ 903 mdelay(1); 904 } 905 906 writel(irqstaten, ®s->irqstaten); 907 writel(irqsigen, ®s->irqsigen); 908 909 esdhc_stop_tuning(mmc); 910 911 return ret; 912 } 913 #endif 914 915 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 916 { 917 struct fsl_esdhc *regs = priv->esdhc_regs; 918 int ret __maybe_unused; 919 920 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 921 /* Select to use peripheral clock */ 922 esdhc_clock_control(priv, false); 923 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 924 esdhc_clock_control(priv, true); 925 #endif 926 /* Set the clock speed */ 927 if (priv->clock != mmc->clock) 928 set_sysctl(priv, mmc, mmc->clock); 929 930 #ifdef MMC_SUPPORTS_TUNING 931 if (mmc->clk_disable) { 932 #ifdef CONFIG_FSL_USDHC 933 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 934 #else 935 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 936 #endif 937 } else { 938 #ifdef CONFIG_FSL_USDHC 939 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 940 VENDORSPEC_CKEN); 941 #else 942 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 943 #endif 944 } 945 946 if (priv->mode != mmc->selected_mode) { 947 ret = esdhc_set_timing(mmc); 948 if (ret) { 949 printf("esdhc_set_timing error %d\n", ret); 950 return ret; 951 } 952 } 953 954 if (priv->signal_voltage != mmc->signal_voltage) { 955 ret = esdhc_set_voltage(mmc); 956 if (ret) { 957 printf("esdhc_set_voltage error %d\n", ret); 958 return ret; 959 } 960 } 961 #endif 962 963 /* Set the bus width */ 964 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 965 966 if (mmc->bus_width == 4) 967 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 968 else if (mmc->bus_width == 8) 969 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 970 971 return 0; 972 } 973 974 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 975 { 976 struct fsl_esdhc *regs = priv->esdhc_regs; 977 ulong start; 978 979 /* Reset the entire host controller */ 980 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 981 982 /* Wait until the controller is available */ 983 start = get_timer(0); 984 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 985 if (get_timer(start) > 1000) 986 return -ETIMEDOUT; 987 } 988 989 #if defined(CONFIG_FSL_USDHC) 990 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 991 esdhc_write32(®s->mmcboot, 0x0); 992 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 993 esdhc_write32(®s->mixctrl, 0x0); 994 esdhc_write32(®s->clktunectrlstatus, 0x0); 995 996 /* Put VEND_SPEC to default value */ 997 if (priv->vs18_enable) 998 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | 999 ESDHC_VENDORSPEC_VSELECT)); 1000 else 1001 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 1002 1003 /* Disable DLL_CTRL delay line */ 1004 esdhc_write32(®s->dllctrl, 0x0); 1005 #endif 1006 1007 #ifndef ARCH_MXC 1008 /* Enable cache snooping */ 1009 esdhc_write32(®s->scr, 0x00000040); 1010 #endif 1011 1012 #ifndef CONFIG_FSL_USDHC 1013 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 1014 #else 1015 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 1016 #endif 1017 1018 /* Set the initial clock speed */ 1019 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); 1020 1021 /* Disable the BRR and BWR bits in IRQSTAT */ 1022 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 1023 1024 /* Put the PROCTL reg back to the default */ 1025 esdhc_write32(®s->proctl, PROCTL_INIT); 1026 1027 /* Set timout to the maximum value */ 1028 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 1029 1030 return 0; 1031 } 1032 1033 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) 1034 { 1035 struct fsl_esdhc *regs = priv->esdhc_regs; 1036 int timeout = 1000; 1037 1038 #ifdef CONFIG_ESDHC_DETECT_QUIRK 1039 if (CONFIG_ESDHC_DETECT_QUIRK) 1040 return 1; 1041 #endif 1042 1043 #if CONFIG_IS_ENABLED(DM_MMC) 1044 if (priv->non_removable) 1045 return 1; 1046 #ifdef CONFIG_DM_GPIO 1047 if (dm_gpio_is_valid(&priv->cd_gpio)) 1048 return dm_gpio_get_value(&priv->cd_gpio); 1049 #endif 1050 #endif 1051 1052 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 1053 udelay(1000); 1054 1055 return timeout > 0; 1056 } 1057 1058 static int esdhc_reset(struct fsl_esdhc *regs) 1059 { 1060 ulong start; 1061 1062 /* reset the controller */ 1063 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 1064 1065 /* hardware clears the bit when it is done */ 1066 start = get_timer(0); 1067 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 1068 if (get_timer(start) > 100) { 1069 printf("MMC/SD: Reset never completed.\n"); 1070 return -ETIMEDOUT; 1071 } 1072 } 1073 1074 return 0; 1075 } 1076 1077 #if !CONFIG_IS_ENABLED(DM_MMC) 1078 static int esdhc_getcd(struct mmc *mmc) 1079 { 1080 struct fsl_esdhc_priv *priv = mmc->priv; 1081 1082 return esdhc_getcd_common(priv); 1083 } 1084 1085 static int esdhc_init(struct mmc *mmc) 1086 { 1087 struct fsl_esdhc_priv *priv = mmc->priv; 1088 1089 return esdhc_init_common(priv, mmc); 1090 } 1091 1092 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 1093 struct mmc_data *data) 1094 { 1095 struct fsl_esdhc_priv *priv = mmc->priv; 1096 1097 return esdhc_send_cmd_common(priv, mmc, cmd, data); 1098 } 1099 1100 static int esdhc_set_ios(struct mmc *mmc) 1101 { 1102 struct fsl_esdhc_priv *priv = mmc->priv; 1103 1104 return esdhc_set_ios_common(priv, mmc); 1105 } 1106 1107 static const struct mmc_ops esdhc_ops = { 1108 .getcd = esdhc_getcd, 1109 .init = esdhc_init, 1110 .send_cmd = esdhc_send_cmd, 1111 .set_ios = esdhc_set_ios, 1112 }; 1113 #endif 1114 1115 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, 1116 struct fsl_esdhc_plat *plat) 1117 { 1118 struct mmc_config *cfg; 1119 struct fsl_esdhc *regs; 1120 u32 caps, voltage_caps; 1121 int ret; 1122 1123 if (!priv) 1124 return -EINVAL; 1125 1126 regs = priv->esdhc_regs; 1127 1128 /* First reset the eSDHC controller */ 1129 ret = esdhc_reset(regs); 1130 if (ret) 1131 return ret; 1132 1133 #ifndef CONFIG_FSL_USDHC 1134 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 1135 | SYSCTL_IPGEN | SYSCTL_CKEN); 1136 /* Clearing tuning bits in case ROM has set it already */ 1137 esdhc_write32(®s->mixctrl, 0); 1138 esdhc_write32(®s->autoc12err, 0); 1139 esdhc_write32(®s->clktunectrlstatus, 0); 1140 #else 1141 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 1142 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 1143 #endif 1144 1145 if (priv->vs18_enable) 1146 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 1147 1148 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 1149 cfg = &plat->cfg; 1150 #ifndef CONFIG_DM_MMC 1151 memset(cfg, '\0', sizeof(*cfg)); 1152 #endif 1153 1154 voltage_caps = 0; 1155 caps = esdhc_read32(®s->hostcapblt); 1156 1157 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 1158 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 1159 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 1160 #endif 1161 1162 /* T4240 host controller capabilities register should have VS33 bit */ 1163 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 1164 caps = caps | ESDHC_HOSTCAPBLT_VS33; 1165 #endif 1166 1167 if (caps & ESDHC_HOSTCAPBLT_VS18) 1168 voltage_caps |= MMC_VDD_165_195; 1169 if (caps & ESDHC_HOSTCAPBLT_VS30) 1170 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 1171 if (caps & ESDHC_HOSTCAPBLT_VS33) 1172 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 1173 1174 cfg->name = "FSL_SDHC"; 1175 #if !CONFIG_IS_ENABLED(DM_MMC) 1176 cfg->ops = &esdhc_ops; 1177 #endif 1178 #ifdef CONFIG_SYS_SD_VOLTAGE 1179 cfg->voltages = CONFIG_SYS_SD_VOLTAGE; 1180 #else 1181 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 1182 #endif 1183 if ((cfg->voltages & voltage_caps) == 0) { 1184 printf("voltage not supported by controller\n"); 1185 return -1; 1186 } 1187 1188 if (priv->bus_width == 8) 1189 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1190 else if (priv->bus_width == 4) 1191 cfg->host_caps = MMC_MODE_4BIT; 1192 1193 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1194 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 1195 cfg->host_caps |= MMC_MODE_DDR_52MHz; 1196 #endif 1197 1198 if (priv->bus_width > 0) { 1199 if (priv->bus_width < 8) 1200 cfg->host_caps &= ~MMC_MODE_8BIT; 1201 if (priv->bus_width < 4) 1202 cfg->host_caps &= ~MMC_MODE_4BIT; 1203 } 1204 1205 if (caps & ESDHC_HOSTCAPBLT_HSS) 1206 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1207 1208 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 1209 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 1210 cfg->host_caps &= ~MMC_MODE_8BIT; 1211 #endif 1212 1213 cfg->host_caps |= priv->caps; 1214 1215 cfg->f_min = 400000; 1216 cfg->f_max = min(priv->sdhc_clk, (u32)200000000); 1217 1218 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1219 1220 writel(0, ®s->dllctrl); 1221 if (priv->flags & ESDHC_FLAG_USDHC) { 1222 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 1223 u32 val = readl(®s->tuning_ctrl); 1224 1225 val |= ESDHC_STD_TUNING_EN; 1226 val &= ~ESDHC_TUNING_START_TAP_MASK; 1227 val |= priv->tuning_start_tap; 1228 val &= ~ESDHC_TUNING_STEP_MASK; 1229 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT; 1230 writel(val, ®s->tuning_ctrl); 1231 } 1232 } 1233 1234 return 0; 1235 } 1236 1237 #if !CONFIG_IS_ENABLED(DM_MMC) 1238 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 1239 struct fsl_esdhc_priv *priv) 1240 { 1241 if (!cfg || !priv) 1242 return -EINVAL; 1243 1244 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 1245 priv->bus_width = cfg->max_bus_width; 1246 priv->sdhc_clk = cfg->sdhc_clk; 1247 priv->wp_enable = cfg->wp_enable; 1248 priv->vs18_enable = cfg->vs18_enable; 1249 1250 return 0; 1251 }; 1252 1253 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 1254 { 1255 struct fsl_esdhc_plat *plat; 1256 struct fsl_esdhc_priv *priv; 1257 struct mmc *mmc; 1258 int ret; 1259 1260 if (!cfg) 1261 return -EINVAL; 1262 1263 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 1264 if (!priv) 1265 return -ENOMEM; 1266 plat = calloc(sizeof(struct fsl_esdhc_plat), 1); 1267 if (!plat) { 1268 free(priv); 1269 return -ENOMEM; 1270 } 1271 1272 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 1273 if (ret) { 1274 debug("%s xlate failure\n", __func__); 1275 free(plat); 1276 free(priv); 1277 return ret; 1278 } 1279 1280 ret = fsl_esdhc_init(priv, plat); 1281 if (ret) { 1282 debug("%s init failure\n", __func__); 1283 free(plat); 1284 free(priv); 1285 return ret; 1286 } 1287 1288 mmc = mmc_create(&plat->cfg, priv); 1289 if (!mmc) 1290 return -EIO; 1291 1292 priv->mmc = mmc; 1293 1294 return 0; 1295 } 1296 1297 int fsl_esdhc_mmc_init(bd_t *bis) 1298 { 1299 struct fsl_esdhc_cfg *cfg; 1300 1301 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 1302 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 1303 cfg->sdhc_clk = gd->arch.sdhc_clk; 1304 return fsl_esdhc_initialize(bis, cfg); 1305 } 1306 #endif 1307 1308 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1309 void mmc_adapter_card_type_ident(void) 1310 { 1311 u8 card_id; 1312 u8 value; 1313 1314 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 1315 gd->arch.sdhc_adapter = card_id; 1316 1317 switch (card_id) { 1318 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 1319 value = QIXIS_READ(brdcfg[5]); 1320 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 1321 QIXIS_WRITE(brdcfg[5], value); 1322 break; 1323 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 1324 value = QIXIS_READ(pwr_ctl[1]); 1325 value |= QIXIS_EVDD_BY_SDHC_VS; 1326 QIXIS_WRITE(pwr_ctl[1], value); 1327 break; 1328 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 1329 value = QIXIS_READ(brdcfg[5]); 1330 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 1331 QIXIS_WRITE(brdcfg[5], value); 1332 break; 1333 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 1334 break; 1335 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 1336 break; 1337 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 1338 break; 1339 case QIXIS_ESDHC_NO_ADAPTER: 1340 break; 1341 default: 1342 break; 1343 } 1344 } 1345 #endif 1346 1347 #ifdef CONFIG_OF_LIBFDT 1348 __weak int esdhc_status_fixup(void *blob, const char *compat) 1349 { 1350 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 1351 if (!hwconfig("esdhc")) { 1352 do_fixup_by_compat(blob, compat, "status", "disabled", 1353 sizeof("disabled"), 1); 1354 return 1; 1355 } 1356 #endif 1357 return 0; 1358 } 1359 1360 void fdt_fixup_esdhc(void *blob, bd_t *bd) 1361 { 1362 const char *compat = "fsl,esdhc"; 1363 1364 if (esdhc_status_fixup(blob, compat)) 1365 return; 1366 1367 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 1368 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 1369 gd->arch.sdhc_clk, 1); 1370 #else 1371 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 1372 gd->arch.sdhc_clk, 1); 1373 #endif 1374 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1375 do_fixup_by_compat_u32(blob, compat, "adapter-type", 1376 (u32)(gd->arch.sdhc_adapter), 1); 1377 #endif 1378 } 1379 #endif 1380 1381 #if CONFIG_IS_ENABLED(DM_MMC) 1382 #include <asm/arch/clock.h> 1383 __weak void init_clk_usdhc(u32 index) 1384 { 1385 } 1386 1387 static int fsl_esdhc_probe(struct udevice *dev) 1388 { 1389 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1390 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1391 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1392 const void *fdt = gd->fdt_blob; 1393 int node = dev_of_offset(dev); 1394 struct esdhc_soc_data *data = 1395 (struct esdhc_soc_data *)dev_get_driver_data(dev); 1396 #ifdef CONFIG_DM_REGULATOR 1397 struct udevice *vqmmc_dev; 1398 #endif 1399 fdt_addr_t addr; 1400 unsigned int val; 1401 struct mmc *mmc; 1402 int ret; 1403 1404 addr = dev_read_addr(dev); 1405 if (addr == FDT_ADDR_T_NONE) 1406 return -EINVAL; 1407 1408 priv->esdhc_regs = (struct fsl_esdhc *)addr; 1409 priv->dev = dev; 1410 priv->mode = -1; 1411 if (data) { 1412 priv->flags = data->flags; 1413 priv->caps = data->caps; 1414 } 1415 1416 val = dev_read_u32_default(dev, "bus-width", -1); 1417 if (val == 8) 1418 priv->bus_width = 8; 1419 else if (val == 4) 1420 priv->bus_width = 4; 1421 else 1422 priv->bus_width = 1; 1423 1424 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1); 1425 priv->tuning_step = val; 1426 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", 1427 ESDHC_TUNING_START_TAP_DEFAULT); 1428 priv->tuning_start_tap = val; 1429 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", 1430 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); 1431 priv->strobe_dll_delay_target = val; 1432 1433 if (dev_read_bool(dev, "non-removable")) { 1434 priv->non_removable = 1; 1435 } else { 1436 priv->non_removable = 0; 1437 #ifdef CONFIG_DM_GPIO 1438 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 1439 GPIOD_IS_IN); 1440 #endif 1441 } 1442 1443 priv->wp_enable = 1; 1444 1445 #ifdef CONFIG_DM_GPIO 1446 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 1447 GPIOD_IS_IN); 1448 if (ret) 1449 priv->wp_enable = 0; 1450 #endif 1451 1452 priv->vs18_enable = 0; 1453 1454 #ifdef CONFIG_DM_REGULATOR 1455 /* 1456 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1457 * otherwise, emmc will work abnormally. 1458 */ 1459 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1460 if (ret) { 1461 dev_dbg(dev, "no vqmmc-supply\n"); 1462 } else { 1463 ret = regulator_set_enable(vqmmc_dev, true); 1464 if (ret) { 1465 dev_err(dev, "fail to enable vqmmc-supply\n"); 1466 return ret; 1467 } 1468 1469 if (regulator_get_value(vqmmc_dev) == 1800000) 1470 priv->vs18_enable = 1; 1471 } 1472 #endif 1473 1474 if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) 1475 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400); 1476 1477 /* 1478 * TODO: 1479 * Because lack of clk driver, if SDHC clk is not enabled, 1480 * need to enable it first before this driver is invoked. 1481 * 1482 * we use MXC_ESDHC_CLK to get clk freq. 1483 * If one would like to make this function work, 1484 * the aliases should be provided in dts as this: 1485 * 1486 * aliases { 1487 * mmc0 = &usdhc1; 1488 * mmc1 = &usdhc2; 1489 * mmc2 = &usdhc3; 1490 * mmc3 = &usdhc4; 1491 * }; 1492 * Then if your board only supports mmc2 and mmc3, but we can 1493 * correctly get the seq as 2 and 3, then let mxc_get_clock 1494 * work as expected. 1495 */ 1496 1497 init_clk_usdhc(dev->seq); 1498 1499 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1500 if (priv->sdhc_clk <= 0) { 1501 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1502 return -EINVAL; 1503 } 1504 1505 ret = fsl_esdhc_init(priv, plat); 1506 if (ret) { 1507 dev_err(dev, "fsl_esdhc_init failure\n"); 1508 return ret; 1509 } 1510 1511 mmc = &plat->mmc; 1512 mmc->cfg = &plat->cfg; 1513 mmc->dev = dev; 1514 upriv->mmc = mmc; 1515 1516 return esdhc_init_common(priv, mmc); 1517 } 1518 1519 #if CONFIG_IS_ENABLED(DM_MMC) 1520 static int fsl_esdhc_get_cd(struct udevice *dev) 1521 { 1522 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1523 1524 return true; 1525 return esdhc_getcd_common(priv); 1526 } 1527 1528 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 1529 struct mmc_data *data) 1530 { 1531 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1532 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1533 1534 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); 1535 } 1536 1537 static int fsl_esdhc_set_ios(struct udevice *dev) 1538 { 1539 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1540 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1541 1542 return esdhc_set_ios_common(priv, &plat->mmc); 1543 } 1544 1545 static const struct dm_mmc_ops fsl_esdhc_ops = { 1546 .get_cd = fsl_esdhc_get_cd, 1547 .send_cmd = fsl_esdhc_send_cmd, 1548 .set_ios = fsl_esdhc_set_ios, 1549 #ifdef MMC_SUPPORTS_TUNING 1550 .execute_tuning = fsl_esdhc_execute_tuning, 1551 #endif 1552 }; 1553 #endif 1554 1555 static struct esdhc_soc_data usdhc_imx7d_data = { 1556 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1557 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 1558 | ESDHC_FLAG_HS400, 1559 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | 1560 MMC_MODE_HS_52MHz | MMC_MODE_HS, 1561 }; 1562 1563 static const struct udevice_id fsl_esdhc_ids[] = { 1564 { .compatible = "fsl,imx6ul-usdhc", }, 1565 { .compatible = "fsl,imx6sx-usdhc", }, 1566 { .compatible = "fsl,imx6sl-usdhc", }, 1567 { .compatible = "fsl,imx6q-usdhc", }, 1568 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, 1569 { .compatible = "fsl,imx7ulp-usdhc", }, 1570 { .compatible = "fsl,esdhc", }, 1571 { /* sentinel */ } 1572 }; 1573 1574 #if CONFIG_IS_ENABLED(BLK) 1575 static int fsl_esdhc_bind(struct udevice *dev) 1576 { 1577 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1578 1579 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1580 } 1581 #endif 1582 1583 U_BOOT_DRIVER(fsl_esdhc) = { 1584 .name = "fsl-esdhc-mmc", 1585 .id = UCLASS_MMC, 1586 .of_match = fsl_esdhc_ids, 1587 .ops = &fsl_esdhc_ops, 1588 #if CONFIG_IS_ENABLED(BLK) 1589 .bind = fsl_esdhc_bind, 1590 #endif 1591 .probe = fsl_esdhc_probe, 1592 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), 1593 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1594 }; 1595 #endif 1596