1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 #include <dm.h> 24 #include <asm-generic/gpio.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 29 IRQSTATEN_CINT | \ 30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 33 IRQSTATEN_DINT) 34 35 struct fsl_esdhc { 36 uint dsaddr; /* SDMA system address register */ 37 uint blkattr; /* Block attributes register */ 38 uint cmdarg; /* Command argument register */ 39 uint xfertyp; /* Transfer type register */ 40 uint cmdrsp0; /* Command response 0 register */ 41 uint cmdrsp1; /* Command response 1 register */ 42 uint cmdrsp2; /* Command response 2 register */ 43 uint cmdrsp3; /* Command response 3 register */ 44 uint datport; /* Buffer data port register */ 45 uint prsstat; /* Present state register */ 46 uint proctl; /* Protocol control register */ 47 uint sysctl; /* System Control Register */ 48 uint irqstat; /* Interrupt status register */ 49 uint irqstaten; /* Interrupt status enable register */ 50 uint irqsigen; /* Interrupt signal enable register */ 51 uint autoc12err; /* Auto CMD error status register */ 52 uint hostcapblt; /* Host controller capabilities register */ 53 uint wml; /* Watermark level register */ 54 uint mixctrl; /* For USDHC */ 55 char reserved1[4]; /* reserved */ 56 uint fevt; /* Force event register */ 57 uint admaes; /* ADMA error status register */ 58 uint adsaddr; /* ADMA system address register */ 59 char reserved2[100]; /* reserved */ 60 uint vendorspec; /* Vendor Specific register */ 61 char reserved3[56]; /* reserved */ 62 uint hostver; /* Host controller version register */ 63 char reserved4[4]; /* reserved */ 64 uint dmaerraddr; /* DMA error address register */ 65 char reserved5[4]; /* reserved */ 66 uint dmaerrattr; /* DMA error attribute register */ 67 char reserved6[4]; /* reserved */ 68 uint hostcapblt2; /* Host controller capabilities register 2 */ 69 char reserved7[8]; /* reserved */ 70 uint tcr; /* Tuning control register */ 71 char reserved8[28]; /* reserved */ 72 uint sddirctl; /* SD direction control register */ 73 char reserved9[712]; /* reserved */ 74 uint scr; /* eSDHC control register */ 75 }; 76 77 /** 78 * struct fsl_esdhc_priv 79 * 80 * @esdhc_regs: registers of the sdhc controller 81 * @sdhc_clk: Current clk of the sdhc controller 82 * @bus_width: bus width, 1bit, 4bit or 8bit 83 * @cfg: mmc config 84 * @mmc: mmc 85 * Following is used when Driver Model is enabled for MMC 86 * @dev: pointer for the device 87 * @non_removable: 0: removable; 1: non-removable 88 * @cd_gpio: gpio for card detection 89 */ 90 struct fsl_esdhc_priv { 91 struct fsl_esdhc *esdhc_regs; 92 unsigned int sdhc_clk; 93 unsigned int bus_width; 94 struct mmc_config cfg; 95 struct mmc *mmc; 96 struct udevice *dev; 97 int non_removable; 98 struct gpio_desc cd_gpio; 99 }; 100 101 /* Return the XFERTYP flags for a given command and data packet */ 102 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 103 { 104 uint xfertyp = 0; 105 106 if (data) { 107 xfertyp |= XFERTYP_DPSEL; 108 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 109 xfertyp |= XFERTYP_DMAEN; 110 #endif 111 if (data->blocks > 1) { 112 xfertyp |= XFERTYP_MSBSEL; 113 xfertyp |= XFERTYP_BCEN; 114 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 115 xfertyp |= XFERTYP_AC12EN; 116 #endif 117 } 118 119 if (data->flags & MMC_DATA_READ) 120 xfertyp |= XFERTYP_DTDSEL; 121 } 122 123 if (cmd->resp_type & MMC_RSP_CRC) 124 xfertyp |= XFERTYP_CCCEN; 125 if (cmd->resp_type & MMC_RSP_OPCODE) 126 xfertyp |= XFERTYP_CICEN; 127 if (cmd->resp_type & MMC_RSP_136) 128 xfertyp |= XFERTYP_RSPTYP_136; 129 else if (cmd->resp_type & MMC_RSP_BUSY) 130 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 131 else if (cmd->resp_type & MMC_RSP_PRESENT) 132 xfertyp |= XFERTYP_RSPTYP_48; 133 134 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 135 xfertyp |= XFERTYP_CMDTYP_ABORT; 136 137 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 138 } 139 140 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 141 /* 142 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 143 */ 144 static void 145 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 146 { 147 struct fsl_esdhc_priv *priv = mmc->priv; 148 struct fsl_esdhc *regs = priv->esdhc_regs; 149 uint blocks; 150 char *buffer; 151 uint databuf; 152 uint size; 153 uint irqstat; 154 uint timeout; 155 156 if (data->flags & MMC_DATA_READ) { 157 blocks = data->blocks; 158 buffer = data->dest; 159 while (blocks) { 160 timeout = PIO_TIMEOUT; 161 size = data->blocksize; 162 irqstat = esdhc_read32(®s->irqstat); 163 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 164 && --timeout); 165 if (timeout <= 0) { 166 printf("\nData Read Failed in PIO Mode."); 167 return; 168 } 169 while (size && (!(irqstat & IRQSTAT_TC))) { 170 udelay(100); /* Wait before last byte transfer complete */ 171 irqstat = esdhc_read32(®s->irqstat); 172 databuf = in_le32(®s->datport); 173 *((uint *)buffer) = databuf; 174 buffer += 4; 175 size -= 4; 176 } 177 blocks--; 178 } 179 } else { 180 blocks = data->blocks; 181 buffer = (char *)data->src; 182 while (blocks) { 183 timeout = PIO_TIMEOUT; 184 size = data->blocksize; 185 irqstat = esdhc_read32(®s->irqstat); 186 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 187 && --timeout); 188 if (timeout <= 0) { 189 printf("\nData Write Failed in PIO Mode."); 190 return; 191 } 192 while (size && (!(irqstat & IRQSTAT_TC))) { 193 udelay(100); /* Wait before last byte transfer complete */ 194 databuf = *((uint *)buffer); 195 buffer += 4; 196 size -= 4; 197 irqstat = esdhc_read32(®s->irqstat); 198 out_le32(®s->datport, databuf); 199 } 200 blocks--; 201 } 202 } 203 } 204 #endif 205 206 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 207 { 208 int timeout; 209 struct fsl_esdhc_priv *priv = mmc->priv; 210 struct fsl_esdhc *regs = priv->esdhc_regs; 211 #ifdef CONFIG_FSL_LAYERSCAPE 212 dma_addr_t addr; 213 #endif 214 uint wml_value; 215 216 wml_value = data->blocksize/4; 217 218 if (data->flags & MMC_DATA_READ) { 219 if (wml_value > WML_RD_WML_MAX) 220 wml_value = WML_RD_WML_MAX_VAL; 221 222 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 223 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 224 #ifdef CONFIG_FSL_LAYERSCAPE 225 addr = virt_to_phys((void *)(data->dest)); 226 if (upper_32_bits(addr)) 227 printf("Error found for upper 32 bits\n"); 228 else 229 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 230 #else 231 esdhc_write32(®s->dsaddr, (u32)data->dest); 232 #endif 233 #endif 234 } else { 235 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 236 flush_dcache_range((ulong)data->src, 237 (ulong)data->src+data->blocks 238 *data->blocksize); 239 #endif 240 if (wml_value > WML_WR_WML_MAX) 241 wml_value = WML_WR_WML_MAX_VAL; 242 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 243 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 244 return TIMEOUT; 245 } 246 247 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 248 wml_value << 16); 249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 250 #ifdef CONFIG_FSL_LAYERSCAPE 251 addr = virt_to_phys((void *)(data->src)); 252 if (upper_32_bits(addr)) 253 printf("Error found for upper 32 bits\n"); 254 else 255 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 256 #else 257 esdhc_write32(®s->dsaddr, (u32)data->src); 258 #endif 259 #endif 260 } 261 262 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 263 264 /* Calculate the timeout period for data transactions */ 265 /* 266 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 267 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 268 * So, Number of SD Clock cycles for 0.25sec should be minimum 269 * (SD Clock/sec * 0.25 sec) SD Clock cycles 270 * = (mmc->clock * 1/4) SD Clock cycles 271 * As 1) >= 2) 272 * => (2^(timeout+13)) >= mmc->clock * 1/4 273 * Taking log2 both the sides 274 * => timeout + 13 >= log2(mmc->clock/4) 275 * Rounding up to next power of 2 276 * => timeout + 13 = log2(mmc->clock/4) + 1 277 * => timeout + 13 = fls(mmc->clock/4) 278 * 279 * However, the MMC spec "It is strongly recommended for hosts to 280 * implement more than 500ms timeout value even if the card 281 * indicates the 250ms maximum busy length." Even the previous 282 * value of 300ms is known to be insufficient for some cards. 283 * So, we use 284 * => timeout + 13 = fls(mmc->clock/2) 285 */ 286 timeout = fls(mmc->clock/2); 287 timeout -= 13; 288 289 if (timeout > 14) 290 timeout = 14; 291 292 if (timeout < 0) 293 timeout = 0; 294 295 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 296 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 297 timeout++; 298 #endif 299 300 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 301 timeout = 0xE; 302 #endif 303 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 304 305 return 0; 306 } 307 308 static void check_and_invalidate_dcache_range 309 (struct mmc_cmd *cmd, 310 struct mmc_data *data) { 311 #ifdef CONFIG_FSL_LAYERSCAPE 312 unsigned start = 0; 313 #else 314 unsigned start = (unsigned)data->dest ; 315 #endif 316 unsigned size = roundup(ARCH_DMA_MINALIGN, 317 data->blocks*data->blocksize); 318 unsigned end = start+size ; 319 #ifdef CONFIG_FSL_LAYERSCAPE 320 dma_addr_t addr; 321 322 addr = virt_to_phys((void *)(data->dest)); 323 if (upper_32_bits(addr)) 324 printf("Error found for upper 32 bits\n"); 325 else 326 start = lower_32_bits(addr); 327 #endif 328 invalidate_dcache_range(start, end); 329 } 330 331 /* 332 * Sends a command out on the bus. Takes the mmc pointer, 333 * a command pointer, and an optional data pointer. 334 */ 335 static int 336 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 337 { 338 int err = 0; 339 uint xfertyp; 340 uint irqstat; 341 struct fsl_esdhc_priv *priv = mmc->priv; 342 struct fsl_esdhc *regs = priv->esdhc_regs; 343 344 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 345 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 346 return 0; 347 #endif 348 349 esdhc_write32(®s->irqstat, -1); 350 351 sync(); 352 353 /* Wait for the bus to be idle */ 354 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 355 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 356 ; 357 358 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 359 ; 360 361 /* Wait at least 8 SD clock cycles before the next command */ 362 /* 363 * Note: This is way more than 8 cycles, but 1ms seems to 364 * resolve timing issues with some cards 365 */ 366 udelay(1000); 367 368 /* Set up for a data transfer if we have one */ 369 if (data) { 370 err = esdhc_setup_data(mmc, data); 371 if(err) 372 return err; 373 374 if (data->flags & MMC_DATA_READ) 375 check_and_invalidate_dcache_range(cmd, data); 376 } 377 378 /* Figure out the transfer arguments */ 379 xfertyp = esdhc_xfertyp(cmd, data); 380 381 /* Mask all irqs */ 382 esdhc_write32(®s->irqsigen, 0); 383 384 /* Send the command */ 385 esdhc_write32(®s->cmdarg, cmd->cmdarg); 386 #if defined(CONFIG_FSL_USDHC) 387 esdhc_write32(®s->mixctrl, 388 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 389 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 390 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 391 #else 392 esdhc_write32(®s->xfertyp, xfertyp); 393 #endif 394 395 /* Wait for the command to complete */ 396 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 397 ; 398 399 irqstat = esdhc_read32(®s->irqstat); 400 401 if (irqstat & CMD_ERR) { 402 err = COMM_ERR; 403 goto out; 404 } 405 406 if (irqstat & IRQSTAT_CTOE) { 407 err = TIMEOUT; 408 goto out; 409 } 410 411 /* Switch voltage to 1.8V if CMD11 succeeded */ 412 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 413 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 414 415 printf("Run CMD11 1.8V switch\n"); 416 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 417 udelay(5000); 418 } 419 420 /* Workaround for ESDHC errata ENGcm03648 */ 421 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 422 int timeout = 6000; 423 424 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 425 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 426 PRSSTAT_DAT0)) { 427 udelay(100); 428 timeout--; 429 } 430 431 if (timeout <= 0) { 432 printf("Timeout waiting for DAT0 to go high!\n"); 433 err = TIMEOUT; 434 goto out; 435 } 436 } 437 438 /* Copy the response to the response buffer */ 439 if (cmd->resp_type & MMC_RSP_136) { 440 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 441 442 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 443 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 444 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 445 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 446 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 447 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 448 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 449 cmd->response[3] = (cmdrsp0 << 8); 450 } else 451 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 452 453 /* Wait until all of the blocks are transferred */ 454 if (data) { 455 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 456 esdhc_pio_read_write(mmc, data); 457 #else 458 do { 459 irqstat = esdhc_read32(®s->irqstat); 460 461 if (irqstat & IRQSTAT_DTOE) { 462 err = TIMEOUT; 463 goto out; 464 } 465 466 if (irqstat & DATA_ERR) { 467 err = COMM_ERR; 468 goto out; 469 } 470 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 471 472 /* 473 * Need invalidate the dcache here again to avoid any 474 * cache-fill during the DMA operations such as the 475 * speculative pre-fetching etc. 476 */ 477 if (data->flags & MMC_DATA_READ) 478 check_and_invalidate_dcache_range(cmd, data); 479 #endif 480 } 481 482 out: 483 /* Reset CMD and DATA portions on error */ 484 if (err) { 485 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 486 SYSCTL_RSTC); 487 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 488 ; 489 490 if (data) { 491 esdhc_write32(®s->sysctl, 492 esdhc_read32(®s->sysctl) | 493 SYSCTL_RSTD); 494 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 495 ; 496 } 497 498 /* If this was CMD11, then notify that power cycle is needed */ 499 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 500 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 501 } 502 503 esdhc_write32(®s->irqstat, -1); 504 505 return err; 506 } 507 508 static void set_sysctl(struct mmc *mmc, uint clock) 509 { 510 int div, pre_div; 511 struct fsl_esdhc_priv *priv = mmc->priv; 512 struct fsl_esdhc *regs = priv->esdhc_regs; 513 int sdhc_clk = priv->sdhc_clk; 514 uint clk; 515 516 if (clock < mmc->cfg->f_min) 517 clock = mmc->cfg->f_min; 518 519 if (sdhc_clk / 16 > clock) { 520 for (pre_div = 2; pre_div < 256; pre_div *= 2) 521 if ((sdhc_clk / pre_div) <= (clock * 16)) 522 break; 523 } else 524 pre_div = 2; 525 526 for (div = 1; div <= 16; div++) 527 if ((sdhc_clk / (div * pre_div)) <= clock) 528 break; 529 530 pre_div >>= mmc->ddr_mode ? 2 : 1; 531 div -= 1; 532 533 clk = (pre_div << 8) | (div << 4); 534 535 #ifdef CONFIG_FSL_USDHC 536 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 537 #else 538 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 539 #endif 540 541 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 542 543 udelay(10000); 544 545 #ifdef CONFIG_FSL_USDHC 546 esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); 547 #else 548 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 549 #endif 550 551 } 552 553 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 554 static void esdhc_clock_control(struct mmc *mmc, bool enable) 555 { 556 struct fsl_esdhc_priv *priv = mmc->priv; 557 struct fsl_esdhc *regs = priv->esdhc_regs; 558 u32 value; 559 u32 time_out; 560 561 value = esdhc_read32(®s->sysctl); 562 563 if (enable) 564 value |= SYSCTL_CKEN; 565 else 566 value &= ~SYSCTL_CKEN; 567 568 esdhc_write32(®s->sysctl, value); 569 570 time_out = 20; 571 value = PRSSTAT_SDSTB; 572 while (!(esdhc_read32(®s->prsstat) & value)) { 573 if (time_out == 0) { 574 printf("fsl_esdhc: Internal clock never stabilised.\n"); 575 break; 576 } 577 time_out--; 578 mdelay(1); 579 } 580 } 581 #endif 582 583 static void esdhc_set_ios(struct mmc *mmc) 584 { 585 struct fsl_esdhc_priv *priv = mmc->priv; 586 struct fsl_esdhc *regs = priv->esdhc_regs; 587 588 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 589 /* Select to use peripheral clock */ 590 esdhc_clock_control(mmc, false); 591 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 592 esdhc_clock_control(mmc, true); 593 #endif 594 /* Set the clock speed */ 595 set_sysctl(mmc, mmc->clock); 596 597 /* Set the bus width */ 598 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 599 600 if (mmc->bus_width == 4) 601 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 602 else if (mmc->bus_width == 8) 603 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 604 605 } 606 607 static int esdhc_init(struct mmc *mmc) 608 { 609 struct fsl_esdhc_priv *priv = mmc->priv; 610 struct fsl_esdhc *regs = priv->esdhc_regs; 611 int timeout = 1000; 612 613 /* Reset the entire host controller */ 614 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 615 616 /* Wait until the controller is available */ 617 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 618 udelay(1000); 619 620 #ifndef ARCH_MXC 621 /* Enable cache snooping */ 622 esdhc_write32(®s->scr, 0x00000040); 623 #endif 624 625 #ifndef CONFIG_FSL_USDHC 626 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 627 #endif 628 629 /* Set the initial clock speed */ 630 mmc_set_clock(mmc, 400000); 631 632 /* Disable the BRR and BWR bits in IRQSTAT */ 633 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 634 635 /* Put the PROCTL reg back to the default */ 636 esdhc_write32(®s->proctl, PROCTL_INIT); 637 638 /* Set timout to the maximum value */ 639 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 640 641 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 642 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 643 #endif 644 645 return 0; 646 } 647 648 static int esdhc_getcd(struct mmc *mmc) 649 { 650 struct fsl_esdhc_priv *priv = mmc->priv; 651 struct fsl_esdhc *regs = priv->esdhc_regs; 652 int timeout = 1000; 653 654 #ifdef CONFIG_ESDHC_DETECT_QUIRK 655 if (CONFIG_ESDHC_DETECT_QUIRK) 656 return 1; 657 #endif 658 659 #ifdef CONFIG_DM_MMC 660 if (priv->non_removable) 661 return 1; 662 663 if (dm_gpio_is_valid(&priv->cd_gpio)) 664 return dm_gpio_get_value(&priv->cd_gpio); 665 #endif 666 667 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 668 udelay(1000); 669 670 return timeout > 0; 671 } 672 673 static void esdhc_reset(struct fsl_esdhc *regs) 674 { 675 unsigned long timeout = 100; /* wait max 100 ms */ 676 677 /* reset the controller */ 678 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 679 680 /* hardware clears the bit when it is done */ 681 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 682 udelay(1000); 683 if (!timeout) 684 printf("MMC/SD: Reset never completed.\n"); 685 } 686 687 static const struct mmc_ops esdhc_ops = { 688 .send_cmd = esdhc_send_cmd, 689 .set_ios = esdhc_set_ios, 690 .init = esdhc_init, 691 .getcd = esdhc_getcd, 692 }; 693 694 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 695 struct fsl_esdhc_priv *priv) 696 { 697 if (!cfg || !priv) 698 return -EINVAL; 699 700 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 701 priv->bus_width = cfg->max_bus_width; 702 priv->sdhc_clk = cfg->sdhc_clk; 703 704 return 0; 705 }; 706 707 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) 708 { 709 struct fsl_esdhc *regs; 710 struct mmc *mmc; 711 u32 caps, voltage_caps; 712 713 if (!priv) 714 return -EINVAL; 715 716 regs = priv->esdhc_regs; 717 718 /* First reset the eSDHC controller */ 719 esdhc_reset(regs); 720 721 #ifndef CONFIG_FSL_USDHC 722 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 723 | SYSCTL_IPGEN | SYSCTL_CKEN); 724 #endif 725 726 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 727 memset(&priv->cfg, 0, sizeof(priv->cfg)); 728 729 voltage_caps = 0; 730 caps = esdhc_read32(®s->hostcapblt); 731 732 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 733 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 734 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 735 #endif 736 737 /* T4240 host controller capabilities register should have VS33 bit */ 738 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 739 caps = caps | ESDHC_HOSTCAPBLT_VS33; 740 #endif 741 742 if (caps & ESDHC_HOSTCAPBLT_VS18) 743 voltage_caps |= MMC_VDD_165_195; 744 if (caps & ESDHC_HOSTCAPBLT_VS30) 745 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 746 if (caps & ESDHC_HOSTCAPBLT_VS33) 747 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 748 749 priv->cfg.name = "FSL_SDHC"; 750 priv->cfg.ops = &esdhc_ops; 751 #ifdef CONFIG_SYS_SD_VOLTAGE 752 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 753 #else 754 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 755 #endif 756 if ((priv->cfg.voltages & voltage_caps) == 0) { 757 printf("voltage not supported by controller\n"); 758 return -1; 759 } 760 761 if (priv->bus_width == 8) 762 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 763 else if (priv->bus_width == 4) 764 priv->cfg.host_caps = MMC_MODE_4BIT; 765 766 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 767 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 768 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; 769 #endif 770 771 if (priv->bus_width > 0) { 772 if (priv->bus_width < 8) 773 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 774 if (priv->bus_width < 4) 775 priv->cfg.host_caps &= ~MMC_MODE_4BIT; 776 } 777 778 if (caps & ESDHC_HOSTCAPBLT_HSS) 779 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 780 781 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 782 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 783 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 784 #endif 785 786 priv->cfg.f_min = 400000; 787 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); 788 789 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 790 791 mmc = mmc_create(&priv->cfg, priv); 792 if (mmc == NULL) 793 return -1; 794 795 priv->mmc = mmc; 796 797 return 0; 798 } 799 800 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 801 { 802 struct fsl_esdhc_priv *priv; 803 int ret; 804 805 if (!cfg) 806 return -EINVAL; 807 808 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 809 if (!priv) 810 return -ENOMEM; 811 812 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 813 if (ret) { 814 debug("%s xlate failure\n", __func__); 815 free(priv); 816 return ret; 817 } 818 819 ret = fsl_esdhc_init(priv); 820 if (ret) { 821 debug("%s init failure\n", __func__); 822 free(priv); 823 return ret; 824 } 825 826 return 0; 827 } 828 829 int fsl_esdhc_mmc_init(bd_t *bis) 830 { 831 struct fsl_esdhc_cfg *cfg; 832 833 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 834 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 835 cfg->sdhc_clk = gd->arch.sdhc_clk; 836 return fsl_esdhc_initialize(bis, cfg); 837 } 838 839 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 840 void mmc_adapter_card_type_ident(void) 841 { 842 u8 card_id; 843 u8 value; 844 845 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 846 gd->arch.sdhc_adapter = card_id; 847 848 switch (card_id) { 849 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 850 value = QIXIS_READ(brdcfg[5]); 851 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 852 QIXIS_WRITE(brdcfg[5], value); 853 break; 854 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 855 value = QIXIS_READ(pwr_ctl[1]); 856 value |= QIXIS_EVDD_BY_SDHC_VS; 857 QIXIS_WRITE(pwr_ctl[1], value); 858 break; 859 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 860 value = QIXIS_READ(brdcfg[5]); 861 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 862 QIXIS_WRITE(brdcfg[5], value); 863 break; 864 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 865 break; 866 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 867 break; 868 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 869 break; 870 case QIXIS_ESDHC_NO_ADAPTER: 871 break; 872 default: 873 break; 874 } 875 } 876 #endif 877 878 #ifdef CONFIG_OF_LIBFDT 879 void fdt_fixup_esdhc(void *blob, bd_t *bd) 880 { 881 const char *compat = "fsl,esdhc"; 882 883 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 884 if (!hwconfig("esdhc")) { 885 do_fixup_by_compat(blob, compat, "status", "disabled", 886 8 + 1, 1); 887 return; 888 } 889 #endif 890 891 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 892 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 893 gd->arch.sdhc_clk, 1); 894 #else 895 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 896 gd->arch.sdhc_clk, 1); 897 #endif 898 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 899 do_fixup_by_compat_u32(blob, compat, "adapter-type", 900 (u32)(gd->arch.sdhc_adapter), 1); 901 #endif 902 do_fixup_by_compat(blob, compat, "status", "okay", 903 4 + 1, 1); 904 } 905 #endif 906 907 #ifdef CONFIG_DM_MMC 908 #include <asm/arch/clock.h> 909 static int fsl_esdhc_probe(struct udevice *dev) 910 { 911 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 912 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 913 const void *fdt = gd->fdt_blob; 914 int node = dev->of_offset; 915 fdt_addr_t addr; 916 unsigned int val; 917 int ret; 918 919 addr = dev_get_addr(dev); 920 if (addr == FDT_ADDR_T_NONE) 921 return -EINVAL; 922 923 priv->esdhc_regs = (struct fsl_esdhc *)addr; 924 priv->dev = dev; 925 926 val = fdtdec_get_int(fdt, node, "bus-width", -1); 927 if (val == 8) 928 priv->bus_width = 8; 929 else if (val == 4) 930 priv->bus_width = 4; 931 else 932 priv->bus_width = 1; 933 934 if (fdt_get_property(fdt, node, "non-removable", NULL)) { 935 priv->non_removable = 1; 936 } else { 937 priv->non_removable = 0; 938 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, 939 &priv->cd_gpio, GPIOD_IS_IN); 940 } 941 942 /* 943 * TODO: 944 * Because lack of clk driver, if SDHC clk is not enabled, 945 * need to enable it first before this driver is invoked. 946 * 947 * we use MXC_ESDHC_CLK to get clk freq. 948 * If one would like to make this function work, 949 * the aliases should be provided in dts as this: 950 * 951 * aliases { 952 * mmc0 = &usdhc1; 953 * mmc1 = &usdhc2; 954 * mmc2 = &usdhc3; 955 * mmc3 = &usdhc4; 956 * }; 957 * Then if your board only supports mmc2 and mmc3, but we can 958 * correctly get the seq as 2 and 3, then let mxc_get_clock 959 * work as expected. 960 */ 961 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 962 if (priv->sdhc_clk <= 0) { 963 dev_err(dev, "Unable to get clk for %s\n", dev->name); 964 return -EINVAL; 965 } 966 967 ret = fsl_esdhc_init(priv); 968 if (ret) { 969 dev_err(dev, "fsl_esdhc_init failure\n"); 970 return ret; 971 } 972 973 upriv->mmc = priv->mmc; 974 975 return 0; 976 } 977 978 static const struct udevice_id fsl_esdhc_ids[] = { 979 { .compatible = "fsl,imx6ul-usdhc", }, 980 { .compatible = "fsl,imx6sx-usdhc", }, 981 { .compatible = "fsl,imx6sl-usdhc", }, 982 { .compatible = "fsl,imx6q-usdhc", }, 983 { .compatible = "fsl,imx7d-usdhc", }, 984 { /* sentinel */ } 985 }; 986 987 U_BOOT_DRIVER(fsl_esdhc) = { 988 .name = "fsl-esdhc-mmc", 989 .id = UCLASS_MMC, 990 .of_match = fsl_esdhc_ids, 991 .probe = fsl_esdhc_probe, 992 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 993 }; 994 #endif 995