1 /* 2 * Copyright 2007,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 char reserved1[8]; 62 uint fevt; 63 char reserved2[168]; 64 uint hostver; 65 char reserved3[780]; 66 uint scr; 67 }; 68 69 /* Return the XFERTYP flags for a given command and data packet */ 70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 71 { 72 uint xfertyp = 0; 73 74 if (data) { 75 xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN; 76 77 if (data->blocks > 1) { 78 xfertyp |= XFERTYP_MSBSEL; 79 xfertyp |= XFERTYP_BCEN; 80 } 81 82 if (data->flags & MMC_DATA_READ) 83 xfertyp |= XFERTYP_DTDSEL; 84 } 85 86 if (cmd->resp_type & MMC_RSP_CRC) 87 xfertyp |= XFERTYP_CCCEN; 88 if (cmd->resp_type & MMC_RSP_OPCODE) 89 xfertyp |= XFERTYP_CICEN; 90 if (cmd->resp_type & MMC_RSP_136) 91 xfertyp |= XFERTYP_RSPTYP_136; 92 else if (cmd->resp_type & MMC_RSP_BUSY) 93 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 94 else if (cmd->resp_type & MMC_RSP_PRESENT) 95 xfertyp |= XFERTYP_RSPTYP_48; 96 97 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 98 } 99 100 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 101 { 102 uint wml_value; 103 int timeout; 104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 105 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 106 107 wml_value = data->blocksize/4; 108 109 if (data->flags & MMC_DATA_READ) { 110 if (wml_value > 0x10) 111 wml_value = 0x10; 112 113 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 114 esdhc_write32(®s->dsaddr, (u32)data->dest); 115 } else { 116 if (wml_value > 0x80) 117 wml_value = 0x80; 118 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 119 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 120 return TIMEOUT; 121 } 122 123 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 124 wml_value << 16); 125 esdhc_write32(®s->dsaddr, (u32)data->src); 126 } 127 128 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 129 130 /* Calculate the timeout period for data transactions */ 131 timeout = fls(mmc->tran_speed/10) - 1; 132 timeout -= 13; 133 134 if (timeout > 14) 135 timeout = 14; 136 137 if (timeout < 0) 138 timeout = 0; 139 140 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 141 142 return 0; 143 } 144 145 146 /* 147 * Sends a command out on the bus. Takes the mmc pointer, 148 * a command pointer, and an optional data pointer. 149 */ 150 static int 151 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 152 { 153 uint xfertyp; 154 uint irqstat; 155 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 156 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 157 158 esdhc_write32(®s->irqstat, -1); 159 160 sync(); 161 162 /* Wait for the bus to be idle */ 163 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 164 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 165 ; 166 167 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 168 ; 169 170 /* Wait at least 8 SD clock cycles before the next command */ 171 /* 172 * Note: This is way more than 8 cycles, but 1ms seems to 173 * resolve timing issues with some cards 174 */ 175 udelay(1000); 176 177 /* Set up for a data transfer if we have one */ 178 if (data) { 179 int err; 180 181 err = esdhc_setup_data(mmc, data); 182 if(err) 183 return err; 184 } 185 186 /* Figure out the transfer arguments */ 187 xfertyp = esdhc_xfertyp(cmd, data); 188 189 /* Send the command */ 190 esdhc_write32(®s->cmdarg, cmd->cmdarg); 191 esdhc_write32(®s->xfertyp, xfertyp); 192 193 /* Wait for the command to complete */ 194 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) 195 ; 196 197 irqstat = esdhc_read32(®s->irqstat); 198 esdhc_write32(®s->irqstat, irqstat); 199 200 if (irqstat & CMD_ERR) 201 return COMM_ERR; 202 203 if (irqstat & IRQSTAT_CTOE) 204 return TIMEOUT; 205 206 /* Copy the response to the response buffer */ 207 if (cmd->resp_type & MMC_RSP_136) { 208 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 209 210 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 211 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 212 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 213 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 214 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 215 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 216 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 217 cmd->response[3] = (cmdrsp0 << 8); 218 } else 219 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 220 221 /* Wait until all of the blocks are transferred */ 222 if (data) { 223 do { 224 irqstat = esdhc_read32(®s->irqstat); 225 226 if (irqstat & DATA_ERR) 227 return COMM_ERR; 228 229 if (irqstat & IRQSTAT_DTOE) 230 return TIMEOUT; 231 } while (!(irqstat & IRQSTAT_TC) && 232 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); 233 } 234 235 esdhc_write32(®s->irqstat, -1); 236 237 return 0; 238 } 239 240 void set_sysctl(struct mmc *mmc, uint clock) 241 { 242 int sdhc_clk = gd->sdhc_clk; 243 int div, pre_div; 244 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 245 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 246 uint clk; 247 248 if (clock < mmc->f_min) 249 clock = mmc->f_min; 250 251 if (sdhc_clk / 16 > clock) { 252 for (pre_div = 2; pre_div < 256; pre_div *= 2) 253 if ((sdhc_clk / pre_div) <= (clock * 16)) 254 break; 255 } else 256 pre_div = 2; 257 258 for (div = 1; div <= 16; div++) 259 if ((sdhc_clk / (div * pre_div)) <= clock) 260 break; 261 262 pre_div >>= 1; 263 div -= 1; 264 265 clk = (pre_div << 8) | (div << 4); 266 267 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 268 269 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 270 271 udelay(10000); 272 273 clk = SYSCTL_PEREN | SYSCTL_CKEN; 274 275 esdhc_setbits32(®s->sysctl, clk); 276 } 277 278 static void esdhc_set_ios(struct mmc *mmc) 279 { 280 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 281 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 282 283 /* Set the clock speed */ 284 set_sysctl(mmc, mmc->clock); 285 286 /* Set the bus width */ 287 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 288 289 if (mmc->bus_width == 4) 290 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 291 else if (mmc->bus_width == 8) 292 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 293 294 } 295 296 static int esdhc_init(struct mmc *mmc) 297 { 298 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 299 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 300 int timeout = 1000; 301 int ret = 0; 302 u8 card_absent; 303 304 /* Enable cache snooping */ 305 if (cfg && !cfg->no_snoop) 306 esdhc_write32(®s->scr, 0x00000040); 307 308 /* Reset the entire host controller */ 309 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 310 311 /* Wait until the controller is available */ 312 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 313 udelay(1000); 314 315 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 316 317 /* Set the initial clock speed */ 318 set_sysctl(mmc, 400000); 319 320 /* Disable the BRR and BWR bits in IRQSTAT */ 321 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 322 323 /* Put the PROCTL reg back to the default */ 324 esdhc_write32(®s->proctl, PROCTL_INIT); 325 326 /* Set timout to the maximum value */ 327 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 328 329 /* Check if there is a callback for detecting the card */ 330 if (board_mmc_getcd(&card_absent, mmc)) { 331 timeout = 1000; 332 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && 333 --timeout) 334 udelay(1000); 335 336 if (timeout <= 0) 337 ret = NO_CARD_ERR; 338 } else { 339 if (card_absent) 340 ret = NO_CARD_ERR; 341 } 342 343 return ret; 344 } 345 346 static void esdhc_reset(struct fsl_esdhc *regs) 347 { 348 unsigned long timeout = 100; /* wait max 100 ms */ 349 350 /* reset the controller */ 351 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 352 353 /* hardware clears the bit when it is done */ 354 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 355 udelay(1000); 356 if (!timeout) 357 printf("MMC/SD: Reset never completed.\n"); 358 } 359 360 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 361 { 362 struct fsl_esdhc *regs; 363 struct mmc *mmc; 364 u32 caps; 365 366 if (!cfg) 367 return -1; 368 369 mmc = malloc(sizeof(struct mmc)); 370 371 sprintf(mmc->name, "FSL_ESDHC"); 372 regs = (struct fsl_esdhc *)cfg->esdhc_base; 373 374 /* First reset the eSDHC controller */ 375 esdhc_reset(regs); 376 377 mmc->priv = cfg; 378 mmc->send_cmd = esdhc_send_cmd; 379 mmc->set_ios = esdhc_set_ios; 380 mmc->init = esdhc_init; 381 382 caps = regs->hostcapblt; 383 384 if (caps & ESDHC_HOSTCAPBLT_VS18) 385 mmc->voltages |= MMC_VDD_165_195; 386 if (caps & ESDHC_HOSTCAPBLT_VS30) 387 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 388 if (caps & ESDHC_HOSTCAPBLT_VS33) 389 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 390 391 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 392 393 if (caps & ESDHC_HOSTCAPBLT_HSS) 394 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 395 396 mmc->f_min = 400000; 397 mmc->f_max = MIN(gd->sdhc_clk, 50000000); 398 399 mmc_register(mmc); 400 401 return 0; 402 } 403 404 int fsl_esdhc_mmc_init(bd_t *bis) 405 { 406 struct fsl_esdhc_cfg *cfg; 407 408 cfg = malloc(sizeof(struct fsl_esdhc_cfg)); 409 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); 410 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 411 return fsl_esdhc_initialize(bis, cfg); 412 } 413 414 #ifdef CONFIG_OF_LIBFDT 415 void fdt_fixup_esdhc(void *blob, bd_t *bd) 416 { 417 const char *compat = "fsl,esdhc"; 418 const char *status = "okay"; 419 420 if (!hwconfig("esdhc")) { 421 status = "disabled"; 422 goto out; 423 } 424 425 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 426 gd->sdhc_clk, 1); 427 out: 428 do_fixup_by_compat(blob, compat, "status", status, 429 strlen(status) + 1, 1); 430 } 431 #endif 432