1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 struct fsl_esdhc { 27 uint dsaddr; /* SDMA system address register */ 28 uint blkattr; /* Block attributes register */ 29 uint cmdarg; /* Command argument register */ 30 uint xfertyp; /* Transfer type register */ 31 uint cmdrsp0; /* Command response 0 register */ 32 uint cmdrsp1; /* Command response 1 register */ 33 uint cmdrsp2; /* Command response 2 register */ 34 uint cmdrsp3; /* Command response 3 register */ 35 uint datport; /* Buffer data port register */ 36 uint prsstat; /* Present state register */ 37 uint proctl; /* Protocol control register */ 38 uint sysctl; /* System Control Register */ 39 uint irqstat; /* Interrupt status register */ 40 uint irqstaten; /* Interrupt status enable register */ 41 uint irqsigen; /* Interrupt signal enable register */ 42 uint autoc12err; /* Auto CMD error status register */ 43 uint hostcapblt; /* Host controller capabilities register */ 44 uint wml; /* Watermark level register */ 45 uint mixctrl; /* For USDHC */ 46 char reserved1[4]; /* reserved */ 47 uint fevt; /* Force event register */ 48 uint admaes; /* ADMA error status register */ 49 uint adsaddr; /* ADMA system address register */ 50 char reserved2[160]; /* reserved */ 51 uint hostver; /* Host controller version register */ 52 char reserved3[4]; /* reserved */ 53 uint dmaerraddr; /* DMA error address register */ 54 char reserved4[4]; /* reserved */ 55 uint dmaerrattr; /* DMA error attribute register */ 56 char reserved5[4]; /* reserved */ 57 uint hostcapblt2; /* Host controller capabilities register 2 */ 58 char reserved6[8]; /* reserved */ 59 uint tcr; /* Tuning control register */ 60 char reserved7[28]; /* reserved */ 61 uint sddirctl; /* SD direction control register */ 62 char reserved8[712]; /* reserved */ 63 uint scr; /* eSDHC control register */ 64 }; 65 66 /* Return the XFERTYP flags for a given command and data packet */ 67 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 68 { 69 uint xfertyp = 0; 70 71 if (data) { 72 xfertyp |= XFERTYP_DPSEL; 73 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 74 xfertyp |= XFERTYP_DMAEN; 75 #endif 76 if (data->blocks > 1) { 77 xfertyp |= XFERTYP_MSBSEL; 78 xfertyp |= XFERTYP_BCEN; 79 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 80 xfertyp |= XFERTYP_AC12EN; 81 #endif 82 } 83 84 if (data->flags & MMC_DATA_READ) 85 xfertyp |= XFERTYP_DTDSEL; 86 } 87 88 if (cmd->resp_type & MMC_RSP_CRC) 89 xfertyp |= XFERTYP_CCCEN; 90 if (cmd->resp_type & MMC_RSP_OPCODE) 91 xfertyp |= XFERTYP_CICEN; 92 if (cmd->resp_type & MMC_RSP_136) 93 xfertyp |= XFERTYP_RSPTYP_136; 94 else if (cmd->resp_type & MMC_RSP_BUSY) 95 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 96 else if (cmd->resp_type & MMC_RSP_PRESENT) 97 xfertyp |= XFERTYP_RSPTYP_48; 98 99 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) 100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 101 xfertyp |= XFERTYP_CMDTYP_ABORT; 102 #endif 103 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 104 } 105 106 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 107 /* 108 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 109 */ 110 static void 111 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 112 { 113 struct fsl_esdhc_cfg *cfg = mmc->priv; 114 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 115 uint blocks; 116 char *buffer; 117 uint databuf; 118 uint size; 119 uint irqstat; 120 uint timeout; 121 122 if (data->flags & MMC_DATA_READ) { 123 blocks = data->blocks; 124 buffer = data->dest; 125 while (blocks) { 126 timeout = PIO_TIMEOUT; 127 size = data->blocksize; 128 irqstat = esdhc_read32(®s->irqstat); 129 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 130 && --timeout); 131 if (timeout <= 0) { 132 printf("\nData Read Failed in PIO Mode."); 133 return; 134 } 135 while (size && (!(irqstat & IRQSTAT_TC))) { 136 udelay(100); /* Wait before last byte transfer complete */ 137 irqstat = esdhc_read32(®s->irqstat); 138 databuf = in_le32(®s->datport); 139 *((uint *)buffer) = databuf; 140 buffer += 4; 141 size -= 4; 142 } 143 blocks--; 144 } 145 } else { 146 blocks = data->blocks; 147 buffer = (char *)data->src; 148 while (blocks) { 149 timeout = PIO_TIMEOUT; 150 size = data->blocksize; 151 irqstat = esdhc_read32(®s->irqstat); 152 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 153 && --timeout); 154 if (timeout <= 0) { 155 printf("\nData Write Failed in PIO Mode."); 156 return; 157 } 158 while (size && (!(irqstat & IRQSTAT_TC))) { 159 udelay(100); /* Wait before last byte transfer complete */ 160 databuf = *((uint *)buffer); 161 buffer += 4; 162 size -= 4; 163 irqstat = esdhc_read32(®s->irqstat); 164 out_le32(®s->datport, databuf); 165 } 166 blocks--; 167 } 168 } 169 } 170 #endif 171 172 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 173 { 174 int timeout; 175 struct fsl_esdhc_cfg *cfg = mmc->priv; 176 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 177 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 178 uint wml_value; 179 180 wml_value = data->blocksize/4; 181 182 if (data->flags & MMC_DATA_READ) { 183 if (wml_value > WML_RD_WML_MAX) 184 wml_value = WML_RD_WML_MAX_VAL; 185 186 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 187 esdhc_write32(®s->dsaddr, (u32)data->dest); 188 } else { 189 flush_dcache_range((ulong)data->src, 190 (ulong)data->src+data->blocks 191 *data->blocksize); 192 193 if (wml_value > WML_WR_WML_MAX) 194 wml_value = WML_WR_WML_MAX_VAL; 195 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 196 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 197 return TIMEOUT; 198 } 199 200 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 201 wml_value << 16); 202 esdhc_write32(®s->dsaddr, (u32)data->src); 203 } 204 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 205 if (!(data->flags & MMC_DATA_READ)) { 206 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 207 printf("\nThe SD card is locked. " 208 "Can not write to a locked card.\n\n"); 209 return TIMEOUT; 210 } 211 esdhc_write32(®s->dsaddr, (u32)data->src); 212 } else 213 esdhc_write32(®s->dsaddr, (u32)data->dest); 214 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 215 216 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 217 218 /* Calculate the timeout period for data transactions */ 219 /* 220 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 221 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 222 * So, Number of SD Clock cycles for 0.25sec should be minimum 223 * (SD Clock/sec * 0.25 sec) SD Clock cycles 224 * = (mmc->clock * 1/4) SD Clock cycles 225 * As 1) >= 2) 226 * => (2^(timeout+13)) >= mmc->clock * 1/4 227 * Taking log2 both the sides 228 * => timeout + 13 >= log2(mmc->clock/4) 229 * Rounding up to next power of 2 230 * => timeout + 13 = log2(mmc->clock/4) + 1 231 * => timeout + 13 = fls(mmc->clock/4) 232 */ 233 timeout = fls(mmc->clock/4); 234 timeout -= 13; 235 236 if (timeout > 14) 237 timeout = 14; 238 239 if (timeout < 0) 240 timeout = 0; 241 242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 243 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 244 timeout++; 245 #endif 246 247 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 248 timeout = 0xE; 249 #endif 250 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 251 252 return 0; 253 } 254 255 static void check_and_invalidate_dcache_range 256 (struct mmc_cmd *cmd, 257 struct mmc_data *data) { 258 unsigned start = (unsigned)data->dest ; 259 unsigned size = roundup(ARCH_DMA_MINALIGN, 260 data->blocks*data->blocksize); 261 unsigned end = start+size ; 262 invalidate_dcache_range(start, end); 263 } 264 /* 265 * Sends a command out on the bus. Takes the mmc pointer, 266 * a command pointer, and an optional data pointer. 267 */ 268 static int 269 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 270 { 271 int err = 0; 272 uint xfertyp; 273 uint irqstat; 274 struct fsl_esdhc_cfg *cfg = mmc->priv; 275 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 276 277 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 278 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 279 return 0; 280 #endif 281 282 esdhc_write32(®s->irqstat, -1); 283 284 sync(); 285 286 /* Wait for the bus to be idle */ 287 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 288 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 289 ; 290 291 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 292 ; 293 294 /* Wait at least 8 SD clock cycles before the next command */ 295 /* 296 * Note: This is way more than 8 cycles, but 1ms seems to 297 * resolve timing issues with some cards 298 */ 299 udelay(1000); 300 301 /* Set up for a data transfer if we have one */ 302 if (data) { 303 err = esdhc_setup_data(mmc, data); 304 if(err) 305 return err; 306 } 307 308 /* Figure out the transfer arguments */ 309 xfertyp = esdhc_xfertyp(cmd, data); 310 311 /* Mask all irqs */ 312 esdhc_write32(®s->irqsigen, 0); 313 314 /* Send the command */ 315 esdhc_write32(®s->cmdarg, cmd->cmdarg); 316 #if defined(CONFIG_FSL_USDHC) 317 esdhc_write32(®s->mixctrl, 318 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); 319 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 320 #else 321 esdhc_write32(®s->xfertyp, xfertyp); 322 #endif 323 324 /* Wait for the command to complete */ 325 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 326 ; 327 328 irqstat = esdhc_read32(®s->irqstat); 329 330 if (irqstat & CMD_ERR) { 331 err = COMM_ERR; 332 goto out; 333 } 334 335 if (irqstat & IRQSTAT_CTOE) { 336 err = TIMEOUT; 337 goto out; 338 } 339 340 /* Workaround for ESDHC errata ENGcm03648 */ 341 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 342 int timeout = 2500; 343 344 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 345 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 346 PRSSTAT_DAT0)) { 347 udelay(100); 348 timeout--; 349 } 350 351 if (timeout <= 0) { 352 printf("Timeout waiting for DAT0 to go high!\n"); 353 err = TIMEOUT; 354 goto out; 355 } 356 } 357 358 /* Copy the response to the response buffer */ 359 if (cmd->resp_type & MMC_RSP_136) { 360 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 361 362 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 363 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 364 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 365 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 366 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 367 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 368 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 369 cmd->response[3] = (cmdrsp0 << 8); 370 } else 371 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 372 373 /* Wait until all of the blocks are transferred */ 374 if (data) { 375 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 376 esdhc_pio_read_write(mmc, data); 377 #else 378 do { 379 irqstat = esdhc_read32(®s->irqstat); 380 381 if (irqstat & IRQSTAT_DTOE) { 382 err = TIMEOUT; 383 goto out; 384 } 385 386 if (irqstat & DATA_ERR) { 387 err = COMM_ERR; 388 goto out; 389 } 390 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 391 #endif 392 if (data->flags & MMC_DATA_READ) 393 check_and_invalidate_dcache_range(cmd, data); 394 } 395 396 out: 397 /* Reset CMD and DATA portions on error */ 398 if (err) { 399 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 400 SYSCTL_RSTC); 401 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 402 ; 403 404 if (data) { 405 esdhc_write32(®s->sysctl, 406 esdhc_read32(®s->sysctl) | 407 SYSCTL_RSTD); 408 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 409 ; 410 } 411 } 412 413 esdhc_write32(®s->irqstat, -1); 414 415 return err; 416 } 417 418 static void set_sysctl(struct mmc *mmc, uint clock) 419 { 420 int div, pre_div; 421 struct fsl_esdhc_cfg *cfg = mmc->priv; 422 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 423 int sdhc_clk = cfg->sdhc_clk; 424 uint clk; 425 426 if (clock < mmc->cfg->f_min) 427 clock = mmc->cfg->f_min; 428 429 if (sdhc_clk / 16 > clock) { 430 for (pre_div = 2; pre_div < 256; pre_div *= 2) 431 if ((sdhc_clk / pre_div) <= (clock * 16)) 432 break; 433 } else 434 pre_div = 2; 435 436 for (div = 1; div <= 16; div++) 437 if ((sdhc_clk / (div * pre_div)) <= clock) 438 break; 439 440 pre_div >>= 1; 441 div -= 1; 442 443 clk = (pre_div << 8) | (div << 4); 444 445 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 446 447 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 448 449 udelay(10000); 450 451 clk = SYSCTL_PEREN | SYSCTL_CKEN; 452 453 esdhc_setbits32(®s->sysctl, clk); 454 } 455 456 static void esdhc_set_ios(struct mmc *mmc) 457 { 458 struct fsl_esdhc_cfg *cfg = mmc->priv; 459 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 460 461 /* Set the clock speed */ 462 set_sysctl(mmc, mmc->clock); 463 464 /* Set the bus width */ 465 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 466 467 if (mmc->bus_width == 4) 468 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 469 else if (mmc->bus_width == 8) 470 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 471 472 } 473 474 static int esdhc_init(struct mmc *mmc) 475 { 476 struct fsl_esdhc_cfg *cfg = mmc->priv; 477 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 478 int timeout = 1000; 479 480 /* Reset the entire host controller */ 481 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 482 483 /* Wait until the controller is available */ 484 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 485 udelay(1000); 486 487 #ifndef ARCH_MXC 488 /* Enable cache snooping */ 489 esdhc_write32(®s->scr, 0x00000040); 490 #endif 491 492 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 493 494 /* Set the initial clock speed */ 495 mmc_set_clock(mmc, 400000); 496 497 /* Disable the BRR and BWR bits in IRQSTAT */ 498 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 499 500 /* Put the PROCTL reg back to the default */ 501 esdhc_write32(®s->proctl, PROCTL_INIT); 502 503 /* Set timout to the maximum value */ 504 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 505 506 return 0; 507 } 508 509 static int esdhc_getcd(struct mmc *mmc) 510 { 511 struct fsl_esdhc_cfg *cfg = mmc->priv; 512 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 513 int timeout = 1000; 514 515 #ifdef CONFIG_ESDHC_DETECT_QUIRK 516 if (CONFIG_ESDHC_DETECT_QUIRK) 517 return 1; 518 #endif 519 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 520 udelay(1000); 521 522 return timeout > 0; 523 } 524 525 static void esdhc_reset(struct fsl_esdhc *regs) 526 { 527 unsigned long timeout = 100; /* wait max 100 ms */ 528 529 /* reset the controller */ 530 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 531 532 /* hardware clears the bit when it is done */ 533 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 534 udelay(1000); 535 if (!timeout) 536 printf("MMC/SD: Reset never completed.\n"); 537 } 538 539 static const struct mmc_ops esdhc_ops = { 540 .send_cmd = esdhc_send_cmd, 541 .set_ios = esdhc_set_ios, 542 .init = esdhc_init, 543 .getcd = esdhc_getcd, 544 }; 545 546 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 547 { 548 struct fsl_esdhc *regs; 549 struct mmc *mmc; 550 u32 caps, voltage_caps; 551 552 if (!cfg) 553 return -1; 554 555 regs = (struct fsl_esdhc *)cfg->esdhc_base; 556 557 /* First reset the eSDHC controller */ 558 esdhc_reset(regs); 559 560 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 561 | SYSCTL_IPGEN | SYSCTL_CKEN); 562 563 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 564 565 voltage_caps = 0; 566 caps = regs->hostcapblt; 567 568 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 569 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 570 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 571 #endif 572 573 /* T4240 host controller capabilities register should have VS33 bit */ 574 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 575 caps = caps | ESDHC_HOSTCAPBLT_VS33; 576 #endif 577 578 if (caps & ESDHC_HOSTCAPBLT_VS18) 579 voltage_caps |= MMC_VDD_165_195; 580 if (caps & ESDHC_HOSTCAPBLT_VS30) 581 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 582 if (caps & ESDHC_HOSTCAPBLT_VS33) 583 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 584 585 cfg->cfg.name = "FSL_SDHC"; 586 cfg->cfg.ops = &esdhc_ops; 587 #ifdef CONFIG_SYS_SD_VOLTAGE 588 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 589 #else 590 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 591 #endif 592 if ((cfg->cfg.voltages & voltage_caps) == 0) { 593 printf("voltage not supported by controller\n"); 594 return -1; 595 } 596 597 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; 598 599 if (cfg->max_bus_width > 0) { 600 if (cfg->max_bus_width < 8) 601 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 602 if (cfg->max_bus_width < 4) 603 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 604 } 605 606 if (caps & ESDHC_HOSTCAPBLT_HSS) 607 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 608 609 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 610 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 611 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 612 #endif 613 614 cfg->cfg.f_min = 400000; 615 cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000); 616 617 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 618 619 mmc = mmc_create(&cfg->cfg, cfg); 620 if (mmc == NULL) 621 return -1; 622 623 return 0; 624 } 625 626 int fsl_esdhc_mmc_init(bd_t *bis) 627 { 628 struct fsl_esdhc_cfg *cfg; 629 630 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 631 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 632 cfg->sdhc_clk = gd->arch.sdhc_clk; 633 return fsl_esdhc_initialize(bis, cfg); 634 } 635 636 #ifdef CONFIG_OF_LIBFDT 637 void fdt_fixup_esdhc(void *blob, bd_t *bd) 638 { 639 const char *compat = "fsl,esdhc"; 640 641 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 642 if (!hwconfig("esdhc")) { 643 do_fixup_by_compat(blob, compat, "status", "disabled", 644 8 + 1, 1); 645 return; 646 } 647 #endif 648 649 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 650 gd->arch.sdhc_clk, 1); 651 652 do_fixup_by_compat(blob, compat, "status", "okay", 653 4 + 1, 1); 654 } 655 #endif 656