1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 27 IRQSTATEN_CINT | \ 28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 31 IRQSTATEN_DINT) 32 33 struct fsl_esdhc { 34 uint dsaddr; /* SDMA system address register */ 35 uint blkattr; /* Block attributes register */ 36 uint cmdarg; /* Command argument register */ 37 uint xfertyp; /* Transfer type register */ 38 uint cmdrsp0; /* Command response 0 register */ 39 uint cmdrsp1; /* Command response 1 register */ 40 uint cmdrsp2; /* Command response 2 register */ 41 uint cmdrsp3; /* Command response 3 register */ 42 uint datport; /* Buffer data port register */ 43 uint prsstat; /* Present state register */ 44 uint proctl; /* Protocol control register */ 45 uint sysctl; /* System Control Register */ 46 uint irqstat; /* Interrupt status register */ 47 uint irqstaten; /* Interrupt status enable register */ 48 uint irqsigen; /* Interrupt signal enable register */ 49 uint autoc12err; /* Auto CMD error status register */ 50 uint hostcapblt; /* Host controller capabilities register */ 51 uint wml; /* Watermark level register */ 52 uint mixctrl; /* For USDHC */ 53 char reserved1[4]; /* reserved */ 54 uint fevt; /* Force event register */ 55 uint admaes; /* ADMA error status register */ 56 uint adsaddr; /* ADMA system address register */ 57 char reserved2[100]; /* reserved */ 58 uint vendorspec; /* Vendor Specific register */ 59 char reserved3[56]; /* reserved */ 60 uint hostver; /* Host controller version register */ 61 char reserved4[4]; /* reserved */ 62 uint dmaerraddr; /* DMA error address register */ 63 char reserved5[4]; /* reserved */ 64 uint dmaerrattr; /* DMA error attribute register */ 65 char reserved6[4]; /* reserved */ 66 uint hostcapblt2; /* Host controller capabilities register 2 */ 67 char reserved7[8]; /* reserved */ 68 uint tcr; /* Tuning control register */ 69 char reserved8[28]; /* reserved */ 70 uint sddirctl; /* SD direction control register */ 71 char reserved9[712]; /* reserved */ 72 uint scr; /* eSDHC control register */ 73 }; 74 75 /* Return the XFERTYP flags for a given command and data packet */ 76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 77 { 78 uint xfertyp = 0; 79 80 if (data) { 81 xfertyp |= XFERTYP_DPSEL; 82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 83 xfertyp |= XFERTYP_DMAEN; 84 #endif 85 if (data->blocks > 1) { 86 xfertyp |= XFERTYP_MSBSEL; 87 xfertyp |= XFERTYP_BCEN; 88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 89 xfertyp |= XFERTYP_AC12EN; 90 #endif 91 } 92 93 if (data->flags & MMC_DATA_READ) 94 xfertyp |= XFERTYP_DTDSEL; 95 } 96 97 if (cmd->resp_type & MMC_RSP_CRC) 98 xfertyp |= XFERTYP_CCCEN; 99 if (cmd->resp_type & MMC_RSP_OPCODE) 100 xfertyp |= XFERTYP_CICEN; 101 if (cmd->resp_type & MMC_RSP_136) 102 xfertyp |= XFERTYP_RSPTYP_136; 103 else if (cmd->resp_type & MMC_RSP_BUSY) 104 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 105 else if (cmd->resp_type & MMC_RSP_PRESENT) 106 xfertyp |= XFERTYP_RSPTYP_48; 107 108 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 109 xfertyp |= XFERTYP_CMDTYP_ABORT; 110 111 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 112 } 113 114 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 115 /* 116 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 117 */ 118 static void 119 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 120 { 121 struct fsl_esdhc_cfg *cfg = mmc->priv; 122 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 123 uint blocks; 124 char *buffer; 125 uint databuf; 126 uint size; 127 uint irqstat; 128 uint timeout; 129 130 if (data->flags & MMC_DATA_READ) { 131 blocks = data->blocks; 132 buffer = data->dest; 133 while (blocks) { 134 timeout = PIO_TIMEOUT; 135 size = data->blocksize; 136 irqstat = esdhc_read32(®s->irqstat); 137 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 138 && --timeout); 139 if (timeout <= 0) { 140 printf("\nData Read Failed in PIO Mode."); 141 return; 142 } 143 while (size && (!(irqstat & IRQSTAT_TC))) { 144 udelay(100); /* Wait before last byte transfer complete */ 145 irqstat = esdhc_read32(®s->irqstat); 146 databuf = in_le32(®s->datport); 147 *((uint *)buffer) = databuf; 148 buffer += 4; 149 size -= 4; 150 } 151 blocks--; 152 } 153 } else { 154 blocks = data->blocks; 155 buffer = (char *)data->src; 156 while (blocks) { 157 timeout = PIO_TIMEOUT; 158 size = data->blocksize; 159 irqstat = esdhc_read32(®s->irqstat); 160 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 161 && --timeout); 162 if (timeout <= 0) { 163 printf("\nData Write Failed in PIO Mode."); 164 return; 165 } 166 while (size && (!(irqstat & IRQSTAT_TC))) { 167 udelay(100); /* Wait before last byte transfer complete */ 168 databuf = *((uint *)buffer); 169 buffer += 4; 170 size -= 4; 171 irqstat = esdhc_read32(®s->irqstat); 172 out_le32(®s->datport, databuf); 173 } 174 blocks--; 175 } 176 } 177 } 178 #endif 179 180 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 181 { 182 int timeout; 183 struct fsl_esdhc_cfg *cfg = mmc->priv; 184 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 185 #ifdef CONFIG_FSL_LAYERSCAPE 186 dma_addr_t addr; 187 #endif 188 uint wml_value; 189 190 wml_value = data->blocksize/4; 191 192 if (data->flags & MMC_DATA_READ) { 193 if (wml_value > WML_RD_WML_MAX) 194 wml_value = WML_RD_WML_MAX_VAL; 195 196 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 197 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 198 #ifdef CONFIG_FSL_LAYERSCAPE 199 addr = virt_to_phys((void *)(data->dest)); 200 if (upper_32_bits(addr)) 201 printf("Error found for upper 32 bits\n"); 202 else 203 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 204 #else 205 esdhc_write32(®s->dsaddr, (u32)data->dest); 206 #endif 207 #endif 208 } else { 209 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 210 flush_dcache_range((ulong)data->src, 211 (ulong)data->src+data->blocks 212 *data->blocksize); 213 #endif 214 if (wml_value > WML_WR_WML_MAX) 215 wml_value = WML_WR_WML_MAX_VAL; 216 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 217 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 218 return TIMEOUT; 219 } 220 221 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 222 wml_value << 16); 223 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 224 #ifdef CONFIG_FSL_LAYERSCAPE 225 addr = virt_to_phys((void *)(data->src)); 226 if (upper_32_bits(addr)) 227 printf("Error found for upper 32 bits\n"); 228 else 229 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 230 #else 231 esdhc_write32(®s->dsaddr, (u32)data->src); 232 #endif 233 #endif 234 } 235 236 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 237 238 /* Calculate the timeout period for data transactions */ 239 /* 240 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 241 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 242 * So, Number of SD Clock cycles for 0.25sec should be minimum 243 * (SD Clock/sec * 0.25 sec) SD Clock cycles 244 * = (mmc->clock * 1/4) SD Clock cycles 245 * As 1) >= 2) 246 * => (2^(timeout+13)) >= mmc->clock * 1/4 247 * Taking log2 both the sides 248 * => timeout + 13 >= log2(mmc->clock/4) 249 * Rounding up to next power of 2 250 * => timeout + 13 = log2(mmc->clock/4) + 1 251 * => timeout + 13 = fls(mmc->clock/4) 252 * 253 * However, the MMC spec "It is strongly recommended for hosts to 254 * implement more than 500ms timeout value even if the card 255 * indicates the 250ms maximum busy length." Even the previous 256 * value of 300ms is known to be insufficient for some cards. 257 * So, we use 258 * => timeout + 13 = fls(mmc->clock/2) 259 */ 260 timeout = fls(mmc->clock/2); 261 timeout -= 13; 262 263 if (timeout > 14) 264 timeout = 14; 265 266 if (timeout < 0) 267 timeout = 0; 268 269 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 270 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 271 timeout++; 272 #endif 273 274 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 275 timeout = 0xE; 276 #endif 277 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 278 279 return 0; 280 } 281 282 static void check_and_invalidate_dcache_range 283 (struct mmc_cmd *cmd, 284 struct mmc_data *data) { 285 #ifdef CONFIG_FSL_LAYERSCAPE 286 unsigned start = 0; 287 #else 288 unsigned start = (unsigned)data->dest ; 289 #endif 290 unsigned size = roundup(ARCH_DMA_MINALIGN, 291 data->blocks*data->blocksize); 292 unsigned end = start+size ; 293 #ifdef CONFIG_FSL_LAYERSCAPE 294 dma_addr_t addr; 295 296 addr = virt_to_phys((void *)(data->dest)); 297 if (upper_32_bits(addr)) 298 printf("Error found for upper 32 bits\n"); 299 else 300 start = lower_32_bits(addr); 301 #endif 302 invalidate_dcache_range(start, end); 303 } 304 305 /* 306 * Sends a command out on the bus. Takes the mmc pointer, 307 * a command pointer, and an optional data pointer. 308 */ 309 static int 310 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 311 { 312 int err = 0; 313 uint xfertyp; 314 uint irqstat; 315 struct fsl_esdhc_cfg *cfg = mmc->priv; 316 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 317 318 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 319 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 320 return 0; 321 #endif 322 323 esdhc_write32(®s->irqstat, -1); 324 325 sync(); 326 327 /* Wait for the bus to be idle */ 328 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 329 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 330 ; 331 332 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 333 ; 334 335 /* Wait at least 8 SD clock cycles before the next command */ 336 /* 337 * Note: This is way more than 8 cycles, but 1ms seems to 338 * resolve timing issues with some cards 339 */ 340 udelay(1000); 341 342 /* Set up for a data transfer if we have one */ 343 if (data) { 344 err = esdhc_setup_data(mmc, data); 345 if(err) 346 return err; 347 348 if (data->flags & MMC_DATA_READ) 349 check_and_invalidate_dcache_range(cmd, data); 350 } 351 352 /* Figure out the transfer arguments */ 353 xfertyp = esdhc_xfertyp(cmd, data); 354 355 /* Mask all irqs */ 356 esdhc_write32(®s->irqsigen, 0); 357 358 /* Send the command */ 359 esdhc_write32(®s->cmdarg, cmd->cmdarg); 360 #if defined(CONFIG_FSL_USDHC) 361 esdhc_write32(®s->mixctrl, 362 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 363 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 364 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 365 #else 366 esdhc_write32(®s->xfertyp, xfertyp); 367 #endif 368 369 /* Wait for the command to complete */ 370 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 371 ; 372 373 irqstat = esdhc_read32(®s->irqstat); 374 375 if (irqstat & CMD_ERR) { 376 err = COMM_ERR; 377 goto out; 378 } 379 380 if (irqstat & IRQSTAT_CTOE) { 381 err = TIMEOUT; 382 goto out; 383 } 384 385 /* Switch voltage to 1.8V if CMD11 succeeded */ 386 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 387 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 388 389 printf("Run CMD11 1.8V switch\n"); 390 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 391 udelay(5000); 392 } 393 394 /* Workaround for ESDHC errata ENGcm03648 */ 395 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 396 int timeout = 6000; 397 398 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 399 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 400 PRSSTAT_DAT0)) { 401 udelay(100); 402 timeout--; 403 } 404 405 if (timeout <= 0) { 406 printf("Timeout waiting for DAT0 to go high!\n"); 407 err = TIMEOUT; 408 goto out; 409 } 410 } 411 412 /* Copy the response to the response buffer */ 413 if (cmd->resp_type & MMC_RSP_136) { 414 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 415 416 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 417 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 418 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 419 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 420 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 421 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 422 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 423 cmd->response[3] = (cmdrsp0 << 8); 424 } else 425 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 426 427 /* Wait until all of the blocks are transferred */ 428 if (data) { 429 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 430 esdhc_pio_read_write(mmc, data); 431 #else 432 do { 433 irqstat = esdhc_read32(®s->irqstat); 434 435 if (irqstat & IRQSTAT_DTOE) { 436 err = TIMEOUT; 437 goto out; 438 } 439 440 if (irqstat & DATA_ERR) { 441 err = COMM_ERR; 442 goto out; 443 } 444 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 445 446 /* 447 * Need invalidate the dcache here again to avoid any 448 * cache-fill during the DMA operations such as the 449 * speculative pre-fetching etc. 450 */ 451 if (data->flags & MMC_DATA_READ) 452 check_and_invalidate_dcache_range(cmd, data); 453 #endif 454 } 455 456 out: 457 /* Reset CMD and DATA portions on error */ 458 if (err) { 459 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 460 SYSCTL_RSTC); 461 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 462 ; 463 464 if (data) { 465 esdhc_write32(®s->sysctl, 466 esdhc_read32(®s->sysctl) | 467 SYSCTL_RSTD); 468 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 469 ; 470 } 471 472 /* If this was CMD11, then notify that power cycle is needed */ 473 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 474 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 475 } 476 477 esdhc_write32(®s->irqstat, -1); 478 479 return err; 480 } 481 482 static void set_sysctl(struct mmc *mmc, uint clock) 483 { 484 int div, pre_div; 485 struct fsl_esdhc_cfg *cfg = mmc->priv; 486 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 487 int sdhc_clk = cfg->sdhc_clk; 488 uint clk; 489 490 if (clock < mmc->cfg->f_min) 491 clock = mmc->cfg->f_min; 492 493 if (sdhc_clk / 16 > clock) { 494 for (pre_div = 2; pre_div < 256; pre_div *= 2) 495 if ((sdhc_clk / pre_div) <= (clock * 16)) 496 break; 497 } else 498 pre_div = 2; 499 500 for (div = 1; div <= 16; div++) 501 if ((sdhc_clk / (div * pre_div)) <= clock) 502 break; 503 504 pre_div >>= mmc->ddr_mode ? 2 : 1; 505 div -= 1; 506 507 clk = (pre_div << 8) | (div << 4); 508 509 #ifdef CONFIG_FSL_USDHC 510 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 511 #else 512 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 513 #endif 514 515 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 516 517 udelay(10000); 518 519 #ifdef CONFIG_FSL_USDHC 520 esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); 521 #else 522 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 523 #endif 524 525 } 526 527 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 528 static void esdhc_clock_control(struct mmc *mmc, bool enable) 529 { 530 struct fsl_esdhc_cfg *cfg = mmc->priv; 531 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 532 u32 value; 533 u32 time_out; 534 535 value = esdhc_read32(®s->sysctl); 536 537 if (enable) 538 value |= SYSCTL_CKEN; 539 else 540 value &= ~SYSCTL_CKEN; 541 542 esdhc_write32(®s->sysctl, value); 543 544 time_out = 20; 545 value = PRSSTAT_SDSTB; 546 while (!(esdhc_read32(®s->prsstat) & value)) { 547 if (time_out == 0) { 548 printf("fsl_esdhc: Internal clock never stabilised.\n"); 549 break; 550 } 551 time_out--; 552 mdelay(1); 553 } 554 } 555 #endif 556 557 static void esdhc_set_ios(struct mmc *mmc) 558 { 559 struct fsl_esdhc_cfg *cfg = mmc->priv; 560 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 561 562 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 563 /* Select to use peripheral clock */ 564 esdhc_clock_control(mmc, false); 565 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 566 esdhc_clock_control(mmc, true); 567 #endif 568 /* Set the clock speed */ 569 set_sysctl(mmc, mmc->clock); 570 571 /* Set the bus width */ 572 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 573 574 if (mmc->bus_width == 4) 575 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 576 else if (mmc->bus_width == 8) 577 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 578 579 } 580 581 static int esdhc_init(struct mmc *mmc) 582 { 583 struct fsl_esdhc_cfg *cfg = mmc->priv; 584 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 585 int timeout = 1000; 586 587 /* Reset the entire host controller */ 588 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 589 590 /* Wait until the controller is available */ 591 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 592 udelay(1000); 593 594 #ifndef ARCH_MXC 595 /* Enable cache snooping */ 596 esdhc_write32(®s->scr, 0x00000040); 597 #endif 598 599 #ifndef CONFIG_FSL_USDHC 600 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 601 #endif 602 603 /* Set the initial clock speed */ 604 mmc_set_clock(mmc, 400000); 605 606 /* Disable the BRR and BWR bits in IRQSTAT */ 607 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 608 609 /* Put the PROCTL reg back to the default */ 610 esdhc_write32(®s->proctl, PROCTL_INIT); 611 612 /* Set timout to the maximum value */ 613 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 614 615 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 616 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 617 #endif 618 619 return 0; 620 } 621 622 static int esdhc_getcd(struct mmc *mmc) 623 { 624 struct fsl_esdhc_cfg *cfg = mmc->priv; 625 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 626 int timeout = 1000; 627 628 #ifdef CONFIG_ESDHC_DETECT_QUIRK 629 if (CONFIG_ESDHC_DETECT_QUIRK) 630 return 1; 631 #endif 632 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 633 udelay(1000); 634 635 return timeout > 0; 636 } 637 638 static void esdhc_reset(struct fsl_esdhc *regs) 639 { 640 unsigned long timeout = 100; /* wait max 100 ms */ 641 642 /* reset the controller */ 643 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 644 645 /* hardware clears the bit when it is done */ 646 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 647 udelay(1000); 648 if (!timeout) 649 printf("MMC/SD: Reset never completed.\n"); 650 } 651 652 static const struct mmc_ops esdhc_ops = { 653 .send_cmd = esdhc_send_cmd, 654 .set_ios = esdhc_set_ios, 655 .init = esdhc_init, 656 .getcd = esdhc_getcd, 657 }; 658 659 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 660 { 661 struct fsl_esdhc *regs; 662 struct mmc *mmc; 663 u32 caps, voltage_caps; 664 665 if (!cfg) 666 return -1; 667 668 regs = (struct fsl_esdhc *)cfg->esdhc_base; 669 670 /* First reset the eSDHC controller */ 671 esdhc_reset(regs); 672 673 #ifndef CONFIG_FSL_USDHC 674 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 675 | SYSCTL_IPGEN | SYSCTL_CKEN); 676 #endif 677 678 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 679 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 680 681 voltage_caps = 0; 682 caps = esdhc_read32(®s->hostcapblt); 683 684 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 685 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 686 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 687 #endif 688 689 /* T4240 host controller capabilities register should have VS33 bit */ 690 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 691 caps = caps | ESDHC_HOSTCAPBLT_VS33; 692 #endif 693 694 if (caps & ESDHC_HOSTCAPBLT_VS18) 695 voltage_caps |= MMC_VDD_165_195; 696 if (caps & ESDHC_HOSTCAPBLT_VS30) 697 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 698 if (caps & ESDHC_HOSTCAPBLT_VS33) 699 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 700 701 cfg->cfg.name = "FSL_SDHC"; 702 cfg->cfg.ops = &esdhc_ops; 703 #ifdef CONFIG_SYS_SD_VOLTAGE 704 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 705 #else 706 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 707 #endif 708 if ((cfg->cfg.voltages & voltage_caps) == 0) { 709 printf("voltage not supported by controller\n"); 710 return -1; 711 } 712 713 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 714 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 715 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; 716 #endif 717 718 if (cfg->max_bus_width > 0) { 719 if (cfg->max_bus_width < 8) 720 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 721 if (cfg->max_bus_width < 4) 722 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 723 } 724 725 if (caps & ESDHC_HOSTCAPBLT_HSS) 726 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 727 728 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 729 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 730 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 731 #endif 732 733 cfg->cfg.f_min = 400000; 734 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); 735 736 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 737 738 mmc = mmc_create(&cfg->cfg, cfg); 739 if (mmc == NULL) 740 return -1; 741 742 return 0; 743 } 744 745 int fsl_esdhc_mmc_init(bd_t *bis) 746 { 747 struct fsl_esdhc_cfg *cfg; 748 749 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 750 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 751 cfg->sdhc_clk = gd->arch.sdhc_clk; 752 return fsl_esdhc_initialize(bis, cfg); 753 } 754 755 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 756 void mmc_adapter_card_type_ident(void) 757 { 758 u8 card_id; 759 u8 value; 760 761 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 762 gd->arch.sdhc_adapter = card_id; 763 764 switch (card_id) { 765 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 766 value = QIXIS_READ(brdcfg[5]); 767 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 768 QIXIS_WRITE(brdcfg[5], value); 769 break; 770 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 771 value = QIXIS_READ(pwr_ctl[1]); 772 value |= QIXIS_EVDD_BY_SDHC_VS; 773 QIXIS_WRITE(pwr_ctl[1], value); 774 break; 775 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 776 value = QIXIS_READ(brdcfg[5]); 777 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 778 QIXIS_WRITE(brdcfg[5], value); 779 break; 780 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 781 break; 782 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 783 break; 784 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 785 break; 786 case QIXIS_ESDHC_NO_ADAPTER: 787 break; 788 default: 789 break; 790 } 791 } 792 #endif 793 794 #ifdef CONFIG_OF_LIBFDT 795 void fdt_fixup_esdhc(void *blob, bd_t *bd) 796 { 797 const char *compat = "fsl,esdhc"; 798 799 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 800 if (!hwconfig("esdhc")) { 801 do_fixup_by_compat(blob, compat, "status", "disabled", 802 8 + 1, 1); 803 return; 804 } 805 #endif 806 807 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 808 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 809 gd->arch.sdhc_clk, 1); 810 #else 811 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 812 gd->arch.sdhc_clk, 1); 813 #endif 814 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 815 do_fixup_by_compat_u32(blob, compat, "adapter-type", 816 (u32)(gd->arch.sdhc_adapter), 1); 817 #endif 818 do_fixup_by_compat(blob, compat, "status", "okay", 819 4 + 1, 1); 820 } 821 #endif 822