1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 4 * Andy Fleming 5 * 6 * Based vaguely on the pxa mmc code: 7 * (C) Copyright 2003 8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <command.h> 14 #include <clk.h> 15 #include <errno.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <part.h> 19 #include <power/regulator.h> 20 #include <malloc.h> 21 #include <fsl_esdhc.h> 22 #include <fdt_support.h> 23 #include <asm/io.h> 24 #include <dm.h> 25 #include <asm-generic/gpio.h> 26 #include <dm/pinctrl.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 31 IRQSTATEN_CINT | \ 32 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 33 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 34 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 35 IRQSTATEN_DINT) 36 #define MAX_TUNING_LOOP 40 37 38 struct fsl_esdhc { 39 uint dsaddr; /* SDMA system address register */ 40 uint blkattr; /* Block attributes register */ 41 uint cmdarg; /* Command argument register */ 42 uint xfertyp; /* Transfer type register */ 43 uint cmdrsp0; /* Command response 0 register */ 44 uint cmdrsp1; /* Command response 1 register */ 45 uint cmdrsp2; /* Command response 2 register */ 46 uint cmdrsp3; /* Command response 3 register */ 47 uint datport; /* Buffer data port register */ 48 uint prsstat; /* Present state register */ 49 uint proctl; /* Protocol control register */ 50 uint sysctl; /* System Control Register */ 51 uint irqstat; /* Interrupt status register */ 52 uint irqstaten; /* Interrupt status enable register */ 53 uint irqsigen; /* Interrupt signal enable register */ 54 uint autoc12err; /* Auto CMD error status register */ 55 uint hostcapblt; /* Host controller capabilities register */ 56 uint wml; /* Watermark level register */ 57 uint mixctrl; /* For USDHC */ 58 char reserved1[4]; /* reserved */ 59 uint fevt; /* Force event register */ 60 uint admaes; /* ADMA error status register */ 61 uint adsaddr; /* ADMA system address register */ 62 char reserved2[4]; 63 uint dllctrl; 64 uint dllstat; 65 uint clktunectrlstatus; 66 char reserved3[4]; 67 uint strobe_dllctrl; 68 uint strobe_dllstat; 69 char reserved4[72]; 70 uint vendorspec; 71 uint mmcboot; 72 uint vendorspec2; 73 uint tuning_ctrl; /* on i.MX6/7/8 */ 74 char reserved5[44]; 75 uint hostver; /* Host controller version register */ 76 char reserved6[4]; /* reserved */ 77 uint dmaerraddr; /* DMA error address register */ 78 char reserved7[4]; /* reserved */ 79 uint dmaerrattr; /* DMA error attribute register */ 80 char reserved8[4]; /* reserved */ 81 uint hostcapblt2; /* Host controller capabilities register 2 */ 82 char reserved9[8]; /* reserved */ 83 uint tcr; /* Tuning control register */ 84 char reserved10[28]; /* reserved */ 85 uint sddirctl; /* SD direction control register */ 86 char reserved11[712];/* reserved */ 87 uint scr; /* eSDHC control register */ 88 }; 89 90 struct fsl_esdhc_plat { 91 struct mmc_config cfg; 92 struct mmc mmc; 93 }; 94 95 struct esdhc_soc_data { 96 u32 flags; 97 u32 caps; 98 }; 99 100 /** 101 * struct fsl_esdhc_priv 102 * 103 * @esdhc_regs: registers of the sdhc controller 104 * @sdhc_clk: Current clk of the sdhc controller 105 * @bus_width: bus width, 1bit, 4bit or 8bit 106 * @cfg: mmc config 107 * @mmc: mmc 108 * Following is used when Driver Model is enabled for MMC 109 * @dev: pointer for the device 110 * @non_removable: 0: removable; 1: non-removable 111 * @wp_enable: 1: enable checking wp; 0: no check 112 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 113 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h 114 * @caps: controller capabilities 115 * @tuning_step: tuning step setting in tuning_ctrl register 116 * @start_tuning_tap: the start point for tuning in tuning_ctrl register 117 * @strobe_dll_delay_target: settings in strobe_dllctrl 118 * @signal_voltage: indicating the current voltage 119 * @cd_gpio: gpio for card detection 120 * @wp_gpio: gpio for write protection 121 */ 122 struct fsl_esdhc_priv { 123 struct fsl_esdhc *esdhc_regs; 124 unsigned int sdhc_clk; 125 struct clk per_clk; 126 unsigned int clock; 127 unsigned int mode; 128 unsigned int bus_width; 129 #if !CONFIG_IS_ENABLED(BLK) 130 struct mmc *mmc; 131 #endif 132 struct udevice *dev; 133 int non_removable; 134 int wp_enable; 135 int vs18_enable; 136 u32 flags; 137 u32 caps; 138 u32 tuning_step; 139 u32 tuning_start_tap; 140 u32 strobe_dll_delay_target; 141 u32 signal_voltage; 142 #if IS_ENABLED(CONFIG_DM_REGULATOR) 143 struct udevice *vqmmc_dev; 144 struct udevice *vmmc_dev; 145 #endif 146 #ifdef CONFIG_DM_GPIO 147 struct gpio_desc cd_gpio; 148 struct gpio_desc wp_gpio; 149 #endif 150 }; 151 152 /* Return the XFERTYP flags for a given command and data packet */ 153 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 154 { 155 uint xfertyp = 0; 156 157 if (data) { 158 xfertyp |= XFERTYP_DPSEL; 159 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 160 xfertyp |= XFERTYP_DMAEN; 161 #endif 162 if (data->blocks > 1) { 163 xfertyp |= XFERTYP_MSBSEL; 164 xfertyp |= XFERTYP_BCEN; 165 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 166 xfertyp |= XFERTYP_AC12EN; 167 #endif 168 } 169 170 if (data->flags & MMC_DATA_READ) 171 xfertyp |= XFERTYP_DTDSEL; 172 } 173 174 if (cmd->resp_type & MMC_RSP_CRC) 175 xfertyp |= XFERTYP_CCCEN; 176 if (cmd->resp_type & MMC_RSP_OPCODE) 177 xfertyp |= XFERTYP_CICEN; 178 if (cmd->resp_type & MMC_RSP_136) 179 xfertyp |= XFERTYP_RSPTYP_136; 180 else if (cmd->resp_type & MMC_RSP_BUSY) 181 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 182 else if (cmd->resp_type & MMC_RSP_PRESENT) 183 xfertyp |= XFERTYP_RSPTYP_48; 184 185 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 186 xfertyp |= XFERTYP_CMDTYP_ABORT; 187 188 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 189 } 190 191 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 192 /* 193 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 194 */ 195 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 196 struct mmc_data *data) 197 { 198 struct fsl_esdhc *regs = priv->esdhc_regs; 199 uint blocks; 200 char *buffer; 201 uint databuf; 202 uint size; 203 uint irqstat; 204 ulong start; 205 206 if (data->flags & MMC_DATA_READ) { 207 blocks = data->blocks; 208 buffer = data->dest; 209 while (blocks) { 210 start = get_timer(0); 211 size = data->blocksize; 212 irqstat = esdhc_read32(®s->irqstat); 213 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { 214 if (get_timer(start) > PIO_TIMEOUT) { 215 printf("\nData Read Failed in PIO Mode."); 216 return; 217 } 218 } 219 while (size && (!(irqstat & IRQSTAT_TC))) { 220 udelay(100); /* Wait before last byte transfer complete */ 221 irqstat = esdhc_read32(®s->irqstat); 222 databuf = in_le32(®s->datport); 223 *((uint *)buffer) = databuf; 224 buffer += 4; 225 size -= 4; 226 } 227 blocks--; 228 } 229 } else { 230 blocks = data->blocks; 231 buffer = (char *)data->src; 232 while (blocks) { 233 start = get_timer(0); 234 size = data->blocksize; 235 irqstat = esdhc_read32(®s->irqstat); 236 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { 237 if (get_timer(start) > PIO_TIMEOUT) { 238 printf("\nData Write Failed in PIO Mode."); 239 return; 240 } 241 } 242 while (size && (!(irqstat & IRQSTAT_TC))) { 243 udelay(100); /* Wait before last byte transfer complete */ 244 databuf = *((uint *)buffer); 245 buffer += 4; 246 size -= 4; 247 irqstat = esdhc_read32(®s->irqstat); 248 out_le32(®s->datport, databuf); 249 } 250 blocks--; 251 } 252 } 253 } 254 #endif 255 256 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 257 struct mmc_data *data) 258 { 259 int timeout; 260 struct fsl_esdhc *regs = priv->esdhc_regs; 261 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 262 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 263 dma_addr_t addr; 264 #endif 265 uint wml_value; 266 267 wml_value = data->blocksize/4; 268 269 if (data->flags & MMC_DATA_READ) { 270 if (wml_value > WML_RD_WML_MAX) 271 wml_value = WML_RD_WML_MAX_VAL; 272 273 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 274 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 275 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 276 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 277 addr = virt_to_phys((void *)(data->dest)); 278 if (upper_32_bits(addr)) 279 printf("Error found for upper 32 bits\n"); 280 else 281 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 282 #else 283 esdhc_write32(®s->dsaddr, (u32)data->dest); 284 #endif 285 #endif 286 } else { 287 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 288 flush_dcache_range((ulong)data->src, 289 (ulong)data->src+data->blocks 290 *data->blocksize); 291 #endif 292 if (wml_value > WML_WR_WML_MAX) 293 wml_value = WML_WR_WML_MAX_VAL; 294 if (priv->wp_enable) { 295 if ((esdhc_read32(®s->prsstat) & 296 PRSSTAT_WPSPL) == 0) { 297 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 298 return -ETIMEDOUT; 299 } 300 } 301 302 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 303 wml_value << 16); 304 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 305 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 306 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 307 addr = virt_to_phys((void *)(data->src)); 308 if (upper_32_bits(addr)) 309 printf("Error found for upper 32 bits\n"); 310 else 311 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 312 #else 313 esdhc_write32(®s->dsaddr, (u32)data->src); 314 #endif 315 #endif 316 } 317 318 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 319 320 /* Calculate the timeout period for data transactions */ 321 /* 322 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 323 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 324 * So, Number of SD Clock cycles for 0.25sec should be minimum 325 * (SD Clock/sec * 0.25 sec) SD Clock cycles 326 * = (mmc->clock * 1/4) SD Clock cycles 327 * As 1) >= 2) 328 * => (2^(timeout+13)) >= mmc->clock * 1/4 329 * Taking log2 both the sides 330 * => timeout + 13 >= log2(mmc->clock/4) 331 * Rounding up to next power of 2 332 * => timeout + 13 = log2(mmc->clock/4) + 1 333 * => timeout + 13 = fls(mmc->clock/4) 334 * 335 * However, the MMC spec "It is strongly recommended for hosts to 336 * implement more than 500ms timeout value even if the card 337 * indicates the 250ms maximum busy length." Even the previous 338 * value of 300ms is known to be insufficient for some cards. 339 * So, we use 340 * => timeout + 13 = fls(mmc->clock/2) 341 */ 342 timeout = fls(mmc->clock/2); 343 timeout -= 13; 344 345 if (timeout > 14) 346 timeout = 14; 347 348 if (timeout < 0) 349 timeout = 0; 350 351 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 352 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 353 timeout++; 354 #endif 355 356 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 357 timeout = 0xE; 358 #endif 359 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 360 361 return 0; 362 } 363 364 static void check_and_invalidate_dcache_range 365 (struct mmc_cmd *cmd, 366 struct mmc_data *data) { 367 unsigned start = 0; 368 unsigned end = 0; 369 unsigned size = roundup(ARCH_DMA_MINALIGN, 370 data->blocks*data->blocksize); 371 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 372 defined(CONFIG_IMX8) || defined(CONFIG_MX8M) 373 dma_addr_t addr; 374 375 addr = virt_to_phys((void *)(data->dest)); 376 if (upper_32_bits(addr)) 377 printf("Error found for upper 32 bits\n"); 378 else 379 start = lower_32_bits(addr); 380 #else 381 start = (unsigned)data->dest; 382 #endif 383 end = start + size; 384 invalidate_dcache_range(start, end); 385 } 386 387 /* 388 * Sends a command out on the bus. Takes the mmc pointer, 389 * a command pointer, and an optional data pointer. 390 */ 391 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, 392 struct mmc_cmd *cmd, struct mmc_data *data) 393 { 394 int err = 0; 395 uint xfertyp; 396 uint irqstat; 397 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; 398 struct fsl_esdhc *regs = priv->esdhc_regs; 399 400 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 401 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 402 return 0; 403 #endif 404 405 esdhc_write32(®s->irqstat, -1); 406 407 sync(); 408 409 /* Wait for the bus to be idle */ 410 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 411 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 412 ; 413 414 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 415 ; 416 417 /* Wait at least 8 SD clock cycles before the next command */ 418 /* 419 * Note: This is way more than 8 cycles, but 1ms seems to 420 * resolve timing issues with some cards 421 */ 422 udelay(1000); 423 424 /* Set up for a data transfer if we have one */ 425 if (data) { 426 err = esdhc_setup_data(priv, mmc, data); 427 if(err) 428 return err; 429 430 if (data->flags & MMC_DATA_READ) 431 check_and_invalidate_dcache_range(cmd, data); 432 } 433 434 /* Figure out the transfer arguments */ 435 xfertyp = esdhc_xfertyp(cmd, data); 436 437 /* Mask all irqs */ 438 esdhc_write32(®s->irqsigen, 0); 439 440 /* Send the command */ 441 esdhc_write32(®s->cmdarg, cmd->cmdarg); 442 #if defined(CONFIG_FSL_USDHC) 443 esdhc_write32(®s->mixctrl, 444 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 445 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 446 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 447 #else 448 esdhc_write32(®s->xfertyp, xfertyp); 449 #endif 450 451 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 452 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) 453 flags = IRQSTAT_BRR; 454 455 /* Wait for the command to complete */ 456 while (!(esdhc_read32(®s->irqstat) & flags)) 457 ; 458 459 irqstat = esdhc_read32(®s->irqstat); 460 461 if (irqstat & CMD_ERR) { 462 err = -ECOMM; 463 goto out; 464 } 465 466 if (irqstat & IRQSTAT_CTOE) { 467 err = -ETIMEDOUT; 468 goto out; 469 } 470 471 /* Switch voltage to 1.8V if CMD11 succeeded */ 472 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 473 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 474 475 printf("Run CMD11 1.8V switch\n"); 476 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 477 udelay(5000); 478 } 479 480 /* Workaround for ESDHC errata ENGcm03648 */ 481 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 482 int timeout = 6000; 483 484 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 485 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 486 PRSSTAT_DAT0)) { 487 udelay(100); 488 timeout--; 489 } 490 491 if (timeout <= 0) { 492 printf("Timeout waiting for DAT0 to go high!\n"); 493 err = -ETIMEDOUT; 494 goto out; 495 } 496 } 497 498 /* Copy the response to the response buffer */ 499 if (cmd->resp_type & MMC_RSP_136) { 500 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 501 502 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 503 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 504 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 505 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 506 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 507 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 508 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 509 cmd->response[3] = (cmdrsp0 << 8); 510 } else 511 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 512 513 /* Wait until all of the blocks are transferred */ 514 if (data) { 515 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 516 esdhc_pio_read_write(priv, data); 517 #else 518 flags = DATA_COMPLETE; 519 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 520 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) { 521 flags = IRQSTAT_BRR; 522 } 523 524 do { 525 irqstat = esdhc_read32(®s->irqstat); 526 527 if (irqstat & IRQSTAT_DTOE) { 528 err = -ETIMEDOUT; 529 goto out; 530 } 531 532 if (irqstat & DATA_ERR) { 533 err = -ECOMM; 534 goto out; 535 } 536 } while ((irqstat & flags) != flags); 537 538 /* 539 * Need invalidate the dcache here again to avoid any 540 * cache-fill during the DMA operations such as the 541 * speculative pre-fetching etc. 542 */ 543 if (data->flags & MMC_DATA_READ) 544 check_and_invalidate_dcache_range(cmd, data); 545 #endif 546 } 547 548 out: 549 /* Reset CMD and DATA portions on error */ 550 if (err) { 551 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 552 SYSCTL_RSTC); 553 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 554 ; 555 556 if (data) { 557 esdhc_write32(®s->sysctl, 558 esdhc_read32(®s->sysctl) | 559 SYSCTL_RSTD); 560 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 561 ; 562 } 563 564 /* If this was CMD11, then notify that power cycle is needed */ 565 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 566 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 567 } 568 569 esdhc_write32(®s->irqstat, -1); 570 571 return err; 572 } 573 574 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 575 { 576 struct fsl_esdhc *regs = priv->esdhc_regs; 577 int div = 1; 578 #ifdef ARCH_MXC 579 #ifdef CONFIG_MX53 580 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 581 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; 582 #else 583 int pre_div = 1; 584 #endif 585 #else 586 int pre_div = 2; 587 #endif 588 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 589 int sdhc_clk = priv->sdhc_clk; 590 uint clk; 591 592 if (clock < mmc->cfg->f_min) 593 clock = mmc->cfg->f_min; 594 595 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 596 pre_div *= 2; 597 598 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 599 div++; 600 601 pre_div >>= 1; 602 div -= 1; 603 604 clk = (pre_div << 8) | (div << 4); 605 606 #ifdef CONFIG_FSL_USDHC 607 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 608 #else 609 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 610 #endif 611 612 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 613 614 udelay(10000); 615 616 #ifdef CONFIG_FSL_USDHC 617 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 618 #else 619 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 620 #endif 621 622 priv->clock = clock; 623 } 624 625 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 626 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 627 { 628 struct fsl_esdhc *regs = priv->esdhc_regs; 629 u32 value; 630 u32 time_out; 631 632 value = esdhc_read32(®s->sysctl); 633 634 if (enable) 635 value |= SYSCTL_CKEN; 636 else 637 value &= ~SYSCTL_CKEN; 638 639 esdhc_write32(®s->sysctl, value); 640 641 time_out = 20; 642 value = PRSSTAT_SDSTB; 643 while (!(esdhc_read32(®s->prsstat) & value)) { 644 if (time_out == 0) { 645 printf("fsl_esdhc: Internal clock never stabilised.\n"); 646 break; 647 } 648 time_out--; 649 mdelay(1); 650 } 651 } 652 #endif 653 654 #ifdef MMC_SUPPORTS_TUNING 655 static int esdhc_change_pinstate(struct udevice *dev) 656 { 657 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 658 int ret; 659 660 switch (priv->mode) { 661 case UHS_SDR50: 662 case UHS_DDR50: 663 ret = pinctrl_select_state(dev, "state_100mhz"); 664 break; 665 case UHS_SDR104: 666 case MMC_HS_200: 667 case MMC_HS_400: 668 ret = pinctrl_select_state(dev, "state_200mhz"); 669 break; 670 default: 671 ret = pinctrl_select_state(dev, "default"); 672 break; 673 } 674 675 if (ret) 676 printf("%s %d error\n", __func__, priv->mode); 677 678 return ret; 679 } 680 681 static void esdhc_reset_tuning(struct mmc *mmc) 682 { 683 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 684 struct fsl_esdhc *regs = priv->esdhc_regs; 685 686 if (priv->flags & ESDHC_FLAG_USDHC) { 687 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 688 esdhc_clrbits32(®s->autoc12err, 689 MIX_CTRL_SMPCLK_SEL | 690 MIX_CTRL_EXE_TUNE); 691 } 692 } 693 } 694 695 static void esdhc_set_strobe_dll(struct mmc *mmc) 696 { 697 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 698 struct fsl_esdhc *regs = priv->esdhc_regs; 699 u32 val; 700 701 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { 702 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl); 703 704 /* 705 * enable strobe dll ctrl and adjust the delay target 706 * for the uSDHC loopback read clock 707 */ 708 val = ESDHC_STROBE_DLL_CTRL_ENABLE | 709 (priv->strobe_dll_delay_target << 710 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 711 writel(val, ®s->strobe_dllctrl); 712 /* wait 1us to make sure strobe dll status register stable */ 713 mdelay(1); 714 val = readl(®s->strobe_dllstat); 715 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) 716 pr_warn("HS400 strobe DLL status REF not lock!\n"); 717 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 718 pr_warn("HS400 strobe DLL status SLV not lock!\n"); 719 } 720 } 721 722 static int esdhc_set_timing(struct mmc *mmc) 723 { 724 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 725 struct fsl_esdhc *regs = priv->esdhc_regs; 726 u32 mixctrl; 727 728 mixctrl = readl(®s->mixctrl); 729 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); 730 731 switch (mmc->selected_mode) { 732 case MMC_LEGACY: 733 case SD_LEGACY: 734 esdhc_reset_tuning(mmc); 735 writel(mixctrl, ®s->mixctrl); 736 break; 737 case MMC_HS_400: 738 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; 739 writel(mixctrl, ®s->mixctrl); 740 esdhc_set_strobe_dll(mmc); 741 break; 742 case MMC_HS: 743 case MMC_HS_52: 744 case MMC_HS_200: 745 case SD_HS: 746 case UHS_SDR12: 747 case UHS_SDR25: 748 case UHS_SDR50: 749 case UHS_SDR104: 750 writel(mixctrl, ®s->mixctrl); 751 break; 752 case UHS_DDR50: 753 case MMC_DDR_52: 754 mixctrl |= MIX_CTRL_DDREN; 755 writel(mixctrl, ®s->mixctrl); 756 break; 757 default: 758 printf("Not supported %d\n", mmc->selected_mode); 759 return -EINVAL; 760 } 761 762 priv->mode = mmc->selected_mode; 763 764 return esdhc_change_pinstate(mmc->dev); 765 } 766 767 static int esdhc_set_voltage(struct mmc *mmc) 768 { 769 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 770 struct fsl_esdhc *regs = priv->esdhc_regs; 771 int ret; 772 773 priv->signal_voltage = mmc->signal_voltage; 774 switch (mmc->signal_voltage) { 775 case MMC_SIGNAL_VOLTAGE_330: 776 if (priv->vs18_enable) 777 return -EIO; 778 #ifdef CONFIG_DM_REGULATOR 779 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 780 ret = regulator_set_value(priv->vqmmc_dev, 3300000); 781 if (ret) { 782 printf("Setting to 3.3V error"); 783 return -EIO; 784 } 785 /* Wait for 5ms */ 786 mdelay(5); 787 } 788 #endif 789 790 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 791 if (!(esdhc_read32(®s->vendorspec) & 792 ESDHC_VENDORSPEC_VSELECT)) 793 return 0; 794 795 return -EAGAIN; 796 case MMC_SIGNAL_VOLTAGE_180: 797 #ifdef CONFIG_DM_REGULATOR 798 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 799 ret = regulator_set_value(priv->vqmmc_dev, 1800000); 800 if (ret) { 801 printf("Setting to 1.8V error"); 802 return -EIO; 803 } 804 } 805 #endif 806 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 807 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) 808 return 0; 809 810 return -EAGAIN; 811 case MMC_SIGNAL_VOLTAGE_120: 812 return -ENOTSUPP; 813 default: 814 return 0; 815 } 816 } 817 818 static void esdhc_stop_tuning(struct mmc *mmc) 819 { 820 struct mmc_cmd cmd; 821 822 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 823 cmd.cmdarg = 0; 824 cmd.resp_type = MMC_RSP_R1b; 825 826 dm_mmc_send_cmd(mmc->dev, &cmd, NULL); 827 } 828 829 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) 830 { 831 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 832 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 833 struct fsl_esdhc *regs = priv->esdhc_regs; 834 struct mmc *mmc = &plat->mmc; 835 u32 irqstaten = readl(®s->irqstaten); 836 u32 irqsigen = readl(®s->irqsigen); 837 int i, ret = -ETIMEDOUT; 838 u32 val, mixctrl; 839 840 /* clock tuning is not needed for upto 52MHz */ 841 if (mmc->clock <= 52000000) 842 return 0; 843 844 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ 845 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 846 val = readl(®s->autoc12err); 847 mixctrl = readl(®s->mixctrl); 848 val &= ~MIX_CTRL_SMPCLK_SEL; 849 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); 850 851 val |= MIX_CTRL_EXE_TUNE; 852 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; 853 854 writel(val, ®s->autoc12err); 855 writel(mixctrl, ®s->mixctrl); 856 } 857 858 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ 859 mixctrl = readl(®s->mixctrl); 860 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); 861 writel(mixctrl, ®s->mixctrl); 862 863 writel(IRQSTATEN_BRR, ®s->irqstaten); 864 writel(IRQSTATEN_BRR, ®s->irqsigen); 865 866 /* 867 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 868 * of loops reaches 40 times. 869 */ 870 for (i = 0; i < MAX_TUNING_LOOP; i++) { 871 u32 ctrl; 872 873 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { 874 if (mmc->bus_width == 8) 875 writel(0x7080, ®s->blkattr); 876 else if (mmc->bus_width == 4) 877 writel(0x7040, ®s->blkattr); 878 } else { 879 writel(0x7040, ®s->blkattr); 880 } 881 882 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ 883 val = readl(®s->mixctrl); 884 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); 885 writel(val, ®s->mixctrl); 886 887 /* We are using STD tuning, no need to check return value */ 888 mmc_send_tuning(mmc, opcode, NULL); 889 890 ctrl = readl(®s->autoc12err); 891 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && 892 (ctrl & MIX_CTRL_SMPCLK_SEL)) { 893 /* 894 * need to wait some time, make sure sd/mmc fininsh 895 * send out tuning data, otherwise, the sd/mmc can't 896 * response to any command when the card still out 897 * put the tuning data. 898 */ 899 mdelay(1); 900 ret = 0; 901 break; 902 } 903 904 /* Add 1ms delay for SD and eMMC */ 905 mdelay(1); 906 } 907 908 writel(irqstaten, ®s->irqstaten); 909 writel(irqsigen, ®s->irqsigen); 910 911 esdhc_stop_tuning(mmc); 912 913 return ret; 914 } 915 #endif 916 917 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 918 { 919 struct fsl_esdhc *regs = priv->esdhc_regs; 920 int ret __maybe_unused; 921 922 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 923 /* Select to use peripheral clock */ 924 esdhc_clock_control(priv, false); 925 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 926 esdhc_clock_control(priv, true); 927 #endif 928 /* Set the clock speed */ 929 if (priv->clock != mmc->clock) 930 set_sysctl(priv, mmc, mmc->clock); 931 932 #ifdef MMC_SUPPORTS_TUNING 933 if (mmc->clk_disable) { 934 #ifdef CONFIG_FSL_USDHC 935 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 936 #else 937 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 938 #endif 939 } else { 940 #ifdef CONFIG_FSL_USDHC 941 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 942 VENDORSPEC_CKEN); 943 #else 944 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 945 #endif 946 } 947 948 if (priv->mode != mmc->selected_mode) { 949 ret = esdhc_set_timing(mmc); 950 if (ret) { 951 printf("esdhc_set_timing error %d\n", ret); 952 return ret; 953 } 954 } 955 956 if (priv->signal_voltage != mmc->signal_voltage) { 957 ret = esdhc_set_voltage(mmc); 958 if (ret) { 959 printf("esdhc_set_voltage error %d\n", ret); 960 return ret; 961 } 962 } 963 #endif 964 965 /* Set the bus width */ 966 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 967 968 if (mmc->bus_width == 4) 969 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 970 else if (mmc->bus_width == 8) 971 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 972 973 return 0; 974 } 975 976 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 977 { 978 struct fsl_esdhc *regs = priv->esdhc_regs; 979 ulong start; 980 981 /* Reset the entire host controller */ 982 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 983 984 /* Wait until the controller is available */ 985 start = get_timer(0); 986 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 987 if (get_timer(start) > 1000) 988 return -ETIMEDOUT; 989 } 990 991 #if defined(CONFIG_FSL_USDHC) 992 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 993 esdhc_write32(®s->mmcboot, 0x0); 994 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 995 esdhc_write32(®s->mixctrl, 0x0); 996 esdhc_write32(®s->clktunectrlstatus, 0x0); 997 998 /* Put VEND_SPEC to default value */ 999 if (priv->vs18_enable) 1000 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | 1001 ESDHC_VENDORSPEC_VSELECT)); 1002 else 1003 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 1004 1005 /* Disable DLL_CTRL delay line */ 1006 esdhc_write32(®s->dllctrl, 0x0); 1007 #endif 1008 1009 #ifndef ARCH_MXC 1010 /* Enable cache snooping */ 1011 esdhc_write32(®s->scr, 0x00000040); 1012 #endif 1013 1014 #ifndef CONFIG_FSL_USDHC 1015 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 1016 #else 1017 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 1018 #endif 1019 1020 /* Set the initial clock speed */ 1021 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); 1022 1023 /* Disable the BRR and BWR bits in IRQSTAT */ 1024 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 1025 1026 /* Put the PROCTL reg back to the default */ 1027 esdhc_write32(®s->proctl, PROCTL_INIT); 1028 1029 /* Set timout to the maximum value */ 1030 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 1031 1032 return 0; 1033 } 1034 1035 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) 1036 { 1037 struct fsl_esdhc *regs = priv->esdhc_regs; 1038 int timeout = 1000; 1039 1040 #ifdef CONFIG_ESDHC_DETECT_QUIRK 1041 if (CONFIG_ESDHC_DETECT_QUIRK) 1042 return 1; 1043 #endif 1044 1045 #if CONFIG_IS_ENABLED(DM_MMC) 1046 if (priv->non_removable) 1047 return 1; 1048 #ifdef CONFIG_DM_GPIO 1049 if (dm_gpio_is_valid(&priv->cd_gpio)) 1050 return dm_gpio_get_value(&priv->cd_gpio); 1051 #endif 1052 #endif 1053 1054 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 1055 udelay(1000); 1056 1057 return timeout > 0; 1058 } 1059 1060 static int esdhc_reset(struct fsl_esdhc *regs) 1061 { 1062 ulong start; 1063 1064 /* reset the controller */ 1065 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 1066 1067 /* hardware clears the bit when it is done */ 1068 start = get_timer(0); 1069 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 1070 if (get_timer(start) > 100) { 1071 printf("MMC/SD: Reset never completed.\n"); 1072 return -ETIMEDOUT; 1073 } 1074 } 1075 1076 return 0; 1077 } 1078 1079 #if !CONFIG_IS_ENABLED(DM_MMC) 1080 static int esdhc_getcd(struct mmc *mmc) 1081 { 1082 struct fsl_esdhc_priv *priv = mmc->priv; 1083 1084 return esdhc_getcd_common(priv); 1085 } 1086 1087 static int esdhc_init(struct mmc *mmc) 1088 { 1089 struct fsl_esdhc_priv *priv = mmc->priv; 1090 1091 return esdhc_init_common(priv, mmc); 1092 } 1093 1094 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 1095 struct mmc_data *data) 1096 { 1097 struct fsl_esdhc_priv *priv = mmc->priv; 1098 1099 return esdhc_send_cmd_common(priv, mmc, cmd, data); 1100 } 1101 1102 static int esdhc_set_ios(struct mmc *mmc) 1103 { 1104 struct fsl_esdhc_priv *priv = mmc->priv; 1105 1106 return esdhc_set_ios_common(priv, mmc); 1107 } 1108 1109 static const struct mmc_ops esdhc_ops = { 1110 .getcd = esdhc_getcd, 1111 .init = esdhc_init, 1112 .send_cmd = esdhc_send_cmd, 1113 .set_ios = esdhc_set_ios, 1114 }; 1115 #endif 1116 1117 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, 1118 struct fsl_esdhc_plat *plat) 1119 { 1120 struct mmc_config *cfg; 1121 struct fsl_esdhc *regs; 1122 u32 caps, voltage_caps; 1123 int ret; 1124 1125 if (!priv) 1126 return -EINVAL; 1127 1128 regs = priv->esdhc_regs; 1129 1130 /* First reset the eSDHC controller */ 1131 ret = esdhc_reset(regs); 1132 if (ret) 1133 return ret; 1134 1135 #ifndef CONFIG_FSL_USDHC 1136 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 1137 | SYSCTL_IPGEN | SYSCTL_CKEN); 1138 /* Clearing tuning bits in case ROM has set it already */ 1139 esdhc_write32(®s->mixctrl, 0); 1140 esdhc_write32(®s->autoc12err, 0); 1141 esdhc_write32(®s->clktunectrlstatus, 0); 1142 #else 1143 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 1144 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 1145 #endif 1146 1147 if (priv->vs18_enable) 1148 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 1149 1150 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 1151 cfg = &plat->cfg; 1152 #ifndef CONFIG_DM_MMC 1153 memset(cfg, '\0', sizeof(*cfg)); 1154 #endif 1155 1156 voltage_caps = 0; 1157 caps = esdhc_read32(®s->hostcapblt); 1158 1159 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 1160 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 1161 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 1162 #endif 1163 1164 /* T4240 host controller capabilities register should have VS33 bit */ 1165 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 1166 caps = caps | ESDHC_HOSTCAPBLT_VS33; 1167 #endif 1168 1169 if (caps & ESDHC_HOSTCAPBLT_VS18) 1170 voltage_caps |= MMC_VDD_165_195; 1171 if (caps & ESDHC_HOSTCAPBLT_VS30) 1172 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 1173 if (caps & ESDHC_HOSTCAPBLT_VS33) 1174 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 1175 1176 cfg->name = "FSL_SDHC"; 1177 #if !CONFIG_IS_ENABLED(DM_MMC) 1178 cfg->ops = &esdhc_ops; 1179 #endif 1180 #ifdef CONFIG_SYS_SD_VOLTAGE 1181 cfg->voltages = CONFIG_SYS_SD_VOLTAGE; 1182 #else 1183 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 1184 #endif 1185 if ((cfg->voltages & voltage_caps) == 0) { 1186 printf("voltage not supported by controller\n"); 1187 return -1; 1188 } 1189 1190 if (priv->bus_width == 8) 1191 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1192 else if (priv->bus_width == 4) 1193 cfg->host_caps = MMC_MODE_4BIT; 1194 1195 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1196 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 1197 cfg->host_caps |= MMC_MODE_DDR_52MHz; 1198 #endif 1199 1200 if (priv->bus_width > 0) { 1201 if (priv->bus_width < 8) 1202 cfg->host_caps &= ~MMC_MODE_8BIT; 1203 if (priv->bus_width < 4) 1204 cfg->host_caps &= ~MMC_MODE_4BIT; 1205 } 1206 1207 if (caps & ESDHC_HOSTCAPBLT_HSS) 1208 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1209 1210 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 1211 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 1212 cfg->host_caps &= ~MMC_MODE_8BIT; 1213 #endif 1214 1215 cfg->host_caps |= priv->caps; 1216 1217 cfg->f_min = 400000; 1218 cfg->f_max = min(priv->sdhc_clk, (u32)200000000); 1219 1220 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1221 1222 writel(0, ®s->dllctrl); 1223 if (priv->flags & ESDHC_FLAG_USDHC) { 1224 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 1225 u32 val = readl(®s->tuning_ctrl); 1226 1227 val |= ESDHC_STD_TUNING_EN; 1228 val &= ~ESDHC_TUNING_START_TAP_MASK; 1229 val |= priv->tuning_start_tap; 1230 val &= ~ESDHC_TUNING_STEP_MASK; 1231 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT; 1232 writel(val, ®s->tuning_ctrl); 1233 } 1234 } 1235 1236 return 0; 1237 } 1238 1239 #if !CONFIG_IS_ENABLED(DM_MMC) 1240 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 1241 struct fsl_esdhc_priv *priv) 1242 { 1243 if (!cfg || !priv) 1244 return -EINVAL; 1245 1246 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 1247 priv->bus_width = cfg->max_bus_width; 1248 priv->sdhc_clk = cfg->sdhc_clk; 1249 priv->wp_enable = cfg->wp_enable; 1250 priv->vs18_enable = cfg->vs18_enable; 1251 1252 return 0; 1253 }; 1254 1255 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 1256 { 1257 struct fsl_esdhc_plat *plat; 1258 struct fsl_esdhc_priv *priv; 1259 struct mmc *mmc; 1260 int ret; 1261 1262 if (!cfg) 1263 return -EINVAL; 1264 1265 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 1266 if (!priv) 1267 return -ENOMEM; 1268 plat = calloc(sizeof(struct fsl_esdhc_plat), 1); 1269 if (!plat) { 1270 free(priv); 1271 return -ENOMEM; 1272 } 1273 1274 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 1275 if (ret) { 1276 debug("%s xlate failure\n", __func__); 1277 free(plat); 1278 free(priv); 1279 return ret; 1280 } 1281 1282 ret = fsl_esdhc_init(priv, plat); 1283 if (ret) { 1284 debug("%s init failure\n", __func__); 1285 free(plat); 1286 free(priv); 1287 return ret; 1288 } 1289 1290 mmc = mmc_create(&plat->cfg, priv); 1291 if (!mmc) 1292 return -EIO; 1293 1294 priv->mmc = mmc; 1295 1296 return 0; 1297 } 1298 1299 int fsl_esdhc_mmc_init(bd_t *bis) 1300 { 1301 struct fsl_esdhc_cfg *cfg; 1302 1303 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 1304 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 1305 cfg->sdhc_clk = gd->arch.sdhc_clk; 1306 return fsl_esdhc_initialize(bis, cfg); 1307 } 1308 #endif 1309 1310 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1311 void mmc_adapter_card_type_ident(void) 1312 { 1313 u8 card_id; 1314 u8 value; 1315 1316 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 1317 gd->arch.sdhc_adapter = card_id; 1318 1319 switch (card_id) { 1320 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 1321 value = QIXIS_READ(brdcfg[5]); 1322 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 1323 QIXIS_WRITE(brdcfg[5], value); 1324 break; 1325 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 1326 value = QIXIS_READ(pwr_ctl[1]); 1327 value |= QIXIS_EVDD_BY_SDHC_VS; 1328 QIXIS_WRITE(pwr_ctl[1], value); 1329 break; 1330 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 1331 value = QIXIS_READ(brdcfg[5]); 1332 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 1333 QIXIS_WRITE(brdcfg[5], value); 1334 break; 1335 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 1336 break; 1337 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 1338 break; 1339 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 1340 break; 1341 case QIXIS_ESDHC_NO_ADAPTER: 1342 break; 1343 default: 1344 break; 1345 } 1346 } 1347 #endif 1348 1349 #ifdef CONFIG_OF_LIBFDT 1350 __weak int esdhc_status_fixup(void *blob, const char *compat) 1351 { 1352 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 1353 if (!hwconfig("esdhc")) { 1354 do_fixup_by_compat(blob, compat, "status", "disabled", 1355 sizeof("disabled"), 1); 1356 return 1; 1357 } 1358 #endif 1359 return 0; 1360 } 1361 1362 void fdt_fixup_esdhc(void *blob, bd_t *bd) 1363 { 1364 const char *compat = "fsl,esdhc"; 1365 1366 if (esdhc_status_fixup(blob, compat)) 1367 return; 1368 1369 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 1370 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 1371 gd->arch.sdhc_clk, 1); 1372 #else 1373 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 1374 gd->arch.sdhc_clk, 1); 1375 #endif 1376 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1377 do_fixup_by_compat_u32(blob, compat, "adapter-type", 1378 (u32)(gd->arch.sdhc_adapter), 1); 1379 #endif 1380 } 1381 #endif 1382 1383 #if CONFIG_IS_ENABLED(DM_MMC) 1384 #include <asm/arch/clock.h> 1385 __weak void init_clk_usdhc(u32 index) 1386 { 1387 } 1388 1389 static int fsl_esdhc_probe(struct udevice *dev) 1390 { 1391 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1392 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1393 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1394 const void *fdt = gd->fdt_blob; 1395 int node = dev_of_offset(dev); 1396 struct esdhc_soc_data *data = 1397 (struct esdhc_soc_data *)dev_get_driver_data(dev); 1398 #ifdef CONFIG_DM_REGULATOR 1399 struct udevice *vqmmc_dev; 1400 #endif 1401 fdt_addr_t addr; 1402 unsigned int val; 1403 struct mmc *mmc; 1404 int ret; 1405 1406 addr = dev_read_addr(dev); 1407 if (addr == FDT_ADDR_T_NONE) 1408 return -EINVAL; 1409 1410 priv->esdhc_regs = (struct fsl_esdhc *)addr; 1411 priv->dev = dev; 1412 priv->mode = -1; 1413 if (data) { 1414 priv->flags = data->flags; 1415 priv->caps = data->caps; 1416 } 1417 1418 val = dev_read_u32_default(dev, "bus-width", -1); 1419 if (val == 8) 1420 priv->bus_width = 8; 1421 else if (val == 4) 1422 priv->bus_width = 4; 1423 else 1424 priv->bus_width = 1; 1425 1426 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1); 1427 priv->tuning_step = val; 1428 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", 1429 ESDHC_TUNING_START_TAP_DEFAULT); 1430 priv->tuning_start_tap = val; 1431 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", 1432 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); 1433 priv->strobe_dll_delay_target = val; 1434 1435 if (dev_read_bool(dev, "non-removable")) { 1436 priv->non_removable = 1; 1437 } else { 1438 priv->non_removable = 0; 1439 #ifdef CONFIG_DM_GPIO 1440 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 1441 GPIOD_IS_IN); 1442 #endif 1443 } 1444 1445 priv->wp_enable = 1; 1446 1447 #ifdef CONFIG_DM_GPIO 1448 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 1449 GPIOD_IS_IN); 1450 if (ret) 1451 priv->wp_enable = 0; 1452 #endif 1453 1454 priv->vs18_enable = 0; 1455 1456 #ifdef CONFIG_DM_REGULATOR 1457 /* 1458 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1459 * otherwise, emmc will work abnormally. 1460 */ 1461 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1462 if (ret) { 1463 dev_dbg(dev, "no vqmmc-supply\n"); 1464 } else { 1465 ret = regulator_set_enable(vqmmc_dev, true); 1466 if (ret) { 1467 dev_err(dev, "fail to enable vqmmc-supply\n"); 1468 return ret; 1469 } 1470 1471 if (regulator_get_value(vqmmc_dev) == 1800000) 1472 priv->vs18_enable = 1; 1473 } 1474 #endif 1475 1476 if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) 1477 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400); 1478 1479 /* 1480 * TODO: 1481 * Because lack of clk driver, if SDHC clk is not enabled, 1482 * need to enable it first before this driver is invoked. 1483 * 1484 * we use MXC_ESDHC_CLK to get clk freq. 1485 * If one would like to make this function work, 1486 * the aliases should be provided in dts as this: 1487 * 1488 * aliases { 1489 * mmc0 = &usdhc1; 1490 * mmc1 = &usdhc2; 1491 * mmc2 = &usdhc3; 1492 * mmc3 = &usdhc4; 1493 * }; 1494 * Then if your board only supports mmc2 and mmc3, but we can 1495 * correctly get the seq as 2 and 3, then let mxc_get_clock 1496 * work as expected. 1497 */ 1498 1499 init_clk_usdhc(dev->seq); 1500 1501 if (IS_ENABLED(CONFIG_CLK)) { 1502 /* Assigned clock already set clock */ 1503 ret = clk_get_by_name(dev, "per", &priv->per_clk); 1504 if (ret) { 1505 printf("Failed to get per_clk\n"); 1506 return ret; 1507 } 1508 ret = clk_enable(&priv->per_clk); 1509 if (ret) { 1510 printf("Failed to enable per_clk\n"); 1511 return ret; 1512 } 1513 1514 priv->sdhc_clk = clk_get_rate(&priv->per_clk); 1515 } else { 1516 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1517 if (priv->sdhc_clk <= 0) { 1518 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1519 return -EINVAL; 1520 } 1521 } 1522 1523 ret = fsl_esdhc_init(priv, plat); 1524 if (ret) { 1525 dev_err(dev, "fsl_esdhc_init failure\n"); 1526 return ret; 1527 } 1528 1529 mmc = &plat->mmc; 1530 mmc->cfg = &plat->cfg; 1531 mmc->dev = dev; 1532 upriv->mmc = mmc; 1533 1534 return esdhc_init_common(priv, mmc); 1535 } 1536 1537 #if CONFIG_IS_ENABLED(DM_MMC) 1538 static int fsl_esdhc_get_cd(struct udevice *dev) 1539 { 1540 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1541 1542 return true; 1543 return esdhc_getcd_common(priv); 1544 } 1545 1546 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 1547 struct mmc_data *data) 1548 { 1549 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1550 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1551 1552 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); 1553 } 1554 1555 static int fsl_esdhc_set_ios(struct udevice *dev) 1556 { 1557 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1558 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1559 1560 return esdhc_set_ios_common(priv, &plat->mmc); 1561 } 1562 1563 static const struct dm_mmc_ops fsl_esdhc_ops = { 1564 .get_cd = fsl_esdhc_get_cd, 1565 .send_cmd = fsl_esdhc_send_cmd, 1566 .set_ios = fsl_esdhc_set_ios, 1567 #ifdef MMC_SUPPORTS_TUNING 1568 .execute_tuning = fsl_esdhc_execute_tuning, 1569 #endif 1570 }; 1571 #endif 1572 1573 static struct esdhc_soc_data usdhc_imx7d_data = { 1574 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1575 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 1576 | ESDHC_FLAG_HS400, 1577 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | 1578 MMC_MODE_HS_52MHz | MMC_MODE_HS, 1579 }; 1580 1581 static const struct udevice_id fsl_esdhc_ids[] = { 1582 { .compatible = "fsl,imx6ul-usdhc", }, 1583 { .compatible = "fsl,imx6sx-usdhc", }, 1584 { .compatible = "fsl,imx6sl-usdhc", }, 1585 { .compatible = "fsl,imx6q-usdhc", }, 1586 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, 1587 { .compatible = "fsl,imx7ulp-usdhc", }, 1588 { .compatible = "fsl,esdhc", }, 1589 { /* sentinel */ } 1590 }; 1591 1592 #if CONFIG_IS_ENABLED(BLK) 1593 static int fsl_esdhc_bind(struct udevice *dev) 1594 { 1595 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1596 1597 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1598 } 1599 #endif 1600 1601 U_BOOT_DRIVER(fsl_esdhc) = { 1602 .name = "fsl-esdhc-mmc", 1603 .id = UCLASS_MMC, 1604 .of_match = fsl_esdhc_ids, 1605 .ops = &fsl_esdhc_ops, 1606 #if CONFIG_IS_ENABLED(BLK) 1607 .bind = fsl_esdhc_bind, 1608 #endif 1609 .probe = fsl_esdhc_probe, 1610 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), 1611 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1612 }; 1613 #endif 1614