1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 4 * Andy Fleming 5 * 6 * Based vaguely on the pxa mmc code: 7 * (C) Copyright 2003 8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <command.h> 14 #include <errno.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <power/regulator.h> 19 #include <malloc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 #include <dm.h> 24 #include <asm-generic/gpio.h> 25 #include <dm/pinctrl.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 30 IRQSTATEN_CINT | \ 31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 34 IRQSTATEN_DINT) 35 #define MAX_TUNING_LOOP 40 36 37 struct fsl_esdhc { 38 uint dsaddr; /* SDMA system address register */ 39 uint blkattr; /* Block attributes register */ 40 uint cmdarg; /* Command argument register */ 41 uint xfertyp; /* Transfer type register */ 42 uint cmdrsp0; /* Command response 0 register */ 43 uint cmdrsp1; /* Command response 1 register */ 44 uint cmdrsp2; /* Command response 2 register */ 45 uint cmdrsp3; /* Command response 3 register */ 46 uint datport; /* Buffer data port register */ 47 uint prsstat; /* Present state register */ 48 uint proctl; /* Protocol control register */ 49 uint sysctl; /* System Control Register */ 50 uint irqstat; /* Interrupt status register */ 51 uint irqstaten; /* Interrupt status enable register */ 52 uint irqsigen; /* Interrupt signal enable register */ 53 uint autoc12err; /* Auto CMD error status register */ 54 uint hostcapblt; /* Host controller capabilities register */ 55 uint wml; /* Watermark level register */ 56 uint mixctrl; /* For USDHC */ 57 char reserved1[4]; /* reserved */ 58 uint fevt; /* Force event register */ 59 uint admaes; /* ADMA error status register */ 60 uint adsaddr; /* ADMA system address register */ 61 char reserved2[4]; 62 uint dllctrl; 63 uint dllstat; 64 uint clktunectrlstatus; 65 char reserved3[4]; 66 uint strobe_dllctrl; 67 uint strobe_dllstat; 68 char reserved4[72]; 69 uint vendorspec; 70 uint mmcboot; 71 uint vendorspec2; 72 uint tuning_ctrl; /* on i.MX6/7/8 */ 73 char reserved5[44]; 74 uint hostver; /* Host controller version register */ 75 char reserved6[4]; /* reserved */ 76 uint dmaerraddr; /* DMA error address register */ 77 char reserved7[4]; /* reserved */ 78 uint dmaerrattr; /* DMA error attribute register */ 79 char reserved8[4]; /* reserved */ 80 uint hostcapblt2; /* Host controller capabilities register 2 */ 81 char reserved9[8]; /* reserved */ 82 uint tcr; /* Tuning control register */ 83 char reserved10[28]; /* reserved */ 84 uint sddirctl; /* SD direction control register */ 85 char reserved11[712];/* reserved */ 86 uint scr; /* eSDHC control register */ 87 }; 88 89 struct fsl_esdhc_plat { 90 struct mmc_config cfg; 91 struct mmc mmc; 92 }; 93 94 struct esdhc_soc_data { 95 u32 flags; 96 u32 caps; 97 }; 98 99 /** 100 * struct fsl_esdhc_priv 101 * 102 * @esdhc_regs: registers of the sdhc controller 103 * @sdhc_clk: Current clk of the sdhc controller 104 * @bus_width: bus width, 1bit, 4bit or 8bit 105 * @cfg: mmc config 106 * @mmc: mmc 107 * Following is used when Driver Model is enabled for MMC 108 * @dev: pointer for the device 109 * @non_removable: 0: removable; 1: non-removable 110 * @wp_enable: 1: enable checking wp; 0: no check 111 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 112 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h 113 * @caps: controller capabilities 114 * @tuning_step: tuning step setting in tuning_ctrl register 115 * @start_tuning_tap: the start point for tuning in tuning_ctrl register 116 * @strobe_dll_delay_target: settings in strobe_dllctrl 117 * @signal_voltage: indicating the current voltage 118 * @cd_gpio: gpio for card detection 119 * @wp_gpio: gpio for write protection 120 */ 121 struct fsl_esdhc_priv { 122 struct fsl_esdhc *esdhc_regs; 123 unsigned int sdhc_clk; 124 unsigned int clock; 125 unsigned int mode; 126 unsigned int bus_width; 127 #if !CONFIG_IS_ENABLED(BLK) 128 struct mmc *mmc; 129 #endif 130 struct udevice *dev; 131 int non_removable; 132 int wp_enable; 133 int vs18_enable; 134 u32 flags; 135 u32 caps; 136 u32 tuning_step; 137 u32 tuning_start_tap; 138 u32 strobe_dll_delay_target; 139 u32 signal_voltage; 140 #if IS_ENABLED(CONFIG_DM_REGULATOR) 141 struct udevice *vqmmc_dev; 142 struct udevice *vmmc_dev; 143 #endif 144 #ifdef CONFIG_DM_GPIO 145 struct gpio_desc cd_gpio; 146 struct gpio_desc wp_gpio; 147 #endif 148 }; 149 150 /* Return the XFERTYP flags for a given command and data packet */ 151 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 152 { 153 uint xfertyp = 0; 154 155 if (data) { 156 xfertyp |= XFERTYP_DPSEL; 157 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 158 xfertyp |= XFERTYP_DMAEN; 159 #endif 160 if (data->blocks > 1) { 161 xfertyp |= XFERTYP_MSBSEL; 162 xfertyp |= XFERTYP_BCEN; 163 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 164 xfertyp |= XFERTYP_AC12EN; 165 #endif 166 } 167 168 if (data->flags & MMC_DATA_READ) 169 xfertyp |= XFERTYP_DTDSEL; 170 } 171 172 if (cmd->resp_type & MMC_RSP_CRC) 173 xfertyp |= XFERTYP_CCCEN; 174 if (cmd->resp_type & MMC_RSP_OPCODE) 175 xfertyp |= XFERTYP_CICEN; 176 if (cmd->resp_type & MMC_RSP_136) 177 xfertyp |= XFERTYP_RSPTYP_136; 178 else if (cmd->resp_type & MMC_RSP_BUSY) 179 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 180 else if (cmd->resp_type & MMC_RSP_PRESENT) 181 xfertyp |= XFERTYP_RSPTYP_48; 182 183 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 184 xfertyp |= XFERTYP_CMDTYP_ABORT; 185 186 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 187 } 188 189 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 190 /* 191 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 192 */ 193 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 194 struct mmc_data *data) 195 { 196 struct fsl_esdhc *regs = priv->esdhc_regs; 197 uint blocks; 198 char *buffer; 199 uint databuf; 200 uint size; 201 uint irqstat; 202 ulong start; 203 204 if (data->flags & MMC_DATA_READ) { 205 blocks = data->blocks; 206 buffer = data->dest; 207 while (blocks) { 208 start = get_timer(0); 209 size = data->blocksize; 210 irqstat = esdhc_read32(®s->irqstat); 211 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { 212 if (get_timer(start) > PIO_TIMEOUT) { 213 printf("\nData Read Failed in PIO Mode."); 214 return; 215 } 216 } 217 while (size && (!(irqstat & IRQSTAT_TC))) { 218 udelay(100); /* Wait before last byte transfer complete */ 219 irqstat = esdhc_read32(®s->irqstat); 220 databuf = in_le32(®s->datport); 221 *((uint *)buffer) = databuf; 222 buffer += 4; 223 size -= 4; 224 } 225 blocks--; 226 } 227 } else { 228 blocks = data->blocks; 229 buffer = (char *)data->src; 230 while (blocks) { 231 start = get_timer(0); 232 size = data->blocksize; 233 irqstat = esdhc_read32(®s->irqstat); 234 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { 235 if (get_timer(start) > PIO_TIMEOUT) { 236 printf("\nData Write Failed in PIO Mode."); 237 return; 238 } 239 } 240 while (size && (!(irqstat & IRQSTAT_TC))) { 241 udelay(100); /* Wait before last byte transfer complete */ 242 databuf = *((uint *)buffer); 243 buffer += 4; 244 size -= 4; 245 irqstat = esdhc_read32(®s->irqstat); 246 out_le32(®s->datport, databuf); 247 } 248 blocks--; 249 } 250 } 251 } 252 #endif 253 254 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 255 struct mmc_data *data) 256 { 257 int timeout; 258 struct fsl_esdhc *regs = priv->esdhc_regs; 259 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 260 defined(CONFIG_MX8M) 261 dma_addr_t addr; 262 #endif 263 uint wml_value; 264 265 wml_value = data->blocksize/4; 266 267 if (data->flags & MMC_DATA_READ) { 268 if (wml_value > WML_RD_WML_MAX) 269 wml_value = WML_RD_WML_MAX_VAL; 270 271 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 272 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 273 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 274 defined(CONFIG_MX8M) 275 addr = virt_to_phys((void *)(data->dest)); 276 if (upper_32_bits(addr)) 277 printf("Error found for upper 32 bits\n"); 278 else 279 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 280 #else 281 esdhc_write32(®s->dsaddr, (u32)data->dest); 282 #endif 283 #endif 284 } else { 285 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 286 flush_dcache_range((ulong)data->src, 287 (ulong)data->src+data->blocks 288 *data->blocksize); 289 #endif 290 if (wml_value > WML_WR_WML_MAX) 291 wml_value = WML_WR_WML_MAX_VAL; 292 if (priv->wp_enable) { 293 if ((esdhc_read32(®s->prsstat) & 294 PRSSTAT_WPSPL) == 0) { 295 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 296 return -ETIMEDOUT; 297 } 298 } 299 300 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 301 wml_value << 16); 302 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 303 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 304 defined(CONFIG_MX8M) 305 addr = virt_to_phys((void *)(data->src)); 306 if (upper_32_bits(addr)) 307 printf("Error found for upper 32 bits\n"); 308 else 309 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 310 #else 311 esdhc_write32(®s->dsaddr, (u32)data->src); 312 #endif 313 #endif 314 } 315 316 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 317 318 /* Calculate the timeout period for data transactions */ 319 /* 320 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 321 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 322 * So, Number of SD Clock cycles for 0.25sec should be minimum 323 * (SD Clock/sec * 0.25 sec) SD Clock cycles 324 * = (mmc->clock * 1/4) SD Clock cycles 325 * As 1) >= 2) 326 * => (2^(timeout+13)) >= mmc->clock * 1/4 327 * Taking log2 both the sides 328 * => timeout + 13 >= log2(mmc->clock/4) 329 * Rounding up to next power of 2 330 * => timeout + 13 = log2(mmc->clock/4) + 1 331 * => timeout + 13 = fls(mmc->clock/4) 332 * 333 * However, the MMC spec "It is strongly recommended for hosts to 334 * implement more than 500ms timeout value even if the card 335 * indicates the 250ms maximum busy length." Even the previous 336 * value of 300ms is known to be insufficient for some cards. 337 * So, we use 338 * => timeout + 13 = fls(mmc->clock/2) 339 */ 340 timeout = fls(mmc->clock/2); 341 timeout -= 13; 342 343 if (timeout > 14) 344 timeout = 14; 345 346 if (timeout < 0) 347 timeout = 0; 348 349 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 350 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 351 timeout++; 352 #endif 353 354 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 355 timeout = 0xE; 356 #endif 357 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 358 359 return 0; 360 } 361 362 static void check_and_invalidate_dcache_range 363 (struct mmc_cmd *cmd, 364 struct mmc_data *data) { 365 unsigned start = 0; 366 unsigned end = 0; 367 unsigned size = roundup(ARCH_DMA_MINALIGN, 368 data->blocks*data->blocksize); 369 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 370 defined(CONFIG_MX8M) 371 dma_addr_t addr; 372 373 addr = virt_to_phys((void *)(data->dest)); 374 if (upper_32_bits(addr)) 375 printf("Error found for upper 32 bits\n"); 376 else 377 start = lower_32_bits(addr); 378 #else 379 start = (unsigned)data->dest; 380 #endif 381 end = start + size; 382 invalidate_dcache_range(start, end); 383 } 384 385 /* 386 * Sends a command out on the bus. Takes the mmc pointer, 387 * a command pointer, and an optional data pointer. 388 */ 389 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, 390 struct mmc_cmd *cmd, struct mmc_data *data) 391 { 392 int err = 0; 393 uint xfertyp; 394 uint irqstat; 395 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; 396 struct fsl_esdhc *regs = priv->esdhc_regs; 397 398 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 399 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 400 return 0; 401 #endif 402 403 esdhc_write32(®s->irqstat, -1); 404 405 sync(); 406 407 /* Wait for the bus to be idle */ 408 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 409 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 410 ; 411 412 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 413 ; 414 415 /* Wait at least 8 SD clock cycles before the next command */ 416 /* 417 * Note: This is way more than 8 cycles, but 1ms seems to 418 * resolve timing issues with some cards 419 */ 420 udelay(1000); 421 422 /* Set up for a data transfer if we have one */ 423 if (data) { 424 err = esdhc_setup_data(priv, mmc, data); 425 if(err) 426 return err; 427 428 if (data->flags & MMC_DATA_READ) 429 check_and_invalidate_dcache_range(cmd, data); 430 } 431 432 /* Figure out the transfer arguments */ 433 xfertyp = esdhc_xfertyp(cmd, data); 434 435 /* Mask all irqs */ 436 esdhc_write32(®s->irqsigen, 0); 437 438 /* Send the command */ 439 esdhc_write32(®s->cmdarg, cmd->cmdarg); 440 #if defined(CONFIG_FSL_USDHC) 441 esdhc_write32(®s->mixctrl, 442 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 443 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 444 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 445 #else 446 esdhc_write32(®s->xfertyp, xfertyp); 447 #endif 448 449 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 450 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) 451 flags = IRQSTAT_BRR; 452 453 /* Wait for the command to complete */ 454 while (!(esdhc_read32(®s->irqstat) & flags)) 455 ; 456 457 irqstat = esdhc_read32(®s->irqstat); 458 459 if (irqstat & CMD_ERR) { 460 err = -ECOMM; 461 goto out; 462 } 463 464 if (irqstat & IRQSTAT_CTOE) { 465 err = -ETIMEDOUT; 466 goto out; 467 } 468 469 /* Switch voltage to 1.8V if CMD11 succeeded */ 470 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 471 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 472 473 printf("Run CMD11 1.8V switch\n"); 474 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 475 udelay(5000); 476 } 477 478 /* Workaround for ESDHC errata ENGcm03648 */ 479 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 480 int timeout = 6000; 481 482 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 483 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 484 PRSSTAT_DAT0)) { 485 udelay(100); 486 timeout--; 487 } 488 489 if (timeout <= 0) { 490 printf("Timeout waiting for DAT0 to go high!\n"); 491 err = -ETIMEDOUT; 492 goto out; 493 } 494 } 495 496 /* Copy the response to the response buffer */ 497 if (cmd->resp_type & MMC_RSP_136) { 498 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 499 500 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 501 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 502 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 503 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 504 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 505 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 506 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 507 cmd->response[3] = (cmdrsp0 << 8); 508 } else 509 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 510 511 /* Wait until all of the blocks are transferred */ 512 if (data) { 513 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 514 esdhc_pio_read_write(priv, data); 515 #else 516 flags = DATA_COMPLETE; 517 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 518 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) { 519 flags = IRQSTAT_BRR; 520 } 521 522 do { 523 irqstat = esdhc_read32(®s->irqstat); 524 525 if (irqstat & IRQSTAT_DTOE) { 526 err = -ETIMEDOUT; 527 goto out; 528 } 529 530 if (irqstat & DATA_ERR) { 531 err = -ECOMM; 532 goto out; 533 } 534 } while ((irqstat & flags) != flags); 535 536 /* 537 * Need invalidate the dcache here again to avoid any 538 * cache-fill during the DMA operations such as the 539 * speculative pre-fetching etc. 540 */ 541 if (data->flags & MMC_DATA_READ) 542 check_and_invalidate_dcache_range(cmd, data); 543 #endif 544 } 545 546 out: 547 /* Reset CMD and DATA portions on error */ 548 if (err) { 549 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 550 SYSCTL_RSTC); 551 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 552 ; 553 554 if (data) { 555 esdhc_write32(®s->sysctl, 556 esdhc_read32(®s->sysctl) | 557 SYSCTL_RSTD); 558 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 559 ; 560 } 561 562 /* If this was CMD11, then notify that power cycle is needed */ 563 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 564 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 565 } 566 567 esdhc_write32(®s->irqstat, -1); 568 569 return err; 570 } 571 572 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 573 { 574 struct fsl_esdhc *regs = priv->esdhc_regs; 575 int div = 1; 576 #ifdef ARCH_MXC 577 #ifdef CONFIG_MX53 578 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 579 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; 580 #else 581 int pre_div = 1; 582 #endif 583 #else 584 int pre_div = 2; 585 #endif 586 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 587 int sdhc_clk = priv->sdhc_clk; 588 uint clk; 589 590 if (clock < mmc->cfg->f_min) 591 clock = mmc->cfg->f_min; 592 593 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 594 pre_div *= 2; 595 596 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 597 div++; 598 599 pre_div >>= 1; 600 div -= 1; 601 602 clk = (pre_div << 8) | (div << 4); 603 604 #ifdef CONFIG_FSL_USDHC 605 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 606 #else 607 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 608 #endif 609 610 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 611 612 udelay(10000); 613 614 #ifdef CONFIG_FSL_USDHC 615 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 616 #else 617 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 618 #endif 619 620 priv->clock = clock; 621 } 622 623 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 624 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 625 { 626 struct fsl_esdhc *regs = priv->esdhc_regs; 627 u32 value; 628 u32 time_out; 629 630 value = esdhc_read32(®s->sysctl); 631 632 if (enable) 633 value |= SYSCTL_CKEN; 634 else 635 value &= ~SYSCTL_CKEN; 636 637 esdhc_write32(®s->sysctl, value); 638 639 time_out = 20; 640 value = PRSSTAT_SDSTB; 641 while (!(esdhc_read32(®s->prsstat) & value)) { 642 if (time_out == 0) { 643 printf("fsl_esdhc: Internal clock never stabilised.\n"); 644 break; 645 } 646 time_out--; 647 mdelay(1); 648 } 649 } 650 #endif 651 652 #ifdef MMC_SUPPORTS_TUNING 653 static int esdhc_change_pinstate(struct udevice *dev) 654 { 655 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 656 int ret; 657 658 switch (priv->mode) { 659 case UHS_SDR50: 660 case UHS_DDR50: 661 ret = pinctrl_select_state(dev, "state_100mhz"); 662 break; 663 case UHS_SDR104: 664 case MMC_HS_200: 665 ret = pinctrl_select_state(dev, "state_200mhz"); 666 break; 667 default: 668 ret = pinctrl_select_state(dev, "default"); 669 break; 670 } 671 672 if (ret) 673 printf("%s %d error\n", __func__, priv->mode); 674 675 return ret; 676 } 677 678 static void esdhc_reset_tuning(struct mmc *mmc) 679 { 680 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 681 struct fsl_esdhc *regs = priv->esdhc_regs; 682 683 if (priv->flags & ESDHC_FLAG_USDHC) { 684 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 685 esdhc_clrbits32(®s->autoc12err, 686 MIX_CTRL_SMPCLK_SEL | 687 MIX_CTRL_EXE_TUNE); 688 } 689 } 690 } 691 692 static int esdhc_set_timing(struct mmc *mmc) 693 { 694 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 695 struct fsl_esdhc *regs = priv->esdhc_regs; 696 u32 mixctrl; 697 698 mixctrl = readl(®s->mixctrl); 699 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); 700 701 switch (mmc->selected_mode) { 702 case MMC_LEGACY: 703 case SD_LEGACY: 704 esdhc_reset_tuning(mmc); 705 break; 706 case MMC_HS: 707 case MMC_HS_52: 708 case MMC_HS_200: 709 case SD_HS: 710 case UHS_SDR12: 711 case UHS_SDR25: 712 case UHS_SDR50: 713 case UHS_SDR104: 714 writel(mixctrl, ®s->mixctrl); 715 break; 716 case UHS_DDR50: 717 case MMC_DDR_52: 718 mixctrl |= MIX_CTRL_DDREN; 719 writel(mixctrl, ®s->mixctrl); 720 break; 721 default: 722 printf("Not supported %d\n", mmc->selected_mode); 723 return -EINVAL; 724 } 725 726 priv->mode = mmc->selected_mode; 727 728 return esdhc_change_pinstate(mmc->dev); 729 } 730 731 static int esdhc_set_voltage(struct mmc *mmc) 732 { 733 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 734 struct fsl_esdhc *regs = priv->esdhc_regs; 735 int ret; 736 737 priv->signal_voltage = mmc->signal_voltage; 738 switch (mmc->signal_voltage) { 739 case MMC_SIGNAL_VOLTAGE_330: 740 if (priv->vs18_enable) 741 return -EIO; 742 #ifdef CONFIG_DM_REGULATOR 743 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 744 ret = regulator_set_value(priv->vqmmc_dev, 3300000); 745 if (ret) { 746 printf("Setting to 3.3V error"); 747 return -EIO; 748 } 749 /* Wait for 5ms */ 750 mdelay(5); 751 } 752 #endif 753 754 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 755 if (!(esdhc_read32(®s->vendorspec) & 756 ESDHC_VENDORSPEC_VSELECT)) 757 return 0; 758 759 return -EAGAIN; 760 case MMC_SIGNAL_VOLTAGE_180: 761 #ifdef CONFIG_DM_REGULATOR 762 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 763 ret = regulator_set_value(priv->vqmmc_dev, 1800000); 764 if (ret) { 765 printf("Setting to 1.8V error"); 766 return -EIO; 767 } 768 } 769 #endif 770 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 771 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) 772 return 0; 773 774 return -EAGAIN; 775 case MMC_SIGNAL_VOLTAGE_120: 776 return -ENOTSUPP; 777 default: 778 return 0; 779 } 780 } 781 782 static void esdhc_stop_tuning(struct mmc *mmc) 783 { 784 struct mmc_cmd cmd; 785 786 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 787 cmd.cmdarg = 0; 788 cmd.resp_type = MMC_RSP_R1b; 789 790 dm_mmc_send_cmd(mmc->dev, &cmd, NULL); 791 } 792 793 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) 794 { 795 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 796 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 797 struct fsl_esdhc *regs = priv->esdhc_regs; 798 struct mmc *mmc = &plat->mmc; 799 u32 irqstaten = readl(®s->irqstaten); 800 u32 irqsigen = readl(®s->irqsigen); 801 int i, ret = -ETIMEDOUT; 802 u32 val, mixctrl; 803 804 /* clock tuning is not needed for upto 52MHz */ 805 if (mmc->clock <= 52000000) 806 return 0; 807 808 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ 809 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 810 val = readl(®s->autoc12err); 811 mixctrl = readl(®s->mixctrl); 812 val &= ~MIX_CTRL_SMPCLK_SEL; 813 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); 814 815 val |= MIX_CTRL_EXE_TUNE; 816 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; 817 818 writel(val, ®s->autoc12err); 819 writel(mixctrl, ®s->mixctrl); 820 } 821 822 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ 823 mixctrl = readl(®s->mixctrl); 824 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); 825 writel(mixctrl, ®s->mixctrl); 826 827 writel(IRQSTATEN_BRR, ®s->irqstaten); 828 writel(IRQSTATEN_BRR, ®s->irqsigen); 829 830 /* 831 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 832 * of loops reaches 40 times. 833 */ 834 for (i = 0; i < MAX_TUNING_LOOP; i++) { 835 u32 ctrl; 836 837 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { 838 if (mmc->bus_width == 8) 839 writel(0x7080, ®s->blkattr); 840 else if (mmc->bus_width == 4) 841 writel(0x7040, ®s->blkattr); 842 } else { 843 writel(0x7040, ®s->blkattr); 844 } 845 846 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ 847 val = readl(®s->mixctrl); 848 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); 849 writel(val, ®s->mixctrl); 850 851 /* We are using STD tuning, no need to check return value */ 852 mmc_send_tuning(mmc, opcode, NULL); 853 854 ctrl = readl(®s->autoc12err); 855 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && 856 (ctrl & MIX_CTRL_SMPCLK_SEL)) { 857 /* 858 * need to wait some time, make sure sd/mmc fininsh 859 * send out tuning data, otherwise, the sd/mmc can't 860 * response to any command when the card still out 861 * put the tuning data. 862 */ 863 mdelay(1); 864 ret = 0; 865 break; 866 } 867 868 /* Add 1ms delay for SD and eMMC */ 869 mdelay(1); 870 } 871 872 writel(irqstaten, ®s->irqstaten); 873 writel(irqsigen, ®s->irqsigen); 874 875 esdhc_stop_tuning(mmc); 876 877 return ret; 878 } 879 #endif 880 881 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 882 { 883 struct fsl_esdhc *regs = priv->esdhc_regs; 884 int ret __maybe_unused; 885 886 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 887 /* Select to use peripheral clock */ 888 esdhc_clock_control(priv, false); 889 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 890 esdhc_clock_control(priv, true); 891 #endif 892 /* Set the clock speed */ 893 if (priv->clock != mmc->clock) 894 set_sysctl(priv, mmc, mmc->clock); 895 896 #ifdef MMC_SUPPORTS_TUNING 897 if (mmc->clk_disable) { 898 #ifdef CONFIG_FSL_USDHC 899 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 900 #else 901 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 902 #endif 903 } else { 904 #ifdef CONFIG_FSL_USDHC 905 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 906 VENDORSPEC_CKEN); 907 #else 908 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 909 #endif 910 } 911 912 if (priv->mode != mmc->selected_mode) { 913 ret = esdhc_set_timing(mmc); 914 if (ret) { 915 printf("esdhc_set_timing error %d\n", ret); 916 return ret; 917 } 918 } 919 920 if (priv->signal_voltage != mmc->signal_voltage) { 921 ret = esdhc_set_voltage(mmc); 922 if (ret) { 923 printf("esdhc_set_voltage error %d\n", ret); 924 return ret; 925 } 926 } 927 #endif 928 929 /* Set the bus width */ 930 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 931 932 if (mmc->bus_width == 4) 933 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 934 else if (mmc->bus_width == 8) 935 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 936 937 return 0; 938 } 939 940 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 941 { 942 struct fsl_esdhc *regs = priv->esdhc_regs; 943 ulong start; 944 945 /* Reset the entire host controller */ 946 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 947 948 /* Wait until the controller is available */ 949 start = get_timer(0); 950 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 951 if (get_timer(start) > 1000) 952 return -ETIMEDOUT; 953 } 954 955 #if defined(CONFIG_FSL_USDHC) 956 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 957 esdhc_write32(®s->mmcboot, 0x0); 958 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 959 esdhc_write32(®s->mixctrl, 0x0); 960 esdhc_write32(®s->clktunectrlstatus, 0x0); 961 962 /* Put VEND_SPEC to default value */ 963 if (priv->vs18_enable) 964 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | 965 ESDHC_VENDORSPEC_VSELECT)); 966 else 967 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 968 969 /* Disable DLL_CTRL delay line */ 970 esdhc_write32(®s->dllctrl, 0x0); 971 #endif 972 973 #ifndef ARCH_MXC 974 /* Enable cache snooping */ 975 esdhc_write32(®s->scr, 0x00000040); 976 #endif 977 978 #ifndef CONFIG_FSL_USDHC 979 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 980 #else 981 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 982 #endif 983 984 /* Set the initial clock speed */ 985 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); 986 987 /* Disable the BRR and BWR bits in IRQSTAT */ 988 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 989 990 /* Put the PROCTL reg back to the default */ 991 esdhc_write32(®s->proctl, PROCTL_INIT); 992 993 /* Set timout to the maximum value */ 994 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 995 996 return 0; 997 } 998 999 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) 1000 { 1001 struct fsl_esdhc *regs = priv->esdhc_regs; 1002 int timeout = 1000; 1003 1004 #ifdef CONFIG_ESDHC_DETECT_QUIRK 1005 if (CONFIG_ESDHC_DETECT_QUIRK) 1006 return 1; 1007 #endif 1008 1009 #if CONFIG_IS_ENABLED(DM_MMC) 1010 if (priv->non_removable) 1011 return 1; 1012 #ifdef CONFIG_DM_GPIO 1013 if (dm_gpio_is_valid(&priv->cd_gpio)) 1014 return dm_gpio_get_value(&priv->cd_gpio); 1015 #endif 1016 #endif 1017 1018 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 1019 udelay(1000); 1020 1021 return timeout > 0; 1022 } 1023 1024 static int esdhc_reset(struct fsl_esdhc *regs) 1025 { 1026 ulong start; 1027 1028 /* reset the controller */ 1029 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 1030 1031 /* hardware clears the bit when it is done */ 1032 start = get_timer(0); 1033 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 1034 if (get_timer(start) > 100) { 1035 printf("MMC/SD: Reset never completed.\n"); 1036 return -ETIMEDOUT; 1037 } 1038 } 1039 1040 return 0; 1041 } 1042 1043 #if !CONFIG_IS_ENABLED(DM_MMC) 1044 static int esdhc_getcd(struct mmc *mmc) 1045 { 1046 struct fsl_esdhc_priv *priv = mmc->priv; 1047 1048 return esdhc_getcd_common(priv); 1049 } 1050 1051 static int esdhc_init(struct mmc *mmc) 1052 { 1053 struct fsl_esdhc_priv *priv = mmc->priv; 1054 1055 return esdhc_init_common(priv, mmc); 1056 } 1057 1058 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 1059 struct mmc_data *data) 1060 { 1061 struct fsl_esdhc_priv *priv = mmc->priv; 1062 1063 return esdhc_send_cmd_common(priv, mmc, cmd, data); 1064 } 1065 1066 static int esdhc_set_ios(struct mmc *mmc) 1067 { 1068 struct fsl_esdhc_priv *priv = mmc->priv; 1069 1070 return esdhc_set_ios_common(priv, mmc); 1071 } 1072 1073 static const struct mmc_ops esdhc_ops = { 1074 .getcd = esdhc_getcd, 1075 .init = esdhc_init, 1076 .send_cmd = esdhc_send_cmd, 1077 .set_ios = esdhc_set_ios, 1078 }; 1079 #endif 1080 1081 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, 1082 struct fsl_esdhc_plat *plat) 1083 { 1084 struct mmc_config *cfg; 1085 struct fsl_esdhc *regs; 1086 u32 caps, voltage_caps; 1087 int ret; 1088 1089 if (!priv) 1090 return -EINVAL; 1091 1092 regs = priv->esdhc_regs; 1093 1094 /* First reset the eSDHC controller */ 1095 ret = esdhc_reset(regs); 1096 if (ret) 1097 return ret; 1098 1099 #ifndef CONFIG_FSL_USDHC 1100 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 1101 | SYSCTL_IPGEN | SYSCTL_CKEN); 1102 /* Clearing tuning bits in case ROM has set it already */ 1103 esdhc_write32(®s->mixctrl, 0); 1104 esdhc_write32(®s->autoc12err, 0); 1105 esdhc_write32(®s->clktunectrlstatus, 0); 1106 #else 1107 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 1108 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 1109 #endif 1110 1111 if (priv->vs18_enable) 1112 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 1113 1114 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 1115 cfg = &plat->cfg; 1116 #ifndef CONFIG_DM_MMC 1117 memset(cfg, '\0', sizeof(*cfg)); 1118 #endif 1119 1120 voltage_caps = 0; 1121 caps = esdhc_read32(®s->hostcapblt); 1122 1123 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 1124 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 1125 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 1126 #endif 1127 1128 /* T4240 host controller capabilities register should have VS33 bit */ 1129 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 1130 caps = caps | ESDHC_HOSTCAPBLT_VS33; 1131 #endif 1132 1133 if (caps & ESDHC_HOSTCAPBLT_VS18) 1134 voltage_caps |= MMC_VDD_165_195; 1135 if (caps & ESDHC_HOSTCAPBLT_VS30) 1136 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 1137 if (caps & ESDHC_HOSTCAPBLT_VS33) 1138 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 1139 1140 cfg->name = "FSL_SDHC"; 1141 #if !CONFIG_IS_ENABLED(DM_MMC) 1142 cfg->ops = &esdhc_ops; 1143 #endif 1144 #ifdef CONFIG_SYS_SD_VOLTAGE 1145 cfg->voltages = CONFIG_SYS_SD_VOLTAGE; 1146 #else 1147 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 1148 #endif 1149 if ((cfg->voltages & voltage_caps) == 0) { 1150 printf("voltage not supported by controller\n"); 1151 return -1; 1152 } 1153 1154 if (priv->bus_width == 8) 1155 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1156 else if (priv->bus_width == 4) 1157 cfg->host_caps = MMC_MODE_4BIT; 1158 1159 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1160 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 1161 cfg->host_caps |= MMC_MODE_DDR_52MHz; 1162 #endif 1163 1164 if (priv->bus_width > 0) { 1165 if (priv->bus_width < 8) 1166 cfg->host_caps &= ~MMC_MODE_8BIT; 1167 if (priv->bus_width < 4) 1168 cfg->host_caps &= ~MMC_MODE_4BIT; 1169 } 1170 1171 if (caps & ESDHC_HOSTCAPBLT_HSS) 1172 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1173 1174 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 1175 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 1176 cfg->host_caps &= ~MMC_MODE_8BIT; 1177 #endif 1178 1179 cfg->host_caps |= priv->caps; 1180 1181 cfg->f_min = 400000; 1182 cfg->f_max = min(priv->sdhc_clk, (u32)200000000); 1183 1184 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1185 1186 writel(0, ®s->dllctrl); 1187 if (priv->flags & ESDHC_FLAG_USDHC) { 1188 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 1189 u32 val = readl(®s->tuning_ctrl); 1190 1191 val |= ESDHC_STD_TUNING_EN; 1192 val &= ~ESDHC_TUNING_START_TAP_MASK; 1193 val |= priv->tuning_start_tap; 1194 val &= ~ESDHC_TUNING_STEP_MASK; 1195 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT; 1196 writel(val, ®s->tuning_ctrl); 1197 } 1198 } 1199 1200 return 0; 1201 } 1202 1203 #if !CONFIG_IS_ENABLED(DM_MMC) 1204 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 1205 struct fsl_esdhc_priv *priv) 1206 { 1207 if (!cfg || !priv) 1208 return -EINVAL; 1209 1210 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 1211 priv->bus_width = cfg->max_bus_width; 1212 priv->sdhc_clk = cfg->sdhc_clk; 1213 priv->wp_enable = cfg->wp_enable; 1214 priv->vs18_enable = cfg->vs18_enable; 1215 1216 return 0; 1217 }; 1218 1219 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 1220 { 1221 struct fsl_esdhc_plat *plat; 1222 struct fsl_esdhc_priv *priv; 1223 struct mmc *mmc; 1224 int ret; 1225 1226 if (!cfg) 1227 return -EINVAL; 1228 1229 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 1230 if (!priv) 1231 return -ENOMEM; 1232 plat = calloc(sizeof(struct fsl_esdhc_plat), 1); 1233 if (!plat) { 1234 free(priv); 1235 return -ENOMEM; 1236 } 1237 1238 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 1239 if (ret) { 1240 debug("%s xlate failure\n", __func__); 1241 free(plat); 1242 free(priv); 1243 return ret; 1244 } 1245 1246 ret = fsl_esdhc_init(priv, plat); 1247 if (ret) { 1248 debug("%s init failure\n", __func__); 1249 free(plat); 1250 free(priv); 1251 return ret; 1252 } 1253 1254 mmc = mmc_create(&plat->cfg, priv); 1255 if (!mmc) 1256 return -EIO; 1257 1258 priv->mmc = mmc; 1259 1260 return 0; 1261 } 1262 1263 int fsl_esdhc_mmc_init(bd_t *bis) 1264 { 1265 struct fsl_esdhc_cfg *cfg; 1266 1267 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 1268 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 1269 cfg->sdhc_clk = gd->arch.sdhc_clk; 1270 return fsl_esdhc_initialize(bis, cfg); 1271 } 1272 #endif 1273 1274 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1275 void mmc_adapter_card_type_ident(void) 1276 { 1277 u8 card_id; 1278 u8 value; 1279 1280 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 1281 gd->arch.sdhc_adapter = card_id; 1282 1283 switch (card_id) { 1284 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 1285 value = QIXIS_READ(brdcfg[5]); 1286 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 1287 QIXIS_WRITE(brdcfg[5], value); 1288 break; 1289 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 1290 value = QIXIS_READ(pwr_ctl[1]); 1291 value |= QIXIS_EVDD_BY_SDHC_VS; 1292 QIXIS_WRITE(pwr_ctl[1], value); 1293 break; 1294 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 1295 value = QIXIS_READ(brdcfg[5]); 1296 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 1297 QIXIS_WRITE(brdcfg[5], value); 1298 break; 1299 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 1300 break; 1301 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 1302 break; 1303 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 1304 break; 1305 case QIXIS_ESDHC_NO_ADAPTER: 1306 break; 1307 default: 1308 break; 1309 } 1310 } 1311 #endif 1312 1313 #ifdef CONFIG_OF_LIBFDT 1314 __weak int esdhc_status_fixup(void *blob, const char *compat) 1315 { 1316 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 1317 if (!hwconfig("esdhc")) { 1318 do_fixup_by_compat(blob, compat, "status", "disabled", 1319 sizeof("disabled"), 1); 1320 return 1; 1321 } 1322 #endif 1323 return 0; 1324 } 1325 1326 void fdt_fixup_esdhc(void *blob, bd_t *bd) 1327 { 1328 const char *compat = "fsl,esdhc"; 1329 1330 if (esdhc_status_fixup(blob, compat)) 1331 return; 1332 1333 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 1334 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 1335 gd->arch.sdhc_clk, 1); 1336 #else 1337 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 1338 gd->arch.sdhc_clk, 1); 1339 #endif 1340 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1341 do_fixup_by_compat_u32(blob, compat, "adapter-type", 1342 (u32)(gd->arch.sdhc_adapter), 1); 1343 #endif 1344 } 1345 #endif 1346 1347 #if CONFIG_IS_ENABLED(DM_MMC) 1348 #include <asm/arch/clock.h> 1349 __weak void init_clk_usdhc(u32 index) 1350 { 1351 } 1352 1353 static int fsl_esdhc_probe(struct udevice *dev) 1354 { 1355 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1356 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1357 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1358 const void *fdt = gd->fdt_blob; 1359 int node = dev_of_offset(dev); 1360 struct esdhc_soc_data *data = 1361 (struct esdhc_soc_data *)dev_get_driver_data(dev); 1362 #ifdef CONFIG_DM_REGULATOR 1363 struct udevice *vqmmc_dev; 1364 #endif 1365 fdt_addr_t addr; 1366 unsigned int val; 1367 struct mmc *mmc; 1368 int ret; 1369 1370 addr = dev_read_addr(dev); 1371 if (addr == FDT_ADDR_T_NONE) 1372 return -EINVAL; 1373 1374 priv->esdhc_regs = (struct fsl_esdhc *)addr; 1375 priv->dev = dev; 1376 priv->mode = -1; 1377 if (data) { 1378 priv->flags = data->flags; 1379 priv->caps = data->caps; 1380 } 1381 1382 val = dev_read_u32_default(dev, "bus-width", -1); 1383 if (val == 8) 1384 priv->bus_width = 8; 1385 else if (val == 4) 1386 priv->bus_width = 4; 1387 else 1388 priv->bus_width = 1; 1389 1390 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1); 1391 priv->tuning_step = val; 1392 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", 1393 ESDHC_TUNING_START_TAP_DEFAULT); 1394 priv->tuning_start_tap = val; 1395 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", 1396 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); 1397 priv->strobe_dll_delay_target = val; 1398 1399 if (dev_read_bool(dev, "non-removable")) { 1400 priv->non_removable = 1; 1401 } else { 1402 priv->non_removable = 0; 1403 #ifdef CONFIG_DM_GPIO 1404 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 1405 GPIOD_IS_IN); 1406 #endif 1407 } 1408 1409 priv->wp_enable = 1; 1410 1411 #ifdef CONFIG_DM_GPIO 1412 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 1413 GPIOD_IS_IN); 1414 if (ret) 1415 priv->wp_enable = 0; 1416 #endif 1417 1418 priv->vs18_enable = 0; 1419 1420 #ifdef CONFIG_DM_REGULATOR 1421 /* 1422 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1423 * otherwise, emmc will work abnormally. 1424 */ 1425 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1426 if (ret) { 1427 dev_dbg(dev, "no vqmmc-supply\n"); 1428 } else { 1429 ret = regulator_set_enable(vqmmc_dev, true); 1430 if (ret) { 1431 dev_err(dev, "fail to enable vqmmc-supply\n"); 1432 return ret; 1433 } 1434 1435 if (regulator_get_value(vqmmc_dev) == 1800000) 1436 priv->vs18_enable = 1; 1437 } 1438 #endif 1439 1440 if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) 1441 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200); 1442 1443 /* 1444 * TODO: 1445 * Because lack of clk driver, if SDHC clk is not enabled, 1446 * need to enable it first before this driver is invoked. 1447 * 1448 * we use MXC_ESDHC_CLK to get clk freq. 1449 * If one would like to make this function work, 1450 * the aliases should be provided in dts as this: 1451 * 1452 * aliases { 1453 * mmc0 = &usdhc1; 1454 * mmc1 = &usdhc2; 1455 * mmc2 = &usdhc3; 1456 * mmc3 = &usdhc4; 1457 * }; 1458 * Then if your board only supports mmc2 and mmc3, but we can 1459 * correctly get the seq as 2 and 3, then let mxc_get_clock 1460 * work as expected. 1461 */ 1462 1463 init_clk_usdhc(dev->seq); 1464 1465 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1466 if (priv->sdhc_clk <= 0) { 1467 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1468 return -EINVAL; 1469 } 1470 1471 ret = fsl_esdhc_init(priv, plat); 1472 if (ret) { 1473 dev_err(dev, "fsl_esdhc_init failure\n"); 1474 return ret; 1475 } 1476 1477 mmc = &plat->mmc; 1478 mmc->cfg = &plat->cfg; 1479 mmc->dev = dev; 1480 upriv->mmc = mmc; 1481 1482 return esdhc_init_common(priv, mmc); 1483 } 1484 1485 #if CONFIG_IS_ENABLED(DM_MMC) 1486 static int fsl_esdhc_get_cd(struct udevice *dev) 1487 { 1488 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1489 1490 return true; 1491 return esdhc_getcd_common(priv); 1492 } 1493 1494 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 1495 struct mmc_data *data) 1496 { 1497 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1498 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1499 1500 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); 1501 } 1502 1503 static int fsl_esdhc_set_ios(struct udevice *dev) 1504 { 1505 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1506 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1507 1508 return esdhc_set_ios_common(priv, &plat->mmc); 1509 } 1510 1511 static const struct dm_mmc_ops fsl_esdhc_ops = { 1512 .get_cd = fsl_esdhc_get_cd, 1513 .send_cmd = fsl_esdhc_send_cmd, 1514 .set_ios = fsl_esdhc_set_ios, 1515 #ifdef MMC_SUPPORTS_TUNING 1516 .execute_tuning = fsl_esdhc_execute_tuning, 1517 #endif 1518 }; 1519 #endif 1520 1521 static struct esdhc_soc_data usdhc_imx7d_data = { 1522 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1523 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 1524 | ESDHC_FLAG_HS400, 1525 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | 1526 MMC_MODE_HS_52MHz | MMC_MODE_HS, 1527 }; 1528 1529 static const struct udevice_id fsl_esdhc_ids[] = { 1530 { .compatible = "fsl,imx6ul-usdhc", }, 1531 { .compatible = "fsl,imx6sx-usdhc", }, 1532 { .compatible = "fsl,imx6sl-usdhc", }, 1533 { .compatible = "fsl,imx6q-usdhc", }, 1534 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, 1535 { .compatible = "fsl,imx7ulp-usdhc", }, 1536 { .compatible = "fsl,esdhc", }, 1537 { /* sentinel */ } 1538 }; 1539 1540 #if CONFIG_IS_ENABLED(BLK) 1541 static int fsl_esdhc_bind(struct udevice *dev) 1542 { 1543 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1544 1545 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1546 } 1547 #endif 1548 1549 U_BOOT_DRIVER(fsl_esdhc) = { 1550 .name = "fsl-esdhc-mmc", 1551 .id = UCLASS_MMC, 1552 .of_match = fsl_esdhc_ids, 1553 .ops = &fsl_esdhc_ops, 1554 #if CONFIG_IS_ENABLED(BLK) 1555 .bind = fsl_esdhc_bind, 1556 #endif 1557 .probe = fsl_esdhc_probe, 1558 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), 1559 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1560 }; 1561 #endif 1562