1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 27 IRQSTATEN_CINT | \ 28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 31 IRQSTATEN_DINT) 32 33 struct fsl_esdhc { 34 uint dsaddr; /* SDMA system address register */ 35 uint blkattr; /* Block attributes register */ 36 uint cmdarg; /* Command argument register */ 37 uint xfertyp; /* Transfer type register */ 38 uint cmdrsp0; /* Command response 0 register */ 39 uint cmdrsp1; /* Command response 1 register */ 40 uint cmdrsp2; /* Command response 2 register */ 41 uint cmdrsp3; /* Command response 3 register */ 42 uint datport; /* Buffer data port register */ 43 uint prsstat; /* Present state register */ 44 uint proctl; /* Protocol control register */ 45 uint sysctl; /* System Control Register */ 46 uint irqstat; /* Interrupt status register */ 47 uint irqstaten; /* Interrupt status enable register */ 48 uint irqsigen; /* Interrupt signal enable register */ 49 uint autoc12err; /* Auto CMD error status register */ 50 uint hostcapblt; /* Host controller capabilities register */ 51 uint wml; /* Watermark level register */ 52 uint mixctrl; /* For USDHC */ 53 char reserved1[4]; /* reserved */ 54 uint fevt; /* Force event register */ 55 uint admaes; /* ADMA error status register */ 56 uint adsaddr; /* ADMA system address register */ 57 char reserved2[100]; /* reserved */ 58 uint vendorspec; /* Vendor Specific register */ 59 char reserved3[56]; /* reserved */ 60 uint hostver; /* Host controller version register */ 61 char reserved4[4]; /* reserved */ 62 uint dmaerraddr; /* DMA error address register */ 63 char reserved5[4]; /* reserved */ 64 uint dmaerrattr; /* DMA error attribute register */ 65 char reserved6[4]; /* reserved */ 66 uint hostcapblt2; /* Host controller capabilities register 2 */ 67 char reserved7[8]; /* reserved */ 68 uint tcr; /* Tuning control register */ 69 char reserved8[28]; /* reserved */ 70 uint sddirctl; /* SD direction control register */ 71 char reserved9[712]; /* reserved */ 72 uint scr; /* eSDHC control register */ 73 }; 74 75 /* Return the XFERTYP flags for a given command and data packet */ 76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 77 { 78 uint xfertyp = 0; 79 80 if (data) { 81 xfertyp |= XFERTYP_DPSEL; 82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 83 xfertyp |= XFERTYP_DMAEN; 84 #endif 85 if (data->blocks > 1) { 86 xfertyp |= XFERTYP_MSBSEL; 87 xfertyp |= XFERTYP_BCEN; 88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 89 xfertyp |= XFERTYP_AC12EN; 90 #endif 91 } 92 93 if (data->flags & MMC_DATA_READ) 94 xfertyp |= XFERTYP_DTDSEL; 95 } 96 97 if (cmd->resp_type & MMC_RSP_CRC) 98 xfertyp |= XFERTYP_CCCEN; 99 if (cmd->resp_type & MMC_RSP_OPCODE) 100 xfertyp |= XFERTYP_CICEN; 101 if (cmd->resp_type & MMC_RSP_136) 102 xfertyp |= XFERTYP_RSPTYP_136; 103 else if (cmd->resp_type & MMC_RSP_BUSY) 104 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 105 else if (cmd->resp_type & MMC_RSP_PRESENT) 106 xfertyp |= XFERTYP_RSPTYP_48; 107 108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ 109 defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \ 110 defined(CONFIG_PPC_T4160) 111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 112 xfertyp |= XFERTYP_CMDTYP_ABORT; 113 #endif 114 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 115 } 116 117 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 118 /* 119 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 120 */ 121 static void 122 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 123 { 124 struct fsl_esdhc_cfg *cfg = mmc->priv; 125 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 126 uint blocks; 127 char *buffer; 128 uint databuf; 129 uint size; 130 uint irqstat; 131 uint timeout; 132 133 if (data->flags & MMC_DATA_READ) { 134 blocks = data->blocks; 135 buffer = data->dest; 136 while (blocks) { 137 timeout = PIO_TIMEOUT; 138 size = data->blocksize; 139 irqstat = esdhc_read32(®s->irqstat); 140 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 141 && --timeout); 142 if (timeout <= 0) { 143 printf("\nData Read Failed in PIO Mode."); 144 return; 145 } 146 while (size && (!(irqstat & IRQSTAT_TC))) { 147 udelay(100); /* Wait before last byte transfer complete */ 148 irqstat = esdhc_read32(®s->irqstat); 149 databuf = in_le32(®s->datport); 150 *((uint *)buffer) = databuf; 151 buffer += 4; 152 size -= 4; 153 } 154 blocks--; 155 } 156 } else { 157 blocks = data->blocks; 158 buffer = (char *)data->src; 159 while (blocks) { 160 timeout = PIO_TIMEOUT; 161 size = data->blocksize; 162 irqstat = esdhc_read32(®s->irqstat); 163 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 164 && --timeout); 165 if (timeout <= 0) { 166 printf("\nData Write Failed in PIO Mode."); 167 return; 168 } 169 while (size && (!(irqstat & IRQSTAT_TC))) { 170 udelay(100); /* Wait before last byte transfer complete */ 171 databuf = *((uint *)buffer); 172 buffer += 4; 173 size -= 4; 174 irqstat = esdhc_read32(®s->irqstat); 175 out_le32(®s->datport, databuf); 176 } 177 blocks--; 178 } 179 } 180 } 181 #endif 182 183 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 184 { 185 int timeout; 186 struct fsl_esdhc_cfg *cfg = mmc->priv; 187 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 188 #ifdef CONFIG_FSL_LAYERSCAPE 189 dma_addr_t addr; 190 #endif 191 uint wml_value; 192 193 wml_value = data->blocksize/4; 194 195 if (data->flags & MMC_DATA_READ) { 196 if (wml_value > WML_RD_WML_MAX) 197 wml_value = WML_RD_WML_MAX_VAL; 198 199 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 200 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 201 #ifdef CONFIG_FSL_LAYERSCAPE 202 addr = virt_to_phys((void *)(data->dest)); 203 if (upper_32_bits(addr)) 204 printf("Error found for upper 32 bits\n"); 205 else 206 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 207 #else 208 esdhc_write32(®s->dsaddr, (u32)data->dest); 209 #endif 210 #endif 211 } else { 212 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 213 flush_dcache_range((ulong)data->src, 214 (ulong)data->src+data->blocks 215 *data->blocksize); 216 #endif 217 if (wml_value > WML_WR_WML_MAX) 218 wml_value = WML_WR_WML_MAX_VAL; 219 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 220 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 221 return TIMEOUT; 222 } 223 224 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 225 wml_value << 16); 226 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 227 #ifdef CONFIG_FSL_LAYERSCAPE 228 addr = virt_to_phys((void *)(data->src)); 229 if (upper_32_bits(addr)) 230 printf("Error found for upper 32 bits\n"); 231 else 232 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 233 #else 234 esdhc_write32(®s->dsaddr, (u32)data->src); 235 #endif 236 #endif 237 } 238 239 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 240 241 /* Calculate the timeout period for data transactions */ 242 /* 243 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 244 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 245 * So, Number of SD Clock cycles for 0.25sec should be minimum 246 * (SD Clock/sec * 0.25 sec) SD Clock cycles 247 * = (mmc->clock * 1/4) SD Clock cycles 248 * As 1) >= 2) 249 * => (2^(timeout+13)) >= mmc->clock * 1/4 250 * Taking log2 both the sides 251 * => timeout + 13 >= log2(mmc->clock/4) 252 * Rounding up to next power of 2 253 * => timeout + 13 = log2(mmc->clock/4) + 1 254 * => timeout + 13 = fls(mmc->clock/4) 255 */ 256 timeout = fls(mmc->clock/4); 257 timeout -= 13; 258 259 if (timeout > 14) 260 timeout = 14; 261 262 if (timeout < 0) 263 timeout = 0; 264 265 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 266 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 267 timeout++; 268 #endif 269 270 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 271 timeout = 0xE; 272 #endif 273 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 274 275 return 0; 276 } 277 278 static void check_and_invalidate_dcache_range 279 (struct mmc_cmd *cmd, 280 struct mmc_data *data) { 281 #ifdef CONFIG_FSL_LAYERSCAPE 282 unsigned start = 0; 283 #else 284 unsigned start = (unsigned)data->dest ; 285 #endif 286 unsigned size = roundup(ARCH_DMA_MINALIGN, 287 data->blocks*data->blocksize); 288 unsigned end = start+size ; 289 #ifdef CONFIG_FSL_LAYERSCAPE 290 dma_addr_t addr; 291 292 addr = virt_to_phys((void *)(data->dest)); 293 if (upper_32_bits(addr)) 294 printf("Error found for upper 32 bits\n"); 295 else 296 start = lower_32_bits(addr); 297 #endif 298 invalidate_dcache_range(start, end); 299 } 300 301 /* 302 * Sends a command out on the bus. Takes the mmc pointer, 303 * a command pointer, and an optional data pointer. 304 */ 305 static int 306 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 307 { 308 int err = 0; 309 uint xfertyp; 310 uint irqstat; 311 struct fsl_esdhc_cfg *cfg = mmc->priv; 312 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 313 314 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 315 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 316 return 0; 317 #endif 318 319 esdhc_write32(®s->irqstat, -1); 320 321 sync(); 322 323 /* Wait for the bus to be idle */ 324 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 325 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 326 ; 327 328 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 329 ; 330 331 /* Wait at least 8 SD clock cycles before the next command */ 332 /* 333 * Note: This is way more than 8 cycles, but 1ms seems to 334 * resolve timing issues with some cards 335 */ 336 udelay(1000); 337 338 /* Set up for a data transfer if we have one */ 339 if (data) { 340 err = esdhc_setup_data(mmc, data); 341 if(err) 342 return err; 343 344 if (data->flags & MMC_DATA_READ) 345 check_and_invalidate_dcache_range(cmd, data); 346 } 347 348 /* Figure out the transfer arguments */ 349 xfertyp = esdhc_xfertyp(cmd, data); 350 351 /* Mask all irqs */ 352 esdhc_write32(®s->irqsigen, 0); 353 354 /* Send the command */ 355 esdhc_write32(®s->cmdarg, cmd->cmdarg); 356 #if defined(CONFIG_FSL_USDHC) 357 esdhc_write32(®s->mixctrl, 358 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 359 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 360 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 361 #else 362 esdhc_write32(®s->xfertyp, xfertyp); 363 #endif 364 365 /* Wait for the command to complete */ 366 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 367 ; 368 369 irqstat = esdhc_read32(®s->irqstat); 370 371 if (irqstat & CMD_ERR) { 372 err = COMM_ERR; 373 goto out; 374 } 375 376 if (irqstat & IRQSTAT_CTOE) { 377 err = TIMEOUT; 378 goto out; 379 } 380 381 /* Switch voltage to 1.8V if CMD11 succeeded */ 382 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 383 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 384 385 printf("Run CMD11 1.8V switch\n"); 386 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 387 udelay(5000); 388 } 389 390 /* Workaround for ESDHC errata ENGcm03648 */ 391 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 392 int timeout = 6000; 393 394 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 395 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 396 PRSSTAT_DAT0)) { 397 udelay(100); 398 timeout--; 399 } 400 401 if (timeout <= 0) { 402 printf("Timeout waiting for DAT0 to go high!\n"); 403 err = TIMEOUT; 404 goto out; 405 } 406 } 407 408 /* Copy the response to the response buffer */ 409 if (cmd->resp_type & MMC_RSP_136) { 410 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 411 412 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 413 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 414 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 415 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 416 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 417 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 418 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 419 cmd->response[3] = (cmdrsp0 << 8); 420 } else 421 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 422 423 /* Wait until all of the blocks are transferred */ 424 if (data) { 425 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 426 esdhc_pio_read_write(mmc, data); 427 #else 428 do { 429 irqstat = esdhc_read32(®s->irqstat); 430 431 if (irqstat & IRQSTAT_DTOE) { 432 err = TIMEOUT; 433 goto out; 434 } 435 436 if (irqstat & DATA_ERR) { 437 err = COMM_ERR; 438 goto out; 439 } 440 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 441 442 /* 443 * Need invalidate the dcache here again to avoid any 444 * cache-fill during the DMA operations such as the 445 * speculative pre-fetching etc. 446 */ 447 if (data->flags & MMC_DATA_READ) 448 check_and_invalidate_dcache_range(cmd, data); 449 #endif 450 } 451 452 out: 453 /* Reset CMD and DATA portions on error */ 454 if (err) { 455 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 456 SYSCTL_RSTC); 457 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 458 ; 459 460 if (data) { 461 esdhc_write32(®s->sysctl, 462 esdhc_read32(®s->sysctl) | 463 SYSCTL_RSTD); 464 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 465 ; 466 } 467 468 /* If this was CMD11, then notify that power cycle is needed */ 469 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 470 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 471 } 472 473 esdhc_write32(®s->irqstat, -1); 474 475 return err; 476 } 477 478 static void set_sysctl(struct mmc *mmc, uint clock) 479 { 480 int div, pre_div; 481 struct fsl_esdhc_cfg *cfg = mmc->priv; 482 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 483 int sdhc_clk = cfg->sdhc_clk; 484 uint clk; 485 486 if (clock < mmc->cfg->f_min) 487 clock = mmc->cfg->f_min; 488 489 if (sdhc_clk / 16 > clock) { 490 for (pre_div = 2; pre_div < 256; pre_div *= 2) 491 if ((sdhc_clk / pre_div) <= (clock * 16)) 492 break; 493 } else 494 pre_div = 2; 495 496 for (div = 1; div <= 16; div++) 497 if ((sdhc_clk / (div * pre_div)) <= clock) 498 break; 499 500 pre_div >>= mmc->ddr_mode ? 2 : 1; 501 div -= 1; 502 503 clk = (pre_div << 8) | (div << 4); 504 505 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 506 507 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 508 509 udelay(10000); 510 511 clk = SYSCTL_PEREN | SYSCTL_CKEN; 512 513 esdhc_setbits32(®s->sysctl, clk); 514 } 515 516 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 517 static void esdhc_clock_control(struct mmc *mmc, bool enable) 518 { 519 struct fsl_esdhc_cfg *cfg = mmc->priv; 520 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 521 u32 value; 522 u32 time_out; 523 524 value = esdhc_read32(®s->sysctl); 525 526 if (enable) 527 value |= SYSCTL_CKEN; 528 else 529 value &= ~SYSCTL_CKEN; 530 531 esdhc_write32(®s->sysctl, value); 532 533 time_out = 20; 534 value = PRSSTAT_SDSTB; 535 while (!(esdhc_read32(®s->prsstat) & value)) { 536 if (time_out == 0) { 537 printf("fsl_esdhc: Internal clock never stabilised.\n"); 538 break; 539 } 540 time_out--; 541 mdelay(1); 542 } 543 } 544 #endif 545 546 static void esdhc_set_ios(struct mmc *mmc) 547 { 548 struct fsl_esdhc_cfg *cfg = mmc->priv; 549 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 550 551 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 552 /* Select to use peripheral clock */ 553 esdhc_clock_control(mmc, false); 554 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 555 esdhc_clock_control(mmc, true); 556 #endif 557 /* Set the clock speed */ 558 set_sysctl(mmc, mmc->clock); 559 560 /* Set the bus width */ 561 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 562 563 if (mmc->bus_width == 4) 564 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 565 else if (mmc->bus_width == 8) 566 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 567 568 } 569 570 static int esdhc_init(struct mmc *mmc) 571 { 572 struct fsl_esdhc_cfg *cfg = mmc->priv; 573 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 574 int timeout = 1000; 575 576 /* Reset the entire host controller */ 577 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 578 579 /* Wait until the controller is available */ 580 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 581 udelay(1000); 582 583 #ifndef ARCH_MXC 584 /* Enable cache snooping */ 585 esdhc_write32(®s->scr, 0x00000040); 586 #endif 587 588 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 589 590 /* Set the initial clock speed */ 591 mmc_set_clock(mmc, 400000); 592 593 /* Disable the BRR and BWR bits in IRQSTAT */ 594 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 595 596 /* Put the PROCTL reg back to the default */ 597 esdhc_write32(®s->proctl, PROCTL_INIT); 598 599 /* Set timout to the maximum value */ 600 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 601 602 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 603 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 604 #endif 605 606 return 0; 607 } 608 609 static int esdhc_getcd(struct mmc *mmc) 610 { 611 struct fsl_esdhc_cfg *cfg = mmc->priv; 612 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 613 int timeout = 1000; 614 615 #ifdef CONFIG_ESDHC_DETECT_QUIRK 616 if (CONFIG_ESDHC_DETECT_QUIRK) 617 return 1; 618 #endif 619 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 620 udelay(1000); 621 622 return timeout > 0; 623 } 624 625 static void esdhc_reset(struct fsl_esdhc *regs) 626 { 627 unsigned long timeout = 100; /* wait max 100 ms */ 628 629 /* reset the controller */ 630 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 631 632 /* hardware clears the bit when it is done */ 633 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 634 udelay(1000); 635 if (!timeout) 636 printf("MMC/SD: Reset never completed.\n"); 637 } 638 639 static const struct mmc_ops esdhc_ops = { 640 .send_cmd = esdhc_send_cmd, 641 .set_ios = esdhc_set_ios, 642 .init = esdhc_init, 643 .getcd = esdhc_getcd, 644 }; 645 646 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 647 { 648 struct fsl_esdhc *regs; 649 struct mmc *mmc; 650 u32 caps, voltage_caps; 651 652 if (!cfg) 653 return -1; 654 655 regs = (struct fsl_esdhc *)cfg->esdhc_base; 656 657 /* First reset the eSDHC controller */ 658 esdhc_reset(regs); 659 660 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 661 | SYSCTL_IPGEN | SYSCTL_CKEN); 662 663 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 664 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 665 666 voltage_caps = 0; 667 caps = esdhc_read32(®s->hostcapblt); 668 669 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 670 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 671 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 672 #endif 673 674 /* T4240 host controller capabilities register should have VS33 bit */ 675 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 676 caps = caps | ESDHC_HOSTCAPBLT_VS33; 677 #endif 678 679 if (caps & ESDHC_HOSTCAPBLT_VS18) 680 voltage_caps |= MMC_VDD_165_195; 681 if (caps & ESDHC_HOSTCAPBLT_VS30) 682 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 683 if (caps & ESDHC_HOSTCAPBLT_VS33) 684 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 685 686 cfg->cfg.name = "FSL_SDHC"; 687 cfg->cfg.ops = &esdhc_ops; 688 #ifdef CONFIG_SYS_SD_VOLTAGE 689 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 690 #else 691 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 692 #endif 693 if ((cfg->cfg.voltages & voltage_caps) == 0) { 694 printf("voltage not supported by controller\n"); 695 return -1; 696 } 697 698 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 699 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 700 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; 701 #endif 702 703 if (cfg->max_bus_width > 0) { 704 if (cfg->max_bus_width < 8) 705 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 706 if (cfg->max_bus_width < 4) 707 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 708 } 709 710 if (caps & ESDHC_HOSTCAPBLT_HSS) 711 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 712 713 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 714 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 715 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 716 #endif 717 718 cfg->cfg.f_min = 400000; 719 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); 720 721 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 722 723 mmc = mmc_create(&cfg->cfg, cfg); 724 if (mmc == NULL) 725 return -1; 726 727 return 0; 728 } 729 730 int fsl_esdhc_mmc_init(bd_t *bis) 731 { 732 struct fsl_esdhc_cfg *cfg; 733 734 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 735 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 736 cfg->sdhc_clk = gd->arch.sdhc_clk; 737 return fsl_esdhc_initialize(bis, cfg); 738 } 739 740 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 741 void mmc_adapter_card_type_ident(void) 742 { 743 u8 card_id; 744 u8 value; 745 746 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 747 gd->arch.sdhc_adapter = card_id; 748 749 switch (card_id) { 750 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 751 value = QIXIS_READ(brdcfg[5]); 752 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 753 QIXIS_WRITE(brdcfg[5], value); 754 break; 755 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 756 value = QIXIS_READ(pwr_ctl[1]); 757 value |= QIXIS_EVDD_BY_SDHC_VS; 758 QIXIS_WRITE(pwr_ctl[1], value); 759 break; 760 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 761 value = QIXIS_READ(brdcfg[5]); 762 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 763 QIXIS_WRITE(brdcfg[5], value); 764 break; 765 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 766 break; 767 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 768 break; 769 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 770 break; 771 case QIXIS_ESDHC_NO_ADAPTER: 772 break; 773 default: 774 break; 775 } 776 } 777 #endif 778 779 #ifdef CONFIG_OF_LIBFDT 780 void fdt_fixup_esdhc(void *blob, bd_t *bd) 781 { 782 const char *compat = "fsl,esdhc"; 783 784 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 785 if (!hwconfig("esdhc")) { 786 do_fixup_by_compat(blob, compat, "status", "disabled", 787 8 + 1, 1); 788 return; 789 } 790 #endif 791 792 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 793 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 794 gd->arch.sdhc_clk, 1); 795 #else 796 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 797 gd->arch.sdhc_clk, 1); 798 #endif 799 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 800 do_fixup_by_compat_u32(blob, compat, "adapter-type", 801 (u32)(gd->arch.sdhc_adapter), 1); 802 #endif 803 do_fixup_by_compat(blob, compat, "status", "okay", 804 4 + 1, 1); 805 } 806 #endif 807