1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 4 * Andy Fleming 5 * 6 * Based vaguely on the pxa mmc code: 7 * (C) Copyright 2003 8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <command.h> 14 #include <clk.h> 15 #include <errno.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <part.h> 19 #include <power/regulator.h> 20 #include <malloc.h> 21 #include <fsl_esdhc.h> 22 #include <fdt_support.h> 23 #include <asm/io.h> 24 #include <dm.h> 25 #include <asm-generic/gpio.h> 26 #include <dm/pinctrl.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 31 IRQSTATEN_CINT | \ 32 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 33 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 34 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 35 IRQSTATEN_DINT) 36 #define MAX_TUNING_LOOP 40 37 38 struct fsl_esdhc { 39 uint dsaddr; /* SDMA system address register */ 40 uint blkattr; /* Block attributes register */ 41 uint cmdarg; /* Command argument register */ 42 uint xfertyp; /* Transfer type register */ 43 uint cmdrsp0; /* Command response 0 register */ 44 uint cmdrsp1; /* Command response 1 register */ 45 uint cmdrsp2; /* Command response 2 register */ 46 uint cmdrsp3; /* Command response 3 register */ 47 uint datport; /* Buffer data port register */ 48 uint prsstat; /* Present state register */ 49 uint proctl; /* Protocol control register */ 50 uint sysctl; /* System Control Register */ 51 uint irqstat; /* Interrupt status register */ 52 uint irqstaten; /* Interrupt status enable register */ 53 uint irqsigen; /* Interrupt signal enable register */ 54 uint autoc12err; /* Auto CMD error status register */ 55 uint hostcapblt; /* Host controller capabilities register */ 56 uint wml; /* Watermark level register */ 57 uint mixctrl; /* For USDHC */ 58 char reserved1[4]; /* reserved */ 59 uint fevt; /* Force event register */ 60 uint admaes; /* ADMA error status register */ 61 uint adsaddr; /* ADMA system address register */ 62 char reserved2[4]; 63 uint dllctrl; 64 uint dllstat; 65 uint clktunectrlstatus; 66 char reserved3[4]; 67 uint strobe_dllctrl; 68 uint strobe_dllstat; 69 char reserved4[72]; 70 uint vendorspec; 71 uint mmcboot; 72 uint vendorspec2; 73 uint tuning_ctrl; /* on i.MX6/7/8 */ 74 char reserved5[44]; 75 uint hostver; /* Host controller version register */ 76 char reserved6[4]; /* reserved */ 77 uint dmaerraddr; /* DMA error address register */ 78 char reserved7[4]; /* reserved */ 79 uint dmaerrattr; /* DMA error attribute register */ 80 char reserved8[4]; /* reserved */ 81 uint hostcapblt2; /* Host controller capabilities register 2 */ 82 char reserved9[8]; /* reserved */ 83 uint tcr; /* Tuning control register */ 84 char reserved10[28]; /* reserved */ 85 uint sddirctl; /* SD direction control register */ 86 char reserved11[712];/* reserved */ 87 uint scr; /* eSDHC control register */ 88 }; 89 90 struct fsl_esdhc_plat { 91 struct mmc_config cfg; 92 struct mmc mmc; 93 }; 94 95 struct esdhc_soc_data { 96 u32 flags; 97 u32 caps; 98 }; 99 100 /** 101 * struct fsl_esdhc_priv 102 * 103 * @esdhc_regs: registers of the sdhc controller 104 * @sdhc_clk: Current clk of the sdhc controller 105 * @bus_width: bus width, 1bit, 4bit or 8bit 106 * @cfg: mmc config 107 * @mmc: mmc 108 * Following is used when Driver Model is enabled for MMC 109 * @dev: pointer for the device 110 * @non_removable: 0: removable; 1: non-removable 111 * @wp_enable: 1: enable checking wp; 0: no check 112 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 113 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h 114 * @caps: controller capabilities 115 * @tuning_step: tuning step setting in tuning_ctrl register 116 * @start_tuning_tap: the start point for tuning in tuning_ctrl register 117 * @strobe_dll_delay_target: settings in strobe_dllctrl 118 * @signal_voltage: indicating the current voltage 119 * @cd_gpio: gpio for card detection 120 * @wp_gpio: gpio for write protection 121 */ 122 struct fsl_esdhc_priv { 123 struct fsl_esdhc *esdhc_regs; 124 unsigned int sdhc_clk; 125 struct clk per_clk; 126 unsigned int clock; 127 unsigned int mode; 128 unsigned int bus_width; 129 #if !CONFIG_IS_ENABLED(BLK) 130 struct mmc *mmc; 131 #endif 132 struct udevice *dev; 133 int non_removable; 134 int wp_enable; 135 int vs18_enable; 136 u32 flags; 137 u32 caps; 138 u32 tuning_step; 139 u32 tuning_start_tap; 140 u32 strobe_dll_delay_target; 141 u32 signal_voltage; 142 #if IS_ENABLED(CONFIG_DM_REGULATOR) 143 struct udevice *vqmmc_dev; 144 struct udevice *vmmc_dev; 145 #endif 146 #ifdef CONFIG_DM_GPIO 147 struct gpio_desc cd_gpio; 148 struct gpio_desc wp_gpio; 149 #endif 150 }; 151 152 /* Return the XFERTYP flags for a given command and data packet */ 153 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 154 { 155 uint xfertyp = 0; 156 157 if (data) { 158 xfertyp |= XFERTYP_DPSEL; 159 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 160 xfertyp |= XFERTYP_DMAEN; 161 #endif 162 if (data->blocks > 1) { 163 xfertyp |= XFERTYP_MSBSEL; 164 xfertyp |= XFERTYP_BCEN; 165 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 166 xfertyp |= XFERTYP_AC12EN; 167 #endif 168 } 169 170 if (data->flags & MMC_DATA_READ) 171 xfertyp |= XFERTYP_DTDSEL; 172 } 173 174 if (cmd->resp_type & MMC_RSP_CRC) 175 xfertyp |= XFERTYP_CCCEN; 176 if (cmd->resp_type & MMC_RSP_OPCODE) 177 xfertyp |= XFERTYP_CICEN; 178 if (cmd->resp_type & MMC_RSP_136) 179 xfertyp |= XFERTYP_RSPTYP_136; 180 else if (cmd->resp_type & MMC_RSP_BUSY) 181 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 182 else if (cmd->resp_type & MMC_RSP_PRESENT) 183 xfertyp |= XFERTYP_RSPTYP_48; 184 185 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 186 xfertyp |= XFERTYP_CMDTYP_ABORT; 187 188 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 189 } 190 191 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 192 /* 193 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 194 */ 195 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 196 struct mmc_data *data) 197 { 198 struct fsl_esdhc *regs = priv->esdhc_regs; 199 uint blocks; 200 char *buffer; 201 uint databuf; 202 uint size; 203 uint irqstat; 204 ulong start; 205 206 if (data->flags & MMC_DATA_READ) { 207 blocks = data->blocks; 208 buffer = data->dest; 209 while (blocks) { 210 start = get_timer(0); 211 size = data->blocksize; 212 irqstat = esdhc_read32(®s->irqstat); 213 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { 214 if (get_timer(start) > PIO_TIMEOUT) { 215 printf("\nData Read Failed in PIO Mode."); 216 return; 217 } 218 } 219 while (size && (!(irqstat & IRQSTAT_TC))) { 220 udelay(100); /* Wait before last byte transfer complete */ 221 irqstat = esdhc_read32(®s->irqstat); 222 databuf = in_le32(®s->datport); 223 *((uint *)buffer) = databuf; 224 buffer += 4; 225 size -= 4; 226 } 227 blocks--; 228 } 229 } else { 230 blocks = data->blocks; 231 buffer = (char *)data->src; 232 while (blocks) { 233 start = get_timer(0); 234 size = data->blocksize; 235 irqstat = esdhc_read32(®s->irqstat); 236 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { 237 if (get_timer(start) > PIO_TIMEOUT) { 238 printf("\nData Write Failed in PIO Mode."); 239 return; 240 } 241 } 242 while (size && (!(irqstat & IRQSTAT_TC))) { 243 udelay(100); /* Wait before last byte transfer complete */ 244 databuf = *((uint *)buffer); 245 buffer += 4; 246 size -= 4; 247 irqstat = esdhc_read32(®s->irqstat); 248 out_le32(®s->datport, databuf); 249 } 250 blocks--; 251 } 252 } 253 } 254 #endif 255 256 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 257 struct mmc_data *data) 258 { 259 int timeout; 260 struct fsl_esdhc *regs = priv->esdhc_regs; 261 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 262 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 263 dma_addr_t addr; 264 #endif 265 uint wml_value; 266 267 wml_value = data->blocksize/4; 268 269 if (data->flags & MMC_DATA_READ) { 270 if (wml_value > WML_RD_WML_MAX) 271 wml_value = WML_RD_WML_MAX_VAL; 272 273 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 274 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 275 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 276 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 277 addr = virt_to_phys((void *)(data->dest)); 278 if (upper_32_bits(addr)) 279 printf("Error found for upper 32 bits\n"); 280 else 281 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 282 #else 283 esdhc_write32(®s->dsaddr, (u32)data->dest); 284 #endif 285 #endif 286 } else { 287 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 288 flush_dcache_range((ulong)data->src, 289 (ulong)data->src+data->blocks 290 *data->blocksize); 291 #endif 292 if (wml_value > WML_WR_WML_MAX) 293 wml_value = WML_WR_WML_MAX_VAL; 294 if (priv->wp_enable) { 295 if ((esdhc_read32(®s->prsstat) & 296 PRSSTAT_WPSPL) == 0) { 297 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 298 return -ETIMEDOUT; 299 } 300 } 301 302 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 303 wml_value << 16); 304 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 305 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 306 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 307 addr = virt_to_phys((void *)(data->src)); 308 if (upper_32_bits(addr)) 309 printf("Error found for upper 32 bits\n"); 310 else 311 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 312 #else 313 esdhc_write32(®s->dsaddr, (u32)data->src); 314 #endif 315 #endif 316 } 317 318 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 319 320 /* Calculate the timeout period for data transactions */ 321 /* 322 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 323 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 324 * So, Number of SD Clock cycles for 0.25sec should be minimum 325 * (SD Clock/sec * 0.25 sec) SD Clock cycles 326 * = (mmc->clock * 1/4) SD Clock cycles 327 * As 1) >= 2) 328 * => (2^(timeout+13)) >= mmc->clock * 1/4 329 * Taking log2 both the sides 330 * => timeout + 13 >= log2(mmc->clock/4) 331 * Rounding up to next power of 2 332 * => timeout + 13 = log2(mmc->clock/4) + 1 333 * => timeout + 13 = fls(mmc->clock/4) 334 * 335 * However, the MMC spec "It is strongly recommended for hosts to 336 * implement more than 500ms timeout value even if the card 337 * indicates the 250ms maximum busy length." Even the previous 338 * value of 300ms is known to be insufficient for some cards. 339 * So, we use 340 * => timeout + 13 = fls(mmc->clock/2) 341 */ 342 timeout = fls(mmc->clock/2); 343 timeout -= 13; 344 345 if (timeout > 14) 346 timeout = 14; 347 348 if (timeout < 0) 349 timeout = 0; 350 351 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 352 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 353 timeout++; 354 #endif 355 356 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 357 timeout = 0xE; 358 #endif 359 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 360 361 return 0; 362 } 363 364 static void check_and_invalidate_dcache_range 365 (struct mmc_cmd *cmd, 366 struct mmc_data *data) { 367 unsigned start = 0; 368 unsigned end = 0; 369 unsigned size = roundup(ARCH_DMA_MINALIGN, 370 data->blocks*data->blocksize); 371 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 372 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 373 dma_addr_t addr; 374 375 addr = virt_to_phys((void *)(data->dest)); 376 if (upper_32_bits(addr)) 377 printf("Error found for upper 32 bits\n"); 378 else 379 start = lower_32_bits(addr); 380 #else 381 start = (unsigned)data->dest; 382 #endif 383 end = start + size; 384 invalidate_dcache_range(start, end); 385 } 386 387 #ifdef CONFIG_MCF5441x 388 /* 389 * Swaps 32-bit words to little-endian byte order. 390 */ 391 static inline void sd_swap_dma_buff(struct mmc_data *data) 392 { 393 int i, size = data->blocksize >> 2; 394 u32 *buffer = (u32 *)data->dest; 395 u32 sw; 396 397 while (data->blocks--) { 398 for (i = 0; i < size; i++) { 399 sw = __sw32(*buffer); 400 *buffer++ = sw; 401 } 402 } 403 } 404 #endif 405 406 /* 407 * Sends a command out on the bus. Takes the mmc pointer, 408 * a command pointer, and an optional data pointer. 409 */ 410 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, 411 struct mmc_cmd *cmd, struct mmc_data *data) 412 { 413 int err = 0; 414 uint xfertyp; 415 uint irqstat; 416 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; 417 struct fsl_esdhc *regs = priv->esdhc_regs; 418 unsigned long start; 419 420 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 421 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 422 return 0; 423 #endif 424 425 esdhc_write32(®s->irqstat, -1); 426 427 sync(); 428 429 /* Wait for the bus to be idle */ 430 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 431 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 432 ; 433 434 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 435 ; 436 437 /* Wait at least 8 SD clock cycles before the next command */ 438 /* 439 * Note: This is way more than 8 cycles, but 1ms seems to 440 * resolve timing issues with some cards 441 */ 442 udelay(1000); 443 444 /* Set up for a data transfer if we have one */ 445 if (data) { 446 err = esdhc_setup_data(priv, mmc, data); 447 if(err) 448 return err; 449 450 if (data->flags & MMC_DATA_READ) 451 check_and_invalidate_dcache_range(cmd, data); 452 } 453 454 /* Figure out the transfer arguments */ 455 xfertyp = esdhc_xfertyp(cmd, data); 456 457 /* Mask all irqs */ 458 esdhc_write32(®s->irqsigen, 0); 459 460 /* Send the command */ 461 esdhc_write32(®s->cmdarg, cmd->cmdarg); 462 #if defined(CONFIG_FSL_USDHC) 463 esdhc_write32(®s->mixctrl, 464 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 465 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 466 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 467 #else 468 esdhc_write32(®s->xfertyp, xfertyp); 469 #endif 470 471 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 472 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) 473 flags = IRQSTAT_BRR; 474 475 /* Wait for the command to complete */ 476 start = get_timer(0); 477 while (!(esdhc_read32(®s->irqstat) & flags)) { 478 if (get_timer(start) > 1000) { 479 err = -ETIMEDOUT; 480 goto out; 481 } 482 } 483 484 irqstat = esdhc_read32(®s->irqstat); 485 486 if (irqstat & CMD_ERR) { 487 err = -ECOMM; 488 goto out; 489 } 490 491 if (irqstat & IRQSTAT_CTOE) { 492 err = -ETIMEDOUT; 493 goto out; 494 } 495 496 /* Switch voltage to 1.8V if CMD11 succeeded */ 497 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 498 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 499 500 printf("Run CMD11 1.8V switch\n"); 501 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 502 udelay(5000); 503 } 504 505 /* Workaround for ESDHC errata ENGcm03648 */ 506 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 507 int timeout = 6000; 508 509 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 510 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 511 PRSSTAT_DAT0)) { 512 udelay(100); 513 timeout--; 514 } 515 516 if (timeout <= 0) { 517 printf("Timeout waiting for DAT0 to go high!\n"); 518 err = -ETIMEDOUT; 519 goto out; 520 } 521 } 522 523 /* Copy the response to the response buffer */ 524 if (cmd->resp_type & MMC_RSP_136) { 525 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 526 527 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 528 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 529 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 530 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 531 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 532 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 533 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 534 cmd->response[3] = (cmdrsp0 << 8); 535 } else 536 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 537 538 /* Wait until all of the blocks are transferred */ 539 if (data) { 540 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 541 esdhc_pio_read_write(priv, data); 542 #else 543 flags = DATA_COMPLETE; 544 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 545 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) { 546 flags = IRQSTAT_BRR; 547 } 548 549 do { 550 irqstat = esdhc_read32(®s->irqstat); 551 552 if (irqstat & IRQSTAT_DTOE) { 553 err = -ETIMEDOUT; 554 goto out; 555 } 556 557 if (irqstat & DATA_ERR) { 558 err = -ECOMM; 559 goto out; 560 } 561 } while ((irqstat & flags) != flags); 562 563 /* 564 * Need invalidate the dcache here again to avoid any 565 * cache-fill during the DMA operations such as the 566 * speculative pre-fetching etc. 567 */ 568 if (data->flags & MMC_DATA_READ) { 569 check_and_invalidate_dcache_range(cmd, data); 570 #ifdef CONFIG_MCF5441x 571 sd_swap_dma_buff(data); 572 #endif 573 } 574 #endif 575 } 576 577 out: 578 /* Reset CMD and DATA portions on error */ 579 if (err) { 580 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 581 SYSCTL_RSTC); 582 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 583 ; 584 585 if (data) { 586 esdhc_write32(®s->sysctl, 587 esdhc_read32(®s->sysctl) | 588 SYSCTL_RSTD); 589 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 590 ; 591 } 592 593 /* If this was CMD11, then notify that power cycle is needed */ 594 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 595 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 596 } 597 598 esdhc_write32(®s->irqstat, -1); 599 600 return err; 601 } 602 603 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 604 { 605 struct fsl_esdhc *regs = priv->esdhc_regs; 606 int div = 1; 607 #ifdef ARCH_MXC 608 #ifdef CONFIG_MX53 609 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 610 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; 611 #else 612 int pre_div = 1; 613 #endif 614 #else 615 int pre_div = 2; 616 #endif 617 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 618 int sdhc_clk = priv->sdhc_clk; 619 uint clk; 620 621 if (clock < mmc->cfg->f_min) 622 clock = mmc->cfg->f_min; 623 624 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 625 pre_div *= 2; 626 627 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 628 div++; 629 630 pre_div >>= 1; 631 div -= 1; 632 633 clk = (pre_div << 8) | (div << 4); 634 635 #ifdef CONFIG_FSL_USDHC 636 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 637 #else 638 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 639 #endif 640 641 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 642 643 udelay(10000); 644 645 #ifdef CONFIG_FSL_USDHC 646 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 647 #else 648 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 649 #endif 650 651 priv->clock = clock; 652 } 653 654 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 655 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 656 { 657 struct fsl_esdhc *regs = priv->esdhc_regs; 658 u32 value; 659 u32 time_out; 660 661 value = esdhc_read32(®s->sysctl); 662 663 if (enable) 664 value |= SYSCTL_CKEN; 665 else 666 value &= ~SYSCTL_CKEN; 667 668 esdhc_write32(®s->sysctl, value); 669 670 time_out = 20; 671 value = PRSSTAT_SDSTB; 672 while (!(esdhc_read32(®s->prsstat) & value)) { 673 if (time_out == 0) { 674 printf("fsl_esdhc: Internal clock never stabilised.\n"); 675 break; 676 } 677 time_out--; 678 mdelay(1); 679 } 680 } 681 #endif 682 683 #ifdef MMC_SUPPORTS_TUNING 684 static int esdhc_change_pinstate(struct udevice *dev) 685 { 686 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 687 int ret; 688 689 switch (priv->mode) { 690 case UHS_SDR50: 691 case UHS_DDR50: 692 ret = pinctrl_select_state(dev, "state_100mhz"); 693 break; 694 case UHS_SDR104: 695 case MMC_HS_200: 696 case MMC_HS_400: 697 ret = pinctrl_select_state(dev, "state_200mhz"); 698 break; 699 default: 700 ret = pinctrl_select_state(dev, "default"); 701 break; 702 } 703 704 if (ret) 705 printf("%s %d error\n", __func__, priv->mode); 706 707 return ret; 708 } 709 710 static void esdhc_reset_tuning(struct mmc *mmc) 711 { 712 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 713 struct fsl_esdhc *regs = priv->esdhc_regs; 714 715 if (priv->flags & ESDHC_FLAG_USDHC) { 716 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 717 esdhc_clrbits32(®s->autoc12err, 718 MIX_CTRL_SMPCLK_SEL | 719 MIX_CTRL_EXE_TUNE); 720 } 721 } 722 } 723 724 static void esdhc_set_strobe_dll(struct mmc *mmc) 725 { 726 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 727 struct fsl_esdhc *regs = priv->esdhc_regs; 728 u32 val; 729 730 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { 731 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl); 732 733 /* 734 * enable strobe dll ctrl and adjust the delay target 735 * for the uSDHC loopback read clock 736 */ 737 val = ESDHC_STROBE_DLL_CTRL_ENABLE | 738 (priv->strobe_dll_delay_target << 739 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 740 writel(val, ®s->strobe_dllctrl); 741 /* wait 1us to make sure strobe dll status register stable */ 742 mdelay(1); 743 val = readl(®s->strobe_dllstat); 744 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) 745 pr_warn("HS400 strobe DLL status REF not lock!\n"); 746 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 747 pr_warn("HS400 strobe DLL status SLV not lock!\n"); 748 } 749 } 750 751 static int esdhc_set_timing(struct mmc *mmc) 752 { 753 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 754 struct fsl_esdhc *regs = priv->esdhc_regs; 755 u32 mixctrl; 756 757 mixctrl = readl(®s->mixctrl); 758 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); 759 760 switch (mmc->selected_mode) { 761 case MMC_LEGACY: 762 case SD_LEGACY: 763 esdhc_reset_tuning(mmc); 764 writel(mixctrl, ®s->mixctrl); 765 break; 766 case MMC_HS_400: 767 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; 768 writel(mixctrl, ®s->mixctrl); 769 esdhc_set_strobe_dll(mmc); 770 break; 771 case MMC_HS: 772 case MMC_HS_52: 773 case MMC_HS_200: 774 case SD_HS: 775 case UHS_SDR12: 776 case UHS_SDR25: 777 case UHS_SDR50: 778 case UHS_SDR104: 779 writel(mixctrl, ®s->mixctrl); 780 break; 781 case UHS_DDR50: 782 case MMC_DDR_52: 783 mixctrl |= MIX_CTRL_DDREN; 784 writel(mixctrl, ®s->mixctrl); 785 break; 786 default: 787 printf("Not supported %d\n", mmc->selected_mode); 788 return -EINVAL; 789 } 790 791 priv->mode = mmc->selected_mode; 792 793 return esdhc_change_pinstate(mmc->dev); 794 } 795 796 static int esdhc_set_voltage(struct mmc *mmc) 797 { 798 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 799 struct fsl_esdhc *regs = priv->esdhc_regs; 800 int ret; 801 802 priv->signal_voltage = mmc->signal_voltage; 803 switch (mmc->signal_voltage) { 804 case MMC_SIGNAL_VOLTAGE_330: 805 if (priv->vs18_enable) 806 return -EIO; 807 #if CONFIG_IS_ENABLED(DM_REGULATOR) 808 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 809 ret = regulator_set_value(priv->vqmmc_dev, 3300000); 810 if (ret) { 811 printf("Setting to 3.3V error"); 812 return -EIO; 813 } 814 /* Wait for 5ms */ 815 mdelay(5); 816 } 817 #endif 818 819 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 820 if (!(esdhc_read32(®s->vendorspec) & 821 ESDHC_VENDORSPEC_VSELECT)) 822 return 0; 823 824 return -EAGAIN; 825 case MMC_SIGNAL_VOLTAGE_180: 826 #if CONFIG_IS_ENABLED(DM_REGULATOR) 827 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 828 ret = regulator_set_value(priv->vqmmc_dev, 1800000); 829 if (ret) { 830 printf("Setting to 1.8V error"); 831 return -EIO; 832 } 833 } 834 #endif 835 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 836 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) 837 return 0; 838 839 return -EAGAIN; 840 case MMC_SIGNAL_VOLTAGE_120: 841 return -ENOTSUPP; 842 default: 843 return 0; 844 } 845 } 846 847 static void esdhc_stop_tuning(struct mmc *mmc) 848 { 849 struct mmc_cmd cmd; 850 851 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 852 cmd.cmdarg = 0; 853 cmd.resp_type = MMC_RSP_R1b; 854 855 dm_mmc_send_cmd(mmc->dev, &cmd, NULL); 856 } 857 858 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) 859 { 860 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 861 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 862 struct fsl_esdhc *regs = priv->esdhc_regs; 863 struct mmc *mmc = &plat->mmc; 864 u32 irqstaten = readl(®s->irqstaten); 865 u32 irqsigen = readl(®s->irqsigen); 866 int i, ret = -ETIMEDOUT; 867 u32 val, mixctrl; 868 869 /* clock tuning is not needed for upto 52MHz */ 870 if (mmc->clock <= 52000000) 871 return 0; 872 873 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ 874 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 875 val = readl(®s->autoc12err); 876 mixctrl = readl(®s->mixctrl); 877 val &= ~MIX_CTRL_SMPCLK_SEL; 878 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); 879 880 val |= MIX_CTRL_EXE_TUNE; 881 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; 882 883 writel(val, ®s->autoc12err); 884 writel(mixctrl, ®s->mixctrl); 885 } 886 887 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ 888 mixctrl = readl(®s->mixctrl); 889 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); 890 writel(mixctrl, ®s->mixctrl); 891 892 writel(IRQSTATEN_BRR, ®s->irqstaten); 893 writel(IRQSTATEN_BRR, ®s->irqsigen); 894 895 /* 896 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 897 * of loops reaches 40 times. 898 */ 899 for (i = 0; i < MAX_TUNING_LOOP; i++) { 900 u32 ctrl; 901 902 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { 903 if (mmc->bus_width == 8) 904 writel(0x7080, ®s->blkattr); 905 else if (mmc->bus_width == 4) 906 writel(0x7040, ®s->blkattr); 907 } else { 908 writel(0x7040, ®s->blkattr); 909 } 910 911 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ 912 val = readl(®s->mixctrl); 913 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); 914 writel(val, ®s->mixctrl); 915 916 /* We are using STD tuning, no need to check return value */ 917 mmc_send_tuning(mmc, opcode, NULL); 918 919 ctrl = readl(®s->autoc12err); 920 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && 921 (ctrl & MIX_CTRL_SMPCLK_SEL)) { 922 /* 923 * need to wait some time, make sure sd/mmc fininsh 924 * send out tuning data, otherwise, the sd/mmc can't 925 * response to any command when the card still out 926 * put the tuning data. 927 */ 928 mdelay(1); 929 ret = 0; 930 break; 931 } 932 933 /* Add 1ms delay for SD and eMMC */ 934 mdelay(1); 935 } 936 937 writel(irqstaten, ®s->irqstaten); 938 writel(irqsigen, ®s->irqsigen); 939 940 esdhc_stop_tuning(mmc); 941 942 return ret; 943 } 944 #endif 945 946 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 947 { 948 struct fsl_esdhc *regs = priv->esdhc_regs; 949 int ret __maybe_unused; 950 951 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 952 /* Select to use peripheral clock */ 953 esdhc_clock_control(priv, false); 954 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 955 esdhc_clock_control(priv, true); 956 #endif 957 /* Set the clock speed */ 958 if (priv->clock != mmc->clock) 959 set_sysctl(priv, mmc, mmc->clock); 960 961 #ifdef MMC_SUPPORTS_TUNING 962 if (mmc->clk_disable) { 963 #ifdef CONFIG_FSL_USDHC 964 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 965 #else 966 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 967 #endif 968 } else { 969 #ifdef CONFIG_FSL_USDHC 970 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 971 VENDORSPEC_CKEN); 972 #else 973 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 974 #endif 975 } 976 977 if (priv->mode != mmc->selected_mode) { 978 ret = esdhc_set_timing(mmc); 979 if (ret) { 980 printf("esdhc_set_timing error %d\n", ret); 981 return ret; 982 } 983 } 984 985 if (priv->signal_voltage != mmc->signal_voltage) { 986 ret = esdhc_set_voltage(mmc); 987 if (ret) { 988 printf("esdhc_set_voltage error %d\n", ret); 989 return ret; 990 } 991 } 992 #endif 993 994 /* Set the bus width */ 995 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 996 997 if (mmc->bus_width == 4) 998 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 999 else if (mmc->bus_width == 8) 1000 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 1001 1002 return 0; 1003 } 1004 1005 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 1006 { 1007 struct fsl_esdhc *regs = priv->esdhc_regs; 1008 ulong start; 1009 1010 /* Reset the entire host controller */ 1011 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 1012 1013 /* Wait until the controller is available */ 1014 start = get_timer(0); 1015 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 1016 if (get_timer(start) > 1000) 1017 return -ETIMEDOUT; 1018 } 1019 1020 #if defined(CONFIG_FSL_USDHC) 1021 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 1022 esdhc_write32(®s->mmcboot, 0x0); 1023 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 1024 esdhc_write32(®s->mixctrl, 0x0); 1025 esdhc_write32(®s->clktunectrlstatus, 0x0); 1026 1027 /* Put VEND_SPEC to default value */ 1028 if (priv->vs18_enable) 1029 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | 1030 ESDHC_VENDORSPEC_VSELECT)); 1031 else 1032 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 1033 1034 /* Disable DLL_CTRL delay line */ 1035 esdhc_write32(®s->dllctrl, 0x0); 1036 #endif 1037 1038 #ifndef ARCH_MXC 1039 /* Enable cache snooping */ 1040 esdhc_write32(®s->scr, 0x00000040); 1041 #endif 1042 1043 #ifndef CONFIG_FSL_USDHC 1044 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 1045 #else 1046 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 1047 #endif 1048 1049 /* Set the initial clock speed */ 1050 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); 1051 1052 /* Disable the BRR and BWR bits in IRQSTAT */ 1053 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 1054 1055 #ifdef CONFIG_MCF5441x 1056 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); 1057 #else 1058 /* Put the PROCTL reg back to the default */ 1059 esdhc_write32(®s->proctl, PROCTL_INIT); 1060 #endif 1061 1062 /* Set timout to the maximum value */ 1063 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 1064 1065 return 0; 1066 } 1067 1068 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) 1069 { 1070 struct fsl_esdhc *regs = priv->esdhc_regs; 1071 int timeout = 1000; 1072 1073 #ifdef CONFIG_ESDHC_DETECT_QUIRK 1074 if (CONFIG_ESDHC_DETECT_QUIRK) 1075 return 1; 1076 #endif 1077 1078 #if CONFIG_IS_ENABLED(DM_MMC) 1079 if (priv->non_removable) 1080 return 1; 1081 #ifdef CONFIG_DM_GPIO 1082 if (dm_gpio_is_valid(&priv->cd_gpio)) 1083 return dm_gpio_get_value(&priv->cd_gpio); 1084 #endif 1085 #endif 1086 1087 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 1088 udelay(1000); 1089 1090 return timeout > 0; 1091 } 1092 1093 static int esdhc_reset(struct fsl_esdhc *regs) 1094 { 1095 ulong start; 1096 1097 /* reset the controller */ 1098 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 1099 1100 /* hardware clears the bit when it is done */ 1101 start = get_timer(0); 1102 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { 1103 if (get_timer(start) > 100) { 1104 printf("MMC/SD: Reset never completed.\n"); 1105 return -ETIMEDOUT; 1106 } 1107 } 1108 1109 return 0; 1110 } 1111 1112 #if !CONFIG_IS_ENABLED(DM_MMC) 1113 static int esdhc_getcd(struct mmc *mmc) 1114 { 1115 struct fsl_esdhc_priv *priv = mmc->priv; 1116 1117 return esdhc_getcd_common(priv); 1118 } 1119 1120 static int esdhc_init(struct mmc *mmc) 1121 { 1122 struct fsl_esdhc_priv *priv = mmc->priv; 1123 1124 return esdhc_init_common(priv, mmc); 1125 } 1126 1127 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 1128 struct mmc_data *data) 1129 { 1130 struct fsl_esdhc_priv *priv = mmc->priv; 1131 1132 return esdhc_send_cmd_common(priv, mmc, cmd, data); 1133 } 1134 1135 static int esdhc_set_ios(struct mmc *mmc) 1136 { 1137 struct fsl_esdhc_priv *priv = mmc->priv; 1138 1139 return esdhc_set_ios_common(priv, mmc); 1140 } 1141 1142 static const struct mmc_ops esdhc_ops = { 1143 .getcd = esdhc_getcd, 1144 .init = esdhc_init, 1145 .send_cmd = esdhc_send_cmd, 1146 .set_ios = esdhc_set_ios, 1147 }; 1148 #endif 1149 1150 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, 1151 struct fsl_esdhc_plat *plat) 1152 { 1153 struct mmc_config *cfg; 1154 struct fsl_esdhc *regs; 1155 u32 caps, voltage_caps; 1156 int ret; 1157 1158 if (!priv) 1159 return -EINVAL; 1160 1161 regs = priv->esdhc_regs; 1162 1163 /* First reset the eSDHC controller */ 1164 ret = esdhc_reset(regs); 1165 if (ret) 1166 return ret; 1167 1168 #ifdef CONFIG_MCF5441x 1169 /* ColdFire, using SDHC_DATA[3] for card detection */ 1170 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); 1171 #endif 1172 1173 #ifndef CONFIG_FSL_USDHC 1174 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 1175 | SYSCTL_IPGEN | SYSCTL_CKEN); 1176 /* Clearing tuning bits in case ROM has set it already */ 1177 esdhc_write32(®s->mixctrl, 0); 1178 esdhc_write32(®s->autoc12err, 0); 1179 esdhc_write32(®s->clktunectrlstatus, 0); 1180 #else 1181 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 1182 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 1183 #endif 1184 1185 if (priv->vs18_enable) 1186 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 1187 1188 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 1189 cfg = &plat->cfg; 1190 #ifndef CONFIG_DM_MMC 1191 memset(cfg, '\0', sizeof(*cfg)); 1192 #endif 1193 1194 voltage_caps = 0; 1195 caps = esdhc_read32(®s->hostcapblt); 1196 1197 #ifdef CONFIG_MCF5441x 1198 /* 1199 * MCF5441x RM declares in more points that sdhc clock speed must 1200 * never exceed 25 Mhz. From this, the HS bit needs to be disabled 1201 * from host capabilities. 1202 */ 1203 caps &= ~ESDHC_HOSTCAPBLT_HSS; 1204 #endif 1205 1206 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 1207 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 1208 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 1209 #endif 1210 1211 /* T4240 host controller capabilities register should have VS33 bit */ 1212 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 1213 caps = caps | ESDHC_HOSTCAPBLT_VS33; 1214 #endif 1215 1216 if (caps & ESDHC_HOSTCAPBLT_VS18) 1217 voltage_caps |= MMC_VDD_165_195; 1218 if (caps & ESDHC_HOSTCAPBLT_VS30) 1219 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 1220 if (caps & ESDHC_HOSTCAPBLT_VS33) 1221 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 1222 1223 cfg->name = "FSL_SDHC"; 1224 #if !CONFIG_IS_ENABLED(DM_MMC) 1225 cfg->ops = &esdhc_ops; 1226 #endif 1227 #ifdef CONFIG_SYS_SD_VOLTAGE 1228 cfg->voltages = CONFIG_SYS_SD_VOLTAGE; 1229 #else 1230 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 1231 #endif 1232 if ((cfg->voltages & voltage_caps) == 0) { 1233 printf("voltage not supported by controller\n"); 1234 return -1; 1235 } 1236 1237 if (priv->bus_width == 8) 1238 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1239 else if (priv->bus_width == 4) 1240 cfg->host_caps = MMC_MODE_4BIT; 1241 1242 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1243 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 1244 cfg->host_caps |= MMC_MODE_DDR_52MHz; 1245 #endif 1246 1247 if (priv->bus_width > 0) { 1248 if (priv->bus_width < 8) 1249 cfg->host_caps &= ~MMC_MODE_8BIT; 1250 if (priv->bus_width < 4) 1251 cfg->host_caps &= ~MMC_MODE_4BIT; 1252 } 1253 1254 if (caps & ESDHC_HOSTCAPBLT_HSS) 1255 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1256 1257 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 1258 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 1259 cfg->host_caps &= ~MMC_MODE_8BIT; 1260 #endif 1261 1262 cfg->host_caps |= priv->caps; 1263 1264 cfg->f_min = 400000; 1265 cfg->f_max = min(priv->sdhc_clk, (u32)200000000); 1266 1267 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1268 1269 writel(0, ®s->dllctrl); 1270 if (priv->flags & ESDHC_FLAG_USDHC) { 1271 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 1272 u32 val = readl(®s->tuning_ctrl); 1273 1274 val |= ESDHC_STD_TUNING_EN; 1275 val &= ~ESDHC_TUNING_START_TAP_MASK; 1276 val |= priv->tuning_start_tap; 1277 val &= ~ESDHC_TUNING_STEP_MASK; 1278 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT; 1279 writel(val, ®s->tuning_ctrl); 1280 } 1281 } 1282 1283 return 0; 1284 } 1285 1286 #if !CONFIG_IS_ENABLED(DM_MMC) 1287 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 1288 struct fsl_esdhc_priv *priv) 1289 { 1290 if (!cfg || !priv) 1291 return -EINVAL; 1292 1293 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 1294 priv->bus_width = cfg->max_bus_width; 1295 priv->sdhc_clk = cfg->sdhc_clk; 1296 priv->wp_enable = cfg->wp_enable; 1297 priv->vs18_enable = cfg->vs18_enable; 1298 1299 return 0; 1300 }; 1301 1302 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 1303 { 1304 struct fsl_esdhc_plat *plat; 1305 struct fsl_esdhc_priv *priv; 1306 struct mmc *mmc; 1307 int ret; 1308 1309 if (!cfg) 1310 return -EINVAL; 1311 1312 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 1313 if (!priv) 1314 return -ENOMEM; 1315 plat = calloc(sizeof(struct fsl_esdhc_plat), 1); 1316 if (!plat) { 1317 free(priv); 1318 return -ENOMEM; 1319 } 1320 1321 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 1322 if (ret) { 1323 debug("%s xlate failure\n", __func__); 1324 free(plat); 1325 free(priv); 1326 return ret; 1327 } 1328 1329 ret = fsl_esdhc_init(priv, plat); 1330 if (ret) { 1331 debug("%s init failure\n", __func__); 1332 free(plat); 1333 free(priv); 1334 return ret; 1335 } 1336 1337 mmc = mmc_create(&plat->cfg, priv); 1338 if (!mmc) 1339 return -EIO; 1340 1341 priv->mmc = mmc; 1342 1343 return 0; 1344 } 1345 1346 int fsl_esdhc_mmc_init(bd_t *bis) 1347 { 1348 struct fsl_esdhc_cfg *cfg; 1349 1350 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 1351 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 1352 cfg->sdhc_clk = gd->arch.sdhc_clk; 1353 return fsl_esdhc_initialize(bis, cfg); 1354 } 1355 #endif 1356 1357 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1358 void mmc_adapter_card_type_ident(void) 1359 { 1360 u8 card_id; 1361 u8 value; 1362 1363 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 1364 gd->arch.sdhc_adapter = card_id; 1365 1366 switch (card_id) { 1367 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 1368 value = QIXIS_READ(brdcfg[5]); 1369 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 1370 QIXIS_WRITE(brdcfg[5], value); 1371 break; 1372 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 1373 value = QIXIS_READ(pwr_ctl[1]); 1374 value |= QIXIS_EVDD_BY_SDHC_VS; 1375 QIXIS_WRITE(pwr_ctl[1], value); 1376 break; 1377 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 1378 value = QIXIS_READ(brdcfg[5]); 1379 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 1380 QIXIS_WRITE(brdcfg[5], value); 1381 break; 1382 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 1383 break; 1384 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 1385 break; 1386 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 1387 break; 1388 case QIXIS_ESDHC_NO_ADAPTER: 1389 break; 1390 default: 1391 break; 1392 } 1393 } 1394 #endif 1395 1396 #ifdef CONFIG_OF_LIBFDT 1397 __weak int esdhc_status_fixup(void *blob, const char *compat) 1398 { 1399 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 1400 if (!hwconfig("esdhc")) { 1401 do_fixup_by_compat(blob, compat, "status", "disabled", 1402 sizeof("disabled"), 1); 1403 return 1; 1404 } 1405 #endif 1406 return 0; 1407 } 1408 1409 void fdt_fixup_esdhc(void *blob, bd_t *bd) 1410 { 1411 const char *compat = "fsl,esdhc"; 1412 1413 if (esdhc_status_fixup(blob, compat)) 1414 return; 1415 1416 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 1417 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 1418 gd->arch.sdhc_clk, 1); 1419 #else 1420 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 1421 gd->arch.sdhc_clk, 1); 1422 #endif 1423 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1424 do_fixup_by_compat_u32(blob, compat, "adapter-type", 1425 (u32)(gd->arch.sdhc_adapter), 1); 1426 #endif 1427 } 1428 #endif 1429 1430 #if CONFIG_IS_ENABLED(DM_MMC) 1431 #include <asm/arch/clock.h> 1432 __weak void init_clk_usdhc(u32 index) 1433 { 1434 } 1435 1436 static int fsl_esdhc_probe(struct udevice *dev) 1437 { 1438 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1439 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1440 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1441 const void *fdt = gd->fdt_blob; 1442 int node = dev_of_offset(dev); 1443 struct esdhc_soc_data *data = 1444 (struct esdhc_soc_data *)dev_get_driver_data(dev); 1445 #if CONFIG_IS_ENABLED(DM_REGULATOR) 1446 struct udevice *vqmmc_dev; 1447 #endif 1448 fdt_addr_t addr; 1449 unsigned int val; 1450 struct mmc *mmc; 1451 int ret; 1452 1453 addr = dev_read_addr(dev); 1454 if (addr == FDT_ADDR_T_NONE) 1455 return -EINVAL; 1456 1457 priv->esdhc_regs = (struct fsl_esdhc *)addr; 1458 priv->dev = dev; 1459 priv->mode = -1; 1460 if (data) { 1461 priv->flags = data->flags; 1462 priv->caps = data->caps; 1463 } 1464 1465 val = dev_read_u32_default(dev, "bus-width", -1); 1466 if (val == 8) 1467 priv->bus_width = 8; 1468 else if (val == 4) 1469 priv->bus_width = 4; 1470 else 1471 priv->bus_width = 1; 1472 1473 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1); 1474 priv->tuning_step = val; 1475 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", 1476 ESDHC_TUNING_START_TAP_DEFAULT); 1477 priv->tuning_start_tap = val; 1478 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", 1479 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); 1480 priv->strobe_dll_delay_target = val; 1481 1482 if (dev_read_bool(dev, "non-removable")) { 1483 priv->non_removable = 1; 1484 } else { 1485 priv->non_removable = 0; 1486 #ifdef CONFIG_DM_GPIO 1487 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 1488 GPIOD_IS_IN); 1489 #endif 1490 } 1491 1492 priv->wp_enable = 1; 1493 1494 #ifdef CONFIG_DM_GPIO 1495 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 1496 GPIOD_IS_IN); 1497 if (ret) 1498 priv->wp_enable = 0; 1499 #endif 1500 1501 priv->vs18_enable = 0; 1502 1503 #if CONFIG_IS_ENABLED(DM_REGULATOR) 1504 /* 1505 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1506 * otherwise, emmc will work abnormally. 1507 */ 1508 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1509 if (ret) { 1510 dev_dbg(dev, "no vqmmc-supply\n"); 1511 } else { 1512 ret = regulator_set_enable(vqmmc_dev, true); 1513 if (ret) { 1514 dev_err(dev, "fail to enable vqmmc-supply\n"); 1515 return ret; 1516 } 1517 1518 if (regulator_get_value(vqmmc_dev) == 1800000) 1519 priv->vs18_enable = 1; 1520 } 1521 #endif 1522 1523 if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) 1524 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400); 1525 1526 /* 1527 * TODO: 1528 * Because lack of clk driver, if SDHC clk is not enabled, 1529 * need to enable it first before this driver is invoked. 1530 * 1531 * we use MXC_ESDHC_CLK to get clk freq. 1532 * If one would like to make this function work, 1533 * the aliases should be provided in dts as this: 1534 * 1535 * aliases { 1536 * mmc0 = &usdhc1; 1537 * mmc1 = &usdhc2; 1538 * mmc2 = &usdhc3; 1539 * mmc3 = &usdhc4; 1540 * }; 1541 * Then if your board only supports mmc2 and mmc3, but we can 1542 * correctly get the seq as 2 and 3, then let mxc_get_clock 1543 * work as expected. 1544 */ 1545 1546 init_clk_usdhc(dev->seq); 1547 1548 if (IS_ENABLED(CONFIG_CLK)) { 1549 /* Assigned clock already set clock */ 1550 ret = clk_get_by_name(dev, "per", &priv->per_clk); 1551 if (ret) { 1552 printf("Failed to get per_clk\n"); 1553 return ret; 1554 } 1555 ret = clk_enable(&priv->per_clk); 1556 if (ret) { 1557 printf("Failed to enable per_clk\n"); 1558 return ret; 1559 } 1560 1561 priv->sdhc_clk = clk_get_rate(&priv->per_clk); 1562 } else { 1563 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1564 if (priv->sdhc_clk <= 0) { 1565 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1566 return -EINVAL; 1567 } 1568 } 1569 1570 ret = fsl_esdhc_init(priv, plat); 1571 if (ret) { 1572 dev_err(dev, "fsl_esdhc_init failure\n"); 1573 return ret; 1574 } 1575 1576 mmc = &plat->mmc; 1577 mmc->cfg = &plat->cfg; 1578 mmc->dev = dev; 1579 upriv->mmc = mmc; 1580 1581 return esdhc_init_common(priv, mmc); 1582 } 1583 1584 #if CONFIG_IS_ENABLED(DM_MMC) 1585 static int fsl_esdhc_get_cd(struct udevice *dev) 1586 { 1587 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1588 1589 return esdhc_getcd_common(priv); 1590 } 1591 1592 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 1593 struct mmc_data *data) 1594 { 1595 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1596 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1597 1598 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); 1599 } 1600 1601 static int fsl_esdhc_set_ios(struct udevice *dev) 1602 { 1603 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1604 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1605 1606 return esdhc_set_ios_common(priv, &plat->mmc); 1607 } 1608 1609 static const struct dm_mmc_ops fsl_esdhc_ops = { 1610 .get_cd = fsl_esdhc_get_cd, 1611 .send_cmd = fsl_esdhc_send_cmd, 1612 .set_ios = fsl_esdhc_set_ios, 1613 #ifdef MMC_SUPPORTS_TUNING 1614 .execute_tuning = fsl_esdhc_execute_tuning, 1615 #endif 1616 }; 1617 #endif 1618 1619 static struct esdhc_soc_data usdhc_imx7d_data = { 1620 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1621 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 1622 | ESDHC_FLAG_HS400, 1623 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | 1624 MMC_MODE_HS_52MHz | MMC_MODE_HS, 1625 }; 1626 1627 static const struct udevice_id fsl_esdhc_ids[] = { 1628 { .compatible = "fsl,imx53-esdhc", }, 1629 { .compatible = "fsl,imx6ul-usdhc", }, 1630 { .compatible = "fsl,imx6sx-usdhc", }, 1631 { .compatible = "fsl,imx6sl-usdhc", }, 1632 { .compatible = "fsl,imx6q-usdhc", }, 1633 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, 1634 { .compatible = "fsl,imx7ulp-usdhc", }, 1635 { .compatible = "fsl,esdhc", }, 1636 { /* sentinel */ } 1637 }; 1638 1639 #if CONFIG_IS_ENABLED(BLK) 1640 static int fsl_esdhc_bind(struct udevice *dev) 1641 { 1642 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1643 1644 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1645 } 1646 #endif 1647 1648 U_BOOT_DRIVER(fsl_esdhc) = { 1649 .name = "fsl-esdhc-mmc", 1650 .id = UCLASS_MMC, 1651 .of_match = fsl_esdhc_ids, 1652 .ops = &fsl_esdhc_ops, 1653 #if CONFIG_IS_ENABLED(BLK) 1654 .bind = fsl_esdhc_bind, 1655 #endif 1656 .probe = fsl_esdhc_probe, 1657 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), 1658 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1659 }; 1660 #endif 1661