1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 uint mixctrl; 62 char reserved1[4]; 63 uint fevt; 64 char reserved2[168]; 65 uint hostver; 66 char reserved3[780]; 67 uint scr; 68 }; 69 70 /* Return the XFERTYP flags for a given command and data packet */ 71 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 72 { 73 uint xfertyp = 0; 74 75 if (data) { 76 xfertyp |= XFERTYP_DPSEL; 77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 78 xfertyp |= XFERTYP_DMAEN; 79 #endif 80 if (data->blocks > 1) { 81 xfertyp |= XFERTYP_MSBSEL; 82 xfertyp |= XFERTYP_BCEN; 83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 84 xfertyp |= XFERTYP_AC12EN; 85 #endif 86 } 87 88 if (data->flags & MMC_DATA_READ) 89 xfertyp |= XFERTYP_DTDSEL; 90 } 91 92 if (cmd->resp_type & MMC_RSP_CRC) 93 xfertyp |= XFERTYP_CCCEN; 94 if (cmd->resp_type & MMC_RSP_OPCODE) 95 xfertyp |= XFERTYP_CICEN; 96 if (cmd->resp_type & MMC_RSP_136) 97 xfertyp |= XFERTYP_RSPTYP_136; 98 else if (cmd->resp_type & MMC_RSP_BUSY) 99 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 100 else if (cmd->resp_type & MMC_RSP_PRESENT) 101 xfertyp |= XFERTYP_RSPTYP_48; 102 103 #ifdef CONFIG_MX53 104 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 105 xfertyp |= XFERTYP_CMDTYP_ABORT; 106 #endif 107 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 108 } 109 110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 111 /* 112 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 113 */ 114 static void 115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 116 { 117 struct fsl_esdhc_cfg *cfg = mmc->priv; 118 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 119 uint blocks; 120 char *buffer; 121 uint databuf; 122 uint size; 123 uint irqstat; 124 uint timeout; 125 126 if (data->flags & MMC_DATA_READ) { 127 blocks = data->blocks; 128 buffer = data->dest; 129 while (blocks) { 130 timeout = PIO_TIMEOUT; 131 size = data->blocksize; 132 irqstat = esdhc_read32(®s->irqstat); 133 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 134 && --timeout); 135 if (timeout <= 0) { 136 printf("\nData Read Failed in PIO Mode."); 137 return; 138 } 139 while (size && (!(irqstat & IRQSTAT_TC))) { 140 udelay(100); /* Wait before last byte transfer complete */ 141 irqstat = esdhc_read32(®s->irqstat); 142 databuf = in_le32(®s->datport); 143 *((uint *)buffer) = databuf; 144 buffer += 4; 145 size -= 4; 146 } 147 blocks--; 148 } 149 } else { 150 blocks = data->blocks; 151 buffer = (char *)data->src; 152 while (blocks) { 153 timeout = PIO_TIMEOUT; 154 size = data->blocksize; 155 irqstat = esdhc_read32(®s->irqstat); 156 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 157 && --timeout); 158 if (timeout <= 0) { 159 printf("\nData Write Failed in PIO Mode."); 160 return; 161 } 162 while (size && (!(irqstat & IRQSTAT_TC))) { 163 udelay(100); /* Wait before last byte transfer complete */ 164 databuf = *((uint *)buffer); 165 buffer += 4; 166 size -= 4; 167 irqstat = esdhc_read32(®s->irqstat); 168 out_le32(®s->datport, databuf); 169 } 170 blocks--; 171 } 172 } 173 } 174 #endif 175 176 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 177 { 178 int timeout; 179 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 180 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 181 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 182 uint wml_value; 183 184 wml_value = data->blocksize/4; 185 186 if (data->flags & MMC_DATA_READ) { 187 if (wml_value > WML_RD_WML_MAX) 188 wml_value = WML_RD_WML_MAX_VAL; 189 190 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 191 esdhc_write32(®s->dsaddr, (u32)data->dest); 192 } else { 193 if (wml_value > WML_WR_WML_MAX) 194 wml_value = WML_WR_WML_MAX_VAL; 195 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 196 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 197 return TIMEOUT; 198 } 199 200 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 201 wml_value << 16); 202 esdhc_write32(®s->dsaddr, (u32)data->src); 203 } 204 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 205 if (!(data->flags & MMC_DATA_READ)) { 206 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 207 printf("\nThe SD card is locked. " 208 "Can not write to a locked card.\n\n"); 209 return TIMEOUT; 210 } 211 esdhc_write32(®s->dsaddr, (u32)data->src); 212 } else 213 esdhc_write32(®s->dsaddr, (u32)data->dest); 214 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 215 216 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 217 218 /* Calculate the timeout period for data transactions */ 219 /* 220 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 221 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 222 * So, Number of SD Clock cycles for 0.25sec should be minimum 223 * (SD Clock/sec * 0.25 sec) SD Clock cycles 224 * = (mmc->tran_speed * 1/4) SD Clock cycles 225 * As 1) >= 2) 226 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 227 * Taking log2 both the sides 228 * => timeout + 13 >= log2(mmc->tran_speed/4) 229 * Rounding up to next power of 2 230 * => timeout + 13 = log2(mmc->tran_speed/4) + 1 231 * => timeout + 13 = fls(mmc->tran_speed/4) 232 */ 233 timeout = fls(mmc->tran_speed/4); 234 timeout -= 13; 235 236 if (timeout > 14) 237 timeout = 14; 238 239 if (timeout < 0) 240 timeout = 0; 241 242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 243 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 244 timeout++; 245 #endif 246 247 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 248 249 return 0; 250 } 251 252 253 /* 254 * Sends a command out on the bus. Takes the mmc pointer, 255 * a command pointer, and an optional data pointer. 256 */ 257 static int 258 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 259 { 260 uint xfertyp; 261 uint irqstat; 262 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 263 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 264 265 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 266 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 267 return 0; 268 #endif 269 270 esdhc_write32(®s->irqstat, -1); 271 272 sync(); 273 274 /* Wait for the bus to be idle */ 275 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 276 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 277 ; 278 279 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 280 ; 281 282 /* Wait at least 8 SD clock cycles before the next command */ 283 /* 284 * Note: This is way more than 8 cycles, but 1ms seems to 285 * resolve timing issues with some cards 286 */ 287 udelay(1000); 288 289 /* Set up for a data transfer if we have one */ 290 if (data) { 291 int err; 292 293 err = esdhc_setup_data(mmc, data); 294 if(err) 295 return err; 296 } 297 298 /* Figure out the transfer arguments */ 299 xfertyp = esdhc_xfertyp(cmd, data); 300 301 /* Send the command */ 302 esdhc_write32(®s->cmdarg, cmd->cmdarg); 303 #if defined(CONFIG_FSL_USDHC) 304 esdhc_write32(®s->mixctrl, 305 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); 306 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 307 #else 308 esdhc_write32(®s->xfertyp, xfertyp); 309 #endif 310 311 /* Mask all irqs */ 312 esdhc_write32(®s->irqsigen, 0); 313 314 /* Wait for the command to complete */ 315 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 316 ; 317 318 irqstat = esdhc_read32(®s->irqstat); 319 esdhc_write32(®s->irqstat, irqstat); 320 321 /* Reset CMD and DATA portions on error */ 322 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { 323 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 324 SYSCTL_RSTC); 325 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 326 ; 327 328 if (data) { 329 esdhc_write32(®s->sysctl, 330 esdhc_read32(®s->sysctl) | 331 SYSCTL_RSTD); 332 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 333 ; 334 } 335 } 336 337 if (irqstat & CMD_ERR) 338 return COMM_ERR; 339 340 if (irqstat & IRQSTAT_CTOE) 341 return TIMEOUT; 342 343 /* Workaround for ESDHC errata ENGcm03648 */ 344 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 345 int timeout = 2500; 346 347 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 348 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 349 PRSSTAT_DAT0)) { 350 udelay(100); 351 timeout--; 352 } 353 354 if (timeout <= 0) { 355 printf("Timeout waiting for DAT0 to go high!\n"); 356 return TIMEOUT; 357 } 358 } 359 360 /* Copy the response to the response buffer */ 361 if (cmd->resp_type & MMC_RSP_136) { 362 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 363 364 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 365 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 366 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 367 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 368 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 369 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 370 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 371 cmd->response[3] = (cmdrsp0 << 8); 372 } else 373 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 374 375 /* Wait until all of the blocks are transferred */ 376 if (data) { 377 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 378 esdhc_pio_read_write(mmc, data); 379 #else 380 do { 381 irqstat = esdhc_read32(®s->irqstat); 382 383 if (irqstat & IRQSTAT_DTOE) 384 return TIMEOUT; 385 386 if (irqstat & DATA_ERR) 387 return COMM_ERR; 388 } while (!(irqstat & IRQSTAT_TC) && 389 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); 390 #endif 391 } 392 393 esdhc_write32(®s->irqstat, -1); 394 395 return 0; 396 } 397 398 void set_sysctl(struct mmc *mmc, uint clock) 399 { 400 int sdhc_clk = gd->sdhc_clk; 401 int div, pre_div; 402 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 403 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 404 uint clk; 405 406 if (clock < mmc->f_min) 407 clock = mmc->f_min; 408 409 if (sdhc_clk / 16 > clock) { 410 for (pre_div = 2; pre_div < 256; pre_div *= 2) 411 if ((sdhc_clk / pre_div) <= (clock * 16)) 412 break; 413 } else 414 pre_div = 2; 415 416 for (div = 1; div <= 16; div++) 417 if ((sdhc_clk / (div * pre_div)) <= clock) 418 break; 419 420 pre_div >>= 1; 421 div -= 1; 422 423 clk = (pre_div << 8) | (div << 4); 424 425 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 426 427 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 428 429 udelay(10000); 430 431 clk = SYSCTL_PEREN | SYSCTL_CKEN; 432 433 esdhc_setbits32(®s->sysctl, clk); 434 } 435 436 static void esdhc_set_ios(struct mmc *mmc) 437 { 438 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 439 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 440 441 /* Set the clock speed */ 442 set_sysctl(mmc, mmc->clock); 443 444 /* Set the bus width */ 445 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 446 447 if (mmc->bus_width == 4) 448 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 449 else if (mmc->bus_width == 8) 450 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 451 452 } 453 454 static int esdhc_init(struct mmc *mmc) 455 { 456 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 457 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 458 int timeout = 1000; 459 460 /* Reset the entire host controller */ 461 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 462 463 /* Wait until the controller is available */ 464 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 465 udelay(1000); 466 467 /* Enable cache snooping */ 468 if (cfg && !cfg->no_snoop) 469 esdhc_write32(®s->scr, 0x00000040); 470 471 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 472 473 /* Set the initial clock speed */ 474 mmc_set_clock(mmc, 400000); 475 476 /* Disable the BRR and BWR bits in IRQSTAT */ 477 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 478 479 /* Put the PROCTL reg back to the default */ 480 esdhc_write32(®s->proctl, PROCTL_INIT); 481 482 /* Set timout to the maximum value */ 483 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 484 485 return 0; 486 } 487 488 static int esdhc_getcd(struct mmc *mmc) 489 { 490 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 491 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 492 int timeout = 1000; 493 494 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 495 udelay(1000); 496 497 return timeout > 0; 498 } 499 500 static void esdhc_reset(struct fsl_esdhc *regs) 501 { 502 unsigned long timeout = 100; /* wait max 100 ms */ 503 504 /* reset the controller */ 505 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 506 507 /* hardware clears the bit when it is done */ 508 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 509 udelay(1000); 510 if (!timeout) 511 printf("MMC/SD: Reset never completed.\n"); 512 } 513 514 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 515 { 516 struct fsl_esdhc *regs; 517 struct mmc *mmc; 518 u32 caps, voltage_caps; 519 520 if (!cfg) 521 return -1; 522 523 mmc = malloc(sizeof(struct mmc)); 524 525 sprintf(mmc->name, "FSL_SDHC"); 526 regs = (struct fsl_esdhc *)cfg->esdhc_base; 527 528 /* First reset the eSDHC controller */ 529 esdhc_reset(regs); 530 531 mmc->priv = cfg; 532 mmc->send_cmd = esdhc_send_cmd; 533 mmc->set_ios = esdhc_set_ios; 534 mmc->init = esdhc_init; 535 mmc->getcd = esdhc_getcd; 536 537 voltage_caps = 0; 538 caps = regs->hostcapblt; 539 540 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 541 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 542 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 543 #endif 544 if (caps & ESDHC_HOSTCAPBLT_VS18) 545 voltage_caps |= MMC_VDD_165_195; 546 if (caps & ESDHC_HOSTCAPBLT_VS30) 547 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 548 if (caps & ESDHC_HOSTCAPBLT_VS33) 549 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 550 551 #ifdef CONFIG_SYS_SD_VOLTAGE 552 mmc->voltages = CONFIG_SYS_SD_VOLTAGE; 553 #else 554 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 555 #endif 556 if ((mmc->voltages & voltage_caps) == 0) { 557 printf("voltage not supported by controller\n"); 558 return -1; 559 } 560 561 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 562 563 if (caps & ESDHC_HOSTCAPBLT_HSS) 564 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 565 566 mmc->f_min = 400000; 567 mmc->f_max = MIN(gd->sdhc_clk, 52000000); 568 569 mmc->b_max = 0; 570 mmc_register(mmc); 571 572 return 0; 573 } 574 575 int fsl_esdhc_mmc_init(bd_t *bis) 576 { 577 struct fsl_esdhc_cfg *cfg; 578 579 cfg = malloc(sizeof(struct fsl_esdhc_cfg)); 580 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); 581 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 582 return fsl_esdhc_initialize(bis, cfg); 583 } 584 585 #ifdef CONFIG_OF_LIBFDT 586 void fdt_fixup_esdhc(void *blob, bd_t *bd) 587 { 588 const char *compat = "fsl,esdhc"; 589 590 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 591 if (!hwconfig("esdhc")) { 592 do_fixup_by_compat(blob, compat, "status", "disabled", 593 8 + 1, 1); 594 return; 595 } 596 #endif 597 598 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 599 gd->sdhc_clk, 1); 600 601 do_fixup_by_compat(blob, compat, "status", "okay", 602 4 + 1, 1); 603 } 604 #endif 605