1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 char reserved1[8]; 62 uint fevt; 63 char reserved2[168]; 64 uint hostver; 65 char reserved3[780]; 66 uint scr; 67 }; 68 69 /* Return the XFERTYP flags for a given command and data packet */ 70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 71 { 72 uint xfertyp = 0; 73 74 if (data) { 75 xfertyp |= XFERTYP_DPSEL; 76 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 77 xfertyp |= XFERTYP_DMAEN; 78 #endif 79 if (data->blocks > 1) { 80 xfertyp |= XFERTYP_MSBSEL; 81 xfertyp |= XFERTYP_BCEN; 82 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 83 xfertyp |= XFERTYP_AC12EN; 84 #endif 85 } 86 87 if (data->flags & MMC_DATA_READ) 88 xfertyp |= XFERTYP_DTDSEL; 89 } 90 91 if (cmd->resp_type & MMC_RSP_CRC) 92 xfertyp |= XFERTYP_CCCEN; 93 if (cmd->resp_type & MMC_RSP_OPCODE) 94 xfertyp |= XFERTYP_CICEN; 95 if (cmd->resp_type & MMC_RSP_136) 96 xfertyp |= XFERTYP_RSPTYP_136; 97 else if (cmd->resp_type & MMC_RSP_BUSY) 98 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 99 else if (cmd->resp_type & MMC_RSP_PRESENT) 100 xfertyp |= XFERTYP_RSPTYP_48; 101 102 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 103 } 104 105 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 106 /* 107 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 108 */ 109 static void 110 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 111 { 112 struct fsl_esdhc *regs = mmc->priv; 113 uint blocks; 114 char *buffer; 115 uint databuf; 116 uint size; 117 uint irqstat; 118 uint timeout; 119 120 if (data->flags & MMC_DATA_READ) { 121 blocks = data->blocks; 122 buffer = data->dest; 123 while (blocks) { 124 timeout = PIO_TIMEOUT; 125 size = data->blocksize; 126 irqstat = esdhc_read32(®s->irqstat); 127 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 128 && --timeout); 129 if (timeout <= 0) { 130 printf("\nData Read Failed in PIO Mode."); 131 return; 132 } 133 while (size && (!(irqstat & IRQSTAT_TC))) { 134 udelay(100); /* Wait before last byte transfer complete */ 135 irqstat = esdhc_read32(®s->irqstat); 136 databuf = in_le32(®s->datport); 137 *((uint *)buffer) = databuf; 138 buffer += 4; 139 size -= 4; 140 } 141 blocks--; 142 } 143 } else { 144 blocks = data->blocks; 145 buffer = (char *)data->src; 146 while (blocks) { 147 timeout = PIO_TIMEOUT; 148 size = data->blocksize; 149 irqstat = esdhc_read32(®s->irqstat); 150 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 151 && --timeout); 152 if (timeout <= 0) { 153 printf("\nData Write Failed in PIO Mode."); 154 return; 155 } 156 while (size && (!(irqstat & IRQSTAT_TC))) { 157 udelay(100); /* Wait before last byte transfer complete */ 158 databuf = *((uint *)buffer); 159 buffer += 4; 160 size -= 4; 161 irqstat = esdhc_read32(®s->irqstat); 162 out_le32(®s->datport, databuf); 163 } 164 blocks--; 165 } 166 } 167 } 168 #endif 169 170 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 171 { 172 int timeout; 173 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 174 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 175 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 176 uint wml_value; 177 178 wml_value = data->blocksize/4; 179 180 if (data->flags & MMC_DATA_READ) { 181 if (wml_value > 0x10) 182 wml_value = 0x10; 183 184 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 185 esdhc_write32(®s->dsaddr, (u32)data->dest); 186 } else { 187 if (wml_value > 0x80) 188 wml_value = 0x80; 189 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 190 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 191 return TIMEOUT; 192 } 193 194 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 195 wml_value << 16); 196 esdhc_write32(®s->dsaddr, (u32)data->src); 197 } 198 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 199 if (!(data->flags & MMC_DATA_READ)) { 200 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 201 printf("\nThe SD card is locked. " 202 "Can not write to a locked card.\n\n"); 203 return TIMEOUT; 204 } 205 esdhc_write32(®s->dsaddr, (u32)data->src); 206 } else 207 esdhc_write32(®s->dsaddr, (u32)data->dest); 208 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 209 210 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 211 212 /* Calculate the timeout period for data transactions */ 213 /* 214 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 215 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 216 * So, Number of SD Clock cycles for 0.25sec should be minimum 217 * (SD Clock/sec * 0.25 sec) SD Clock cycles 218 * = (mmc->tran_speed * 1/4) SD Clock cycles 219 * As 1) >= 2) 220 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 221 * Taking log2 both the sides 222 * => timeout + 13 >= log2(mmc->tran_speed/4) 223 * Rounding up to next power of 2 224 * => timeout + 13 = log2(mmc->tran_speed/4) + 1 225 * => timeout + 13 = fls(mmc->tran_speed/4) 226 */ 227 timeout = fls(mmc->tran_speed/4); 228 timeout -= 13; 229 230 if (timeout > 14) 231 timeout = 14; 232 233 if (timeout < 0) 234 timeout = 0; 235 236 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 237 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 238 timeout++; 239 #endif 240 241 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 242 243 return 0; 244 } 245 246 247 /* 248 * Sends a command out on the bus. Takes the mmc pointer, 249 * a command pointer, and an optional data pointer. 250 */ 251 static int 252 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 253 { 254 uint xfertyp; 255 uint irqstat; 256 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 257 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 258 259 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 260 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 261 return 0; 262 #endif 263 264 esdhc_write32(®s->irqstat, -1); 265 266 sync(); 267 268 /* Wait for the bus to be idle */ 269 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 270 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 271 ; 272 273 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 274 ; 275 276 /* Wait at least 8 SD clock cycles before the next command */ 277 /* 278 * Note: This is way more than 8 cycles, but 1ms seems to 279 * resolve timing issues with some cards 280 */ 281 udelay(1000); 282 283 /* Set up for a data transfer if we have one */ 284 if (data) { 285 int err; 286 287 err = esdhc_setup_data(mmc, data); 288 if(err) 289 return err; 290 } 291 292 /* Figure out the transfer arguments */ 293 xfertyp = esdhc_xfertyp(cmd, data); 294 295 /* Send the command */ 296 esdhc_write32(®s->cmdarg, cmd->cmdarg); 297 esdhc_write32(®s->xfertyp, xfertyp); 298 299 /* Wait for the command to complete */ 300 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) 301 ; 302 303 irqstat = esdhc_read32(®s->irqstat); 304 esdhc_write32(®s->irqstat, irqstat); 305 306 if (irqstat & CMD_ERR) 307 return COMM_ERR; 308 309 if (irqstat & IRQSTAT_CTOE) 310 return TIMEOUT; 311 312 /* Copy the response to the response buffer */ 313 if (cmd->resp_type & MMC_RSP_136) { 314 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 315 316 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 317 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 318 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 319 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 320 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 321 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 322 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 323 cmd->response[3] = (cmdrsp0 << 8); 324 } else 325 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 326 327 /* Wait until all of the blocks are transferred */ 328 if (data) { 329 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 330 esdhc_pio_read_write(mmc, data); 331 #else 332 do { 333 irqstat = esdhc_read32(®s->irqstat); 334 335 if (irqstat & DATA_ERR) 336 return COMM_ERR; 337 338 if (irqstat & IRQSTAT_DTOE) 339 return TIMEOUT; 340 } while (!(irqstat & IRQSTAT_TC) && 341 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); 342 #endif 343 } 344 345 esdhc_write32(®s->irqstat, -1); 346 347 return 0; 348 } 349 350 void set_sysctl(struct mmc *mmc, uint clock) 351 { 352 int sdhc_clk = gd->sdhc_clk; 353 int div, pre_div; 354 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 355 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 356 uint clk; 357 358 if (clock < mmc->f_min) 359 clock = mmc->f_min; 360 361 if (sdhc_clk / 16 > clock) { 362 for (pre_div = 2; pre_div < 256; pre_div *= 2) 363 if ((sdhc_clk / pre_div) <= (clock * 16)) 364 break; 365 } else 366 pre_div = 2; 367 368 for (div = 1; div <= 16; div++) 369 if ((sdhc_clk / (div * pre_div)) <= clock) 370 break; 371 372 pre_div >>= 1; 373 div -= 1; 374 375 clk = (pre_div << 8) | (div << 4); 376 377 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 378 379 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 380 381 udelay(10000); 382 383 clk = SYSCTL_PEREN | SYSCTL_CKEN; 384 385 esdhc_setbits32(®s->sysctl, clk); 386 } 387 388 static void esdhc_set_ios(struct mmc *mmc) 389 { 390 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 391 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 392 393 /* Set the clock speed */ 394 set_sysctl(mmc, mmc->clock); 395 396 /* Set the bus width */ 397 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 398 399 if (mmc->bus_width == 4) 400 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 401 else if (mmc->bus_width == 8) 402 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 403 404 } 405 406 static int esdhc_init(struct mmc *mmc) 407 { 408 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 409 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 410 int timeout = 1000; 411 int ret = 0; 412 u8 card_absent; 413 414 /* Reset the entire host controller */ 415 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 416 417 /* Wait until the controller is available */ 418 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 419 udelay(1000); 420 421 /* Enable cache snooping */ 422 if (cfg && !cfg->no_snoop) 423 esdhc_write32(®s->scr, 0x00000040); 424 425 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 426 427 /* Set the initial clock speed */ 428 mmc_set_clock(mmc, 400000); 429 430 /* Disable the BRR and BWR bits in IRQSTAT */ 431 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 432 433 /* Put the PROCTL reg back to the default */ 434 esdhc_write32(®s->proctl, PROCTL_INIT); 435 436 /* Set timout to the maximum value */ 437 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 438 439 /* Check if there is a callback for detecting the card */ 440 if (board_mmc_getcd(&card_absent, mmc)) { 441 timeout = 1000; 442 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && 443 --timeout) 444 udelay(1000); 445 446 if (timeout <= 0) 447 ret = NO_CARD_ERR; 448 } else { 449 if (card_absent) 450 ret = NO_CARD_ERR; 451 } 452 453 return ret; 454 } 455 456 static void esdhc_reset(struct fsl_esdhc *regs) 457 { 458 unsigned long timeout = 100; /* wait max 100 ms */ 459 460 /* reset the controller */ 461 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 462 463 /* hardware clears the bit when it is done */ 464 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 465 udelay(1000); 466 if (!timeout) 467 printf("MMC/SD: Reset never completed.\n"); 468 } 469 470 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 471 { 472 struct fsl_esdhc *regs; 473 struct mmc *mmc; 474 u32 caps, voltage_caps; 475 476 if (!cfg) 477 return -1; 478 479 mmc = malloc(sizeof(struct mmc)); 480 481 sprintf(mmc->name, "FSL_ESDHC"); 482 regs = (struct fsl_esdhc *)cfg->esdhc_base; 483 484 /* First reset the eSDHC controller */ 485 esdhc_reset(regs); 486 487 mmc->priv = cfg; 488 mmc->send_cmd = esdhc_send_cmd; 489 mmc->set_ios = esdhc_set_ios; 490 mmc->init = esdhc_init; 491 492 voltage_caps = 0; 493 caps = regs->hostcapblt; 494 495 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 496 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 497 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 498 #endif 499 if (caps & ESDHC_HOSTCAPBLT_VS18) 500 voltage_caps |= MMC_VDD_165_195; 501 if (caps & ESDHC_HOSTCAPBLT_VS30) 502 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 503 if (caps & ESDHC_HOSTCAPBLT_VS33) 504 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 505 506 #ifdef CONFIG_SYS_SD_VOLTAGE 507 mmc->voltages = CONFIG_SYS_SD_VOLTAGE; 508 #else 509 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 510 #endif 511 if ((mmc->voltages & voltage_caps) == 0) { 512 printf("voltage not supported by controller\n"); 513 return -1; 514 } 515 516 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 517 518 if (caps & ESDHC_HOSTCAPBLT_HSS) 519 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 520 521 mmc->f_min = 400000; 522 mmc->f_max = MIN(gd->sdhc_clk, 52000000); 523 524 mmc_register(mmc); 525 526 return 0; 527 } 528 529 int fsl_esdhc_mmc_init(bd_t *bis) 530 { 531 struct fsl_esdhc_cfg *cfg; 532 533 cfg = malloc(sizeof(struct fsl_esdhc_cfg)); 534 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); 535 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 536 return fsl_esdhc_initialize(bis, cfg); 537 } 538 539 #ifdef CONFIG_OF_LIBFDT 540 void fdt_fixup_esdhc(void *blob, bd_t *bd) 541 { 542 const char *compat = "fsl,esdhc"; 543 544 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 545 if (!hwconfig("esdhc")) { 546 do_fixup_by_compat(blob, compat, "status", "disabled", 547 8 + 1, 1); 548 return; 549 } 550 #endif 551 552 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 553 gd->sdhc_clk, 1); 554 555 do_fixup_by_compat(blob, compat, "status", "okay", 556 4 + 1, 1); 557 } 558 #endif 559