xref: /openbmc/u-boot/drivers/mmc/fsl_esdhc.c (revision 314284b1)
1 /*
2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
3  * Andy Fleming
4  *
5  * Based vaguely on the pxa mmc code:
6  * (C) Copyright 2003
7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 #include <config.h>
29 #include <common.h>
30 #include <command.h>
31 #include <hwconfig.h>
32 #include <mmc.h>
33 #include <part.h>
34 #include <malloc.h>
35 #include <mmc.h>
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
38 #include <asm/io.h>
39 
40 DECLARE_GLOBAL_DATA_PTR;
41 
42 struct fsl_esdhc {
43 	uint	dsaddr;
44 	uint	blkattr;
45 	uint	cmdarg;
46 	uint	xfertyp;
47 	uint	cmdrsp0;
48 	uint	cmdrsp1;
49 	uint	cmdrsp2;
50 	uint	cmdrsp3;
51 	uint	datport;
52 	uint	prsstat;
53 	uint	proctl;
54 	uint	sysctl;
55 	uint	irqstat;
56 	uint	irqstaten;
57 	uint	irqsigen;
58 	uint	autoc12err;
59 	uint	hostcapblt;
60 	uint	wml;
61 	uint    mixctrl;
62 	char    reserved1[4];
63 	uint	fevt;
64 	char	reserved2[168];
65 	uint	hostver;
66 	char	reserved3[780];
67 	uint	scr;
68 };
69 
70 /* Return the XFERTYP flags for a given command and data packet */
71 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
72 {
73 	uint xfertyp = 0;
74 
75 	if (data) {
76 		xfertyp |= XFERTYP_DPSEL;
77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
78 		xfertyp |= XFERTYP_DMAEN;
79 #endif
80 		if (data->blocks > 1) {
81 			xfertyp |= XFERTYP_MSBSEL;
82 			xfertyp |= XFERTYP_BCEN;
83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
84 			xfertyp |= XFERTYP_AC12EN;
85 #endif
86 		}
87 
88 		if (data->flags & MMC_DATA_READ)
89 			xfertyp |= XFERTYP_DTDSEL;
90 	}
91 
92 	if (cmd->resp_type & MMC_RSP_CRC)
93 		xfertyp |= XFERTYP_CCCEN;
94 	if (cmd->resp_type & MMC_RSP_OPCODE)
95 		xfertyp |= XFERTYP_CICEN;
96 	if (cmd->resp_type & MMC_RSP_136)
97 		xfertyp |= XFERTYP_RSPTYP_136;
98 	else if (cmd->resp_type & MMC_RSP_BUSY)
99 		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
100 	else if (cmd->resp_type & MMC_RSP_PRESENT)
101 		xfertyp |= XFERTYP_RSPTYP_48;
102 
103 #ifdef CONFIG_MX53
104 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
105 		xfertyp |= XFERTYP_CMDTYP_ABORT;
106 #endif
107 	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
108 }
109 
110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
111 /*
112  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
113  */
114 static void
115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
116 {
117 	struct fsl_esdhc *regs = mmc->priv;
118 	uint blocks;
119 	char *buffer;
120 	uint databuf;
121 	uint size;
122 	uint irqstat;
123 	uint timeout;
124 
125 	if (data->flags & MMC_DATA_READ) {
126 		blocks = data->blocks;
127 		buffer = data->dest;
128 		while (blocks) {
129 			timeout = PIO_TIMEOUT;
130 			size = data->blocksize;
131 			irqstat = esdhc_read32(&regs->irqstat);
132 			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
133 				&& --timeout);
134 			if (timeout <= 0) {
135 				printf("\nData Read Failed in PIO Mode.");
136 				return;
137 			}
138 			while (size && (!(irqstat & IRQSTAT_TC))) {
139 				udelay(100); /* Wait before last byte transfer complete */
140 				irqstat = esdhc_read32(&regs->irqstat);
141 				databuf = in_le32(&regs->datport);
142 				*((uint *)buffer) = databuf;
143 				buffer += 4;
144 				size -= 4;
145 			}
146 			blocks--;
147 		}
148 	} else {
149 		blocks = data->blocks;
150 		buffer = (char *)data->src;
151 		while (blocks) {
152 			timeout = PIO_TIMEOUT;
153 			size = data->blocksize;
154 			irqstat = esdhc_read32(&regs->irqstat);
155 			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
156 				&& --timeout);
157 			if (timeout <= 0) {
158 				printf("\nData Write Failed in PIO Mode.");
159 				return;
160 			}
161 			while (size && (!(irqstat & IRQSTAT_TC))) {
162 				udelay(100); /* Wait before last byte transfer complete */
163 				databuf = *((uint *)buffer);
164 				buffer += 4;
165 				size -= 4;
166 				irqstat = esdhc_read32(&regs->irqstat);
167 				out_le32(&regs->datport, databuf);
168 			}
169 			blocks--;
170 		}
171 	}
172 }
173 #endif
174 
175 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
176 {
177 	int timeout;
178 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
179 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
180 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
181 	uint wml_value;
182 
183 	wml_value = data->blocksize/4;
184 
185 	if (data->flags & MMC_DATA_READ) {
186 		if (wml_value > WML_RD_WML_MAX)
187 			wml_value = WML_RD_WML_MAX_VAL;
188 
189 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
190 		esdhc_write32(&regs->dsaddr, (u32)data->dest);
191 	} else {
192 		if (wml_value > WML_WR_WML_MAX)
193 			wml_value = WML_WR_WML_MAX_VAL;
194 		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
195 			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
196 			return TIMEOUT;
197 		}
198 
199 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
200 					wml_value << 16);
201 		esdhc_write32(&regs->dsaddr, (u32)data->src);
202 	}
203 #else	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */
204 	if (!(data->flags & MMC_DATA_READ)) {
205 		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
206 			printf("\nThe SD card is locked. "
207 				"Can not write to a locked card.\n\n");
208 			return TIMEOUT;
209 		}
210 		esdhc_write32(&regs->dsaddr, (u32)data->src);
211 	} else
212 		esdhc_write32(&regs->dsaddr, (u32)data->dest);
213 #endif	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */
214 
215 	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
216 
217 	/* Calculate the timeout period for data transactions */
218 	/*
219 	 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
220 	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
221 	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
222 	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
223 	 *		= (mmc->tran_speed * 1/4) SD Clock cycles
224 	 * As 1) >=  2)
225 	 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
226 	 * Taking log2 both the sides
227 	 * => timeout + 13 >= log2(mmc->tran_speed/4)
228 	 * Rounding up to next power of 2
229 	 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
230 	 * => timeout + 13 = fls(mmc->tran_speed/4)
231 	 */
232 	timeout = fls(mmc->tran_speed/4);
233 	timeout -= 13;
234 
235 	if (timeout > 14)
236 		timeout = 14;
237 
238 	if (timeout < 0)
239 		timeout = 0;
240 
241 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
242 	if ((timeout == 4) || (timeout == 8) || (timeout == 12))
243 		timeout++;
244 #endif
245 
246 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
247 
248 	return 0;
249 }
250 
251 
252 /*
253  * Sends a command out on the bus.  Takes the mmc pointer,
254  * a command pointer, and an optional data pointer.
255  */
256 static int
257 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
258 {
259 	uint	xfertyp;
260 	uint	irqstat;
261 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
262 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
263 
264 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
265 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
266 		return 0;
267 #endif
268 
269 	esdhc_write32(&regs->irqstat, -1);
270 
271 	sync();
272 
273 	/* Wait for the bus to be idle */
274 	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
275 			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
276 		;
277 
278 	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
279 		;
280 
281 	/* Wait at least 8 SD clock cycles before the next command */
282 	/*
283 	 * Note: This is way more than 8 cycles, but 1ms seems to
284 	 * resolve timing issues with some cards
285 	 */
286 	udelay(1000);
287 
288 	/* Set up for a data transfer if we have one */
289 	if (data) {
290 		int err;
291 
292 		err = esdhc_setup_data(mmc, data);
293 		if(err)
294 			return err;
295 	}
296 
297 	/* Figure out the transfer arguments */
298 	xfertyp = esdhc_xfertyp(cmd, data);
299 
300 	/* Send the command */
301 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
302 #if defined(CONFIG_FSL_USDHC)
303 	esdhc_write32(&regs->mixctrl,
304 	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
305 	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
306 #else
307 	esdhc_write32(&regs->xfertyp, xfertyp);
308 #endif
309 	/* Wait for the command to complete */
310 	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
311 		;
312 
313 	irqstat = esdhc_read32(&regs->irqstat);
314 	esdhc_write32(&regs->irqstat, irqstat);
315 
316 	if (irqstat & CMD_ERR)
317 		return COMM_ERR;
318 
319 	if (irqstat & IRQSTAT_CTOE)
320 		return TIMEOUT;
321 
322 	/* Copy the response to the response buffer */
323 	if (cmd->resp_type & MMC_RSP_136) {
324 		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
325 
326 		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
327 		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
328 		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
329 		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
330 		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
331 		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
332 		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
333 		cmd->response[3] = (cmdrsp0 << 8);
334 	} else
335 		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
336 
337 	/* Wait until all of the blocks are transferred */
338 	if (data) {
339 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
340 		esdhc_pio_read_write(mmc, data);
341 #else
342 		do {
343 			irqstat = esdhc_read32(&regs->irqstat);
344 
345 			if (irqstat & IRQSTAT_DTOE)
346 				return TIMEOUT;
347 
348 			if (irqstat & DATA_ERR)
349 				return COMM_ERR;
350 		} while (!(irqstat & IRQSTAT_TC) &&
351 				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
352 #endif
353 	}
354 
355 	esdhc_write32(&regs->irqstat, -1);
356 
357 	return 0;
358 }
359 
360 void set_sysctl(struct mmc *mmc, uint clock)
361 {
362 	int sdhc_clk = gd->sdhc_clk;
363 	int div, pre_div;
364 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
365 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
366 	uint clk;
367 
368 	if (clock < mmc->f_min)
369 		clock = mmc->f_min;
370 
371 	if (sdhc_clk / 16 > clock) {
372 		for (pre_div = 2; pre_div < 256; pre_div *= 2)
373 			if ((sdhc_clk / pre_div) <= (clock * 16))
374 				break;
375 	} else
376 		pre_div = 2;
377 
378 	for (div = 1; div <= 16; div++)
379 		if ((sdhc_clk / (div * pre_div)) <= clock)
380 			break;
381 
382 	pre_div >>= 1;
383 	div -= 1;
384 
385 	clk = (pre_div << 8) | (div << 4);
386 
387 	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
388 
389 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
390 
391 	udelay(10000);
392 
393 	clk = SYSCTL_PEREN | SYSCTL_CKEN;
394 
395 	esdhc_setbits32(&regs->sysctl, clk);
396 }
397 
398 static void esdhc_set_ios(struct mmc *mmc)
399 {
400 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
401 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
402 
403 	/* Set the clock speed */
404 	set_sysctl(mmc, mmc->clock);
405 
406 	/* Set the bus width */
407 	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
408 
409 	if (mmc->bus_width == 4)
410 		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
411 	else if (mmc->bus_width == 8)
412 		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
413 
414 }
415 
416 static int esdhc_init(struct mmc *mmc)
417 {
418 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
419 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
420 	int timeout = 1000;
421 	int ret = 0;
422 
423 	/* Reset the entire host controller */
424 	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
425 
426 	/* Wait until the controller is available */
427 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
428 		udelay(1000);
429 
430 	/* Enable cache snooping */
431 	if (cfg && !cfg->no_snoop)
432 		esdhc_write32(&regs->scr, 0x00000040);
433 
434 	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
435 
436 	/* Set the initial clock speed */
437 	mmc_set_clock(mmc, 400000);
438 
439 	/* Disable the BRR and BWR bits in IRQSTAT */
440 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
441 
442 	/* Put the PROCTL reg back to the default */
443 	esdhc_write32(&regs->proctl, PROCTL_INIT);
444 
445 	/* Set timout to the maximum value */
446 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
447 
448 	/* Check if there is a callback for detecting the card */
449 	ret = board_mmc_getcd(mmc);
450 	if (ret < 0) {
451 		timeout = 1000;
452 		while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) &&
453 				--timeout)
454 			udelay(1000);
455 
456 		if (timeout <= 0)
457 			ret = NO_CARD_ERR;
458 	} else {
459 		if (ret == 0)
460 			ret = NO_CARD_ERR;
461 		else
462 			ret = 0;
463 	}
464 
465 	return ret;
466 }
467 
468 static void esdhc_reset(struct fsl_esdhc *regs)
469 {
470 	unsigned long timeout = 100; /* wait max 100 ms */
471 
472 	/* reset the controller */
473 	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
474 
475 	/* hardware clears the bit when it is done */
476 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
477 		udelay(1000);
478 	if (!timeout)
479 		printf("MMC/SD: Reset never completed.\n");
480 }
481 
482 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
483 {
484 	struct fsl_esdhc *regs;
485 	struct mmc *mmc;
486 	u32 caps, voltage_caps;
487 
488 	if (!cfg)
489 		return -1;
490 
491 	mmc = malloc(sizeof(struct mmc));
492 
493 	sprintf(mmc->name, "FSL_SDHC");
494 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
495 
496 	/* First reset the eSDHC controller */
497 	esdhc_reset(regs);
498 
499 	mmc->priv = cfg;
500 	mmc->send_cmd = esdhc_send_cmd;
501 	mmc->set_ios = esdhc_set_ios;
502 	mmc->init = esdhc_init;
503 
504 	voltage_caps = 0;
505 	caps = regs->hostcapblt;
506 
507 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
508 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
509 			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
510 #endif
511 	if (caps & ESDHC_HOSTCAPBLT_VS18)
512 		voltage_caps |= MMC_VDD_165_195;
513 	if (caps & ESDHC_HOSTCAPBLT_VS30)
514 		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
515 	if (caps & ESDHC_HOSTCAPBLT_VS33)
516 		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
517 
518 #ifdef CONFIG_SYS_SD_VOLTAGE
519 	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
520 #else
521 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
522 #endif
523 	if ((mmc->voltages & voltage_caps) == 0) {
524 		printf("voltage not supported by controller\n");
525 		return -1;
526 	}
527 
528 	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
529 
530 	if (caps & ESDHC_HOSTCAPBLT_HSS)
531 		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
532 
533 	mmc->f_min = 400000;
534 	mmc->f_max = MIN(gd->sdhc_clk, 52000000);
535 
536 	mmc->b_max = 0;
537 	mmc_register(mmc);
538 
539 	return 0;
540 }
541 
542 int fsl_esdhc_mmc_init(bd_t *bis)
543 {
544 	struct fsl_esdhc_cfg *cfg;
545 
546 	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
547 	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
548 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
549 	return fsl_esdhc_initialize(bis, cfg);
550 }
551 
552 #ifdef CONFIG_OF_LIBFDT
553 void fdt_fixup_esdhc(void *blob, bd_t *bd)
554 {
555 	const char *compat = "fsl,esdhc";
556 
557 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
558 	if (!hwconfig("esdhc")) {
559 		do_fixup_by_compat(blob, compat, "status", "disabled",
560 				8 + 1, 1);
561 		return;
562 	}
563 #endif
564 
565 	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
566 			       gd->sdhc_clk, 1);
567 
568 	do_fixup_by_compat(blob, compat, "status", "okay",
569 			   4 + 1, 1);
570 }
571 #endif
572