1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 uint mixctrl; 62 char reserved1[4]; 63 uint fevt; 64 char reserved2[168]; 65 uint hostver; 66 char reserved3[780]; 67 uint scr; 68 }; 69 70 /* Return the XFERTYP flags for a given command and data packet */ 71 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 72 { 73 uint xfertyp = 0; 74 75 if (data) { 76 xfertyp |= XFERTYP_DPSEL; 77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 78 xfertyp |= XFERTYP_DMAEN; 79 #endif 80 if (data->blocks > 1) { 81 xfertyp |= XFERTYP_MSBSEL; 82 xfertyp |= XFERTYP_BCEN; 83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 84 xfertyp |= XFERTYP_AC12EN; 85 #endif 86 } 87 88 if (data->flags & MMC_DATA_READ) 89 xfertyp |= XFERTYP_DTDSEL; 90 } 91 92 if (cmd->resp_type & MMC_RSP_CRC) 93 xfertyp |= XFERTYP_CCCEN; 94 if (cmd->resp_type & MMC_RSP_OPCODE) 95 xfertyp |= XFERTYP_CICEN; 96 if (cmd->resp_type & MMC_RSP_136) 97 xfertyp |= XFERTYP_RSPTYP_136; 98 else if (cmd->resp_type & MMC_RSP_BUSY) 99 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 100 else if (cmd->resp_type & MMC_RSP_PRESENT) 101 xfertyp |= XFERTYP_RSPTYP_48; 102 103 #ifdef CONFIG_MX53 104 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 105 xfertyp |= XFERTYP_CMDTYP_ABORT; 106 #endif 107 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 108 } 109 110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 111 /* 112 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 113 */ 114 static void 115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 116 { 117 struct fsl_esdhc_cfg *cfg = mmc->priv; 118 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 119 uint blocks; 120 char *buffer; 121 uint databuf; 122 uint size; 123 uint irqstat; 124 uint timeout; 125 126 if (data->flags & MMC_DATA_READ) { 127 blocks = data->blocks; 128 buffer = data->dest; 129 while (blocks) { 130 timeout = PIO_TIMEOUT; 131 size = data->blocksize; 132 irqstat = esdhc_read32(®s->irqstat); 133 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 134 && --timeout); 135 if (timeout <= 0) { 136 printf("\nData Read Failed in PIO Mode."); 137 return; 138 } 139 while (size && (!(irqstat & IRQSTAT_TC))) { 140 udelay(100); /* Wait before last byte transfer complete */ 141 irqstat = esdhc_read32(®s->irqstat); 142 databuf = in_le32(®s->datport); 143 *((uint *)buffer) = databuf; 144 buffer += 4; 145 size -= 4; 146 } 147 blocks--; 148 } 149 } else { 150 blocks = data->blocks; 151 buffer = (char *)data->src; 152 while (blocks) { 153 timeout = PIO_TIMEOUT; 154 size = data->blocksize; 155 irqstat = esdhc_read32(®s->irqstat); 156 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 157 && --timeout); 158 if (timeout <= 0) { 159 printf("\nData Write Failed in PIO Mode."); 160 return; 161 } 162 while (size && (!(irqstat & IRQSTAT_TC))) { 163 udelay(100); /* Wait before last byte transfer complete */ 164 databuf = *((uint *)buffer); 165 buffer += 4; 166 size -= 4; 167 irqstat = esdhc_read32(®s->irqstat); 168 out_le32(®s->datport, databuf); 169 } 170 blocks--; 171 } 172 } 173 } 174 #endif 175 176 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 177 { 178 int timeout; 179 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 180 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 181 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 182 uint wml_value; 183 184 wml_value = data->blocksize/4; 185 186 if (data->flags & MMC_DATA_READ) { 187 if (wml_value > WML_RD_WML_MAX) 188 wml_value = WML_RD_WML_MAX_VAL; 189 190 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 191 esdhc_write32(®s->dsaddr, (u32)data->dest); 192 } else { 193 flush_dcache_range((ulong)data->src, 194 (ulong)data->src+data->blocks 195 *data->blocksize); 196 197 if (wml_value > WML_WR_WML_MAX) 198 wml_value = WML_WR_WML_MAX_VAL; 199 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 200 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 201 return TIMEOUT; 202 } 203 204 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 205 wml_value << 16); 206 esdhc_write32(®s->dsaddr, (u32)data->src); 207 } 208 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 209 if (!(data->flags & MMC_DATA_READ)) { 210 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 211 printf("\nThe SD card is locked. " 212 "Can not write to a locked card.\n\n"); 213 return TIMEOUT; 214 } 215 esdhc_write32(®s->dsaddr, (u32)data->src); 216 } else 217 esdhc_write32(®s->dsaddr, (u32)data->dest); 218 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 219 220 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 221 222 /* Calculate the timeout period for data transactions */ 223 /* 224 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 225 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 226 * So, Number of SD Clock cycles for 0.25sec should be minimum 227 * (SD Clock/sec * 0.25 sec) SD Clock cycles 228 * = (mmc->tran_speed * 1/4) SD Clock cycles 229 * As 1) >= 2) 230 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 231 * Taking log2 both the sides 232 * => timeout + 13 >= log2(mmc->tran_speed/4) 233 * Rounding up to next power of 2 234 * => timeout + 13 = log2(mmc->tran_speed/4) + 1 235 * => timeout + 13 = fls(mmc->tran_speed/4) 236 */ 237 timeout = fls(mmc->tran_speed/4); 238 timeout -= 13; 239 240 if (timeout > 14) 241 timeout = 14; 242 243 if (timeout < 0) 244 timeout = 0; 245 246 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 247 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 248 timeout++; 249 #endif 250 251 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 252 253 return 0; 254 } 255 256 static void check_and_invalidate_dcache_range 257 (struct mmc_cmd *cmd, 258 struct mmc_data *data) { 259 unsigned start = (unsigned)data->dest ; 260 unsigned size = roundup(ARCH_DMA_MINALIGN, 261 data->blocks*data->blocksize); 262 unsigned end = start+size ; 263 invalidate_dcache_range(start, end); 264 } 265 /* 266 * Sends a command out on the bus. Takes the mmc pointer, 267 * a command pointer, and an optional data pointer. 268 */ 269 static int 270 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 271 { 272 uint xfertyp; 273 uint irqstat; 274 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 275 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 276 277 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 278 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 279 return 0; 280 #endif 281 282 esdhc_write32(®s->irqstat, -1); 283 284 sync(); 285 286 /* Wait for the bus to be idle */ 287 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 288 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 289 ; 290 291 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 292 ; 293 294 /* Wait at least 8 SD clock cycles before the next command */ 295 /* 296 * Note: This is way more than 8 cycles, but 1ms seems to 297 * resolve timing issues with some cards 298 */ 299 udelay(1000); 300 301 /* Set up for a data transfer if we have one */ 302 if (data) { 303 int err; 304 305 err = esdhc_setup_data(mmc, data); 306 if(err) 307 return err; 308 } 309 310 /* Figure out the transfer arguments */ 311 xfertyp = esdhc_xfertyp(cmd, data); 312 313 /* Send the command */ 314 esdhc_write32(®s->cmdarg, cmd->cmdarg); 315 #if defined(CONFIG_FSL_USDHC) 316 esdhc_write32(®s->mixctrl, 317 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); 318 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 319 #else 320 esdhc_write32(®s->xfertyp, xfertyp); 321 #endif 322 323 /* Mask all irqs */ 324 esdhc_write32(®s->irqsigen, 0); 325 326 /* Wait for the command to complete */ 327 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 328 ; 329 330 irqstat = esdhc_read32(®s->irqstat); 331 esdhc_write32(®s->irqstat, irqstat); 332 333 /* Reset CMD and DATA portions on error */ 334 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { 335 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 336 SYSCTL_RSTC); 337 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 338 ; 339 340 if (data) { 341 esdhc_write32(®s->sysctl, 342 esdhc_read32(®s->sysctl) | 343 SYSCTL_RSTD); 344 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 345 ; 346 } 347 } 348 349 if (irqstat & CMD_ERR) 350 return COMM_ERR; 351 352 if (irqstat & IRQSTAT_CTOE) 353 return TIMEOUT; 354 355 /* Workaround for ESDHC errata ENGcm03648 */ 356 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 357 int timeout = 2500; 358 359 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 360 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 361 PRSSTAT_DAT0)) { 362 udelay(100); 363 timeout--; 364 } 365 366 if (timeout <= 0) { 367 printf("Timeout waiting for DAT0 to go high!\n"); 368 return TIMEOUT; 369 } 370 } 371 372 /* Copy the response to the response buffer */ 373 if (cmd->resp_type & MMC_RSP_136) { 374 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 375 376 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 377 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 378 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 379 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 380 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 381 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 382 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 383 cmd->response[3] = (cmdrsp0 << 8); 384 } else 385 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 386 387 /* Wait until all of the blocks are transferred */ 388 if (data) { 389 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 390 esdhc_pio_read_write(mmc, data); 391 #else 392 do { 393 irqstat = esdhc_read32(®s->irqstat); 394 395 if (irqstat & IRQSTAT_DTOE) 396 return TIMEOUT; 397 398 if (irqstat & DATA_ERR) 399 return COMM_ERR; 400 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 401 #endif 402 if (data->flags & MMC_DATA_READ) 403 check_and_invalidate_dcache_range(cmd, data); 404 } 405 406 esdhc_write32(®s->irqstat, -1); 407 408 return 0; 409 } 410 411 static void set_sysctl(struct mmc *mmc, uint clock) 412 { 413 int div, pre_div; 414 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 415 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 416 int sdhc_clk = cfg->sdhc_clk; 417 uint clk; 418 419 if (clock < mmc->f_min) 420 clock = mmc->f_min; 421 422 if (sdhc_clk / 16 > clock) { 423 for (pre_div = 2; pre_div < 256; pre_div *= 2) 424 if ((sdhc_clk / pre_div) <= (clock * 16)) 425 break; 426 } else 427 pre_div = 2; 428 429 for (div = 1; div <= 16; div++) 430 if ((sdhc_clk / (div * pre_div)) <= clock) 431 break; 432 433 pre_div >>= 1; 434 div -= 1; 435 436 clk = (pre_div << 8) | (div << 4); 437 438 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 439 440 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 441 442 udelay(10000); 443 444 clk = SYSCTL_PEREN | SYSCTL_CKEN; 445 446 esdhc_setbits32(®s->sysctl, clk); 447 } 448 449 static void esdhc_set_ios(struct mmc *mmc) 450 { 451 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 452 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 453 454 /* Set the clock speed */ 455 set_sysctl(mmc, mmc->clock); 456 457 /* Set the bus width */ 458 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 459 460 if (mmc->bus_width == 4) 461 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 462 else if (mmc->bus_width == 8) 463 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 464 465 } 466 467 static int esdhc_init(struct mmc *mmc) 468 { 469 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 470 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 471 int timeout = 1000; 472 473 /* Reset the entire host controller */ 474 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 475 476 /* Wait until the controller is available */ 477 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 478 udelay(1000); 479 480 #ifndef ARCH_MXC 481 /* Enable cache snooping */ 482 esdhc_write32(®s->scr, 0x00000040); 483 #endif 484 485 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 486 487 /* Set the initial clock speed */ 488 mmc_set_clock(mmc, 400000); 489 490 /* Disable the BRR and BWR bits in IRQSTAT */ 491 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 492 493 /* Put the PROCTL reg back to the default */ 494 esdhc_write32(®s->proctl, PROCTL_INIT); 495 496 /* Set timout to the maximum value */ 497 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 498 499 return 0; 500 } 501 502 static int esdhc_getcd(struct mmc *mmc) 503 { 504 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 505 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 506 int timeout = 1000; 507 508 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 509 udelay(1000); 510 511 return timeout > 0; 512 } 513 514 static void esdhc_reset(struct fsl_esdhc *regs) 515 { 516 unsigned long timeout = 100; /* wait max 100 ms */ 517 518 /* reset the controller */ 519 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 520 521 /* hardware clears the bit when it is done */ 522 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 523 udelay(1000); 524 if (!timeout) 525 printf("MMC/SD: Reset never completed.\n"); 526 } 527 528 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 529 { 530 struct fsl_esdhc *regs; 531 struct mmc *mmc; 532 u32 caps, voltage_caps; 533 534 if (!cfg) 535 return -1; 536 537 mmc = malloc(sizeof(struct mmc)); 538 539 sprintf(mmc->name, "FSL_SDHC"); 540 regs = (struct fsl_esdhc *)cfg->esdhc_base; 541 542 /* First reset the eSDHC controller */ 543 esdhc_reset(regs); 544 545 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 546 | SYSCTL_IPGEN | SYSCTL_CKEN); 547 548 mmc->priv = cfg; 549 mmc->send_cmd = esdhc_send_cmd; 550 mmc->set_ios = esdhc_set_ios; 551 mmc->init = esdhc_init; 552 mmc->getcd = esdhc_getcd; 553 mmc->getwp = NULL; 554 555 voltage_caps = 0; 556 caps = regs->hostcapblt; 557 558 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 559 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 560 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 561 #endif 562 if (caps & ESDHC_HOSTCAPBLT_VS18) 563 voltage_caps |= MMC_VDD_165_195; 564 if (caps & ESDHC_HOSTCAPBLT_VS30) 565 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 566 if (caps & ESDHC_HOSTCAPBLT_VS33) 567 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 568 569 #ifdef CONFIG_SYS_SD_VOLTAGE 570 mmc->voltages = CONFIG_SYS_SD_VOLTAGE; 571 #else 572 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 573 #endif 574 if ((mmc->voltages & voltage_caps) == 0) { 575 printf("voltage not supported by controller\n"); 576 return -1; 577 } 578 579 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; 580 581 if (cfg->max_bus_width > 0) { 582 if (cfg->max_bus_width < 8) 583 mmc->host_caps &= ~MMC_MODE_8BIT; 584 if (cfg->max_bus_width < 4) 585 mmc->host_caps &= ~MMC_MODE_4BIT; 586 } 587 588 if (caps & ESDHC_HOSTCAPBLT_HSS) 589 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 590 591 mmc->f_min = 400000; 592 mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); 593 594 mmc->b_max = 0; 595 mmc_register(mmc); 596 597 return 0; 598 } 599 600 int fsl_esdhc_mmc_init(bd_t *bis) 601 { 602 struct fsl_esdhc_cfg *cfg; 603 604 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 605 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 606 cfg->sdhc_clk = gd->arch.sdhc_clk; 607 return fsl_esdhc_initialize(bis, cfg); 608 } 609 610 #ifdef CONFIG_OF_LIBFDT 611 void fdt_fixup_esdhc(void *blob, bd_t *bd) 612 { 613 const char *compat = "fsl,esdhc"; 614 615 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 616 if (!hwconfig("esdhc")) { 617 do_fixup_by_compat(blob, compat, "status", "disabled", 618 8 + 1, 1); 619 return; 620 } 621 #endif 622 623 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 624 gd->arch.sdhc_clk, 1); 625 626 do_fixup_by_compat(blob, compat, "status", "okay", 627 4 + 1, 1); 628 } 629 #endif 630