1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <errno.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <part.h> 19 #include <malloc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 #include <dm.h> 24 #include <asm-generic/gpio.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 29 IRQSTATEN_CINT | \ 30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 33 IRQSTATEN_DINT) 34 35 struct fsl_esdhc { 36 uint dsaddr; /* SDMA system address register */ 37 uint blkattr; /* Block attributes register */ 38 uint cmdarg; /* Command argument register */ 39 uint xfertyp; /* Transfer type register */ 40 uint cmdrsp0; /* Command response 0 register */ 41 uint cmdrsp1; /* Command response 1 register */ 42 uint cmdrsp2; /* Command response 2 register */ 43 uint cmdrsp3; /* Command response 3 register */ 44 uint datport; /* Buffer data port register */ 45 uint prsstat; /* Present state register */ 46 uint proctl; /* Protocol control register */ 47 uint sysctl; /* System Control Register */ 48 uint irqstat; /* Interrupt status register */ 49 uint irqstaten; /* Interrupt status enable register */ 50 uint irqsigen; /* Interrupt signal enable register */ 51 uint autoc12err; /* Auto CMD error status register */ 52 uint hostcapblt; /* Host controller capabilities register */ 53 uint wml; /* Watermark level register */ 54 uint mixctrl; /* For USDHC */ 55 char reserved1[4]; /* reserved */ 56 uint fevt; /* Force event register */ 57 uint admaes; /* ADMA error status register */ 58 uint adsaddr; /* ADMA system address register */ 59 char reserved2[4]; 60 uint dllctrl; 61 uint dllstat; 62 uint clktunectrlstatus; 63 char reserved3[84]; 64 uint vendorspec; 65 uint mmcboot; 66 uint vendorspec2; 67 char reserved4[48]; 68 uint hostver; /* Host controller version register */ 69 char reserved5[4]; /* reserved */ 70 uint dmaerraddr; /* DMA error address register */ 71 char reserved6[4]; /* reserved */ 72 uint dmaerrattr; /* DMA error attribute register */ 73 char reserved7[4]; /* reserved */ 74 uint hostcapblt2; /* Host controller capabilities register 2 */ 75 char reserved8[8]; /* reserved */ 76 uint tcr; /* Tuning control register */ 77 char reserved9[28]; /* reserved */ 78 uint sddirctl; /* SD direction control register */ 79 char reserved10[712];/* reserved */ 80 uint scr; /* eSDHC control register */ 81 }; 82 83 /** 84 * struct fsl_esdhc_priv 85 * 86 * @esdhc_regs: registers of the sdhc controller 87 * @sdhc_clk: Current clk of the sdhc controller 88 * @bus_width: bus width, 1bit, 4bit or 8bit 89 * @cfg: mmc config 90 * @mmc: mmc 91 * Following is used when Driver Model is enabled for MMC 92 * @dev: pointer for the device 93 * @non_removable: 0: removable; 1: non-removable 94 * @wp_enable: 1: enable checking wp; 0: no check 95 * @cd_gpio: gpio for card detection 96 * @wp_gpio: gpio for write protection 97 */ 98 struct fsl_esdhc_priv { 99 struct fsl_esdhc *esdhc_regs; 100 unsigned int sdhc_clk; 101 unsigned int bus_width; 102 struct mmc_config cfg; 103 struct mmc *mmc; 104 struct udevice *dev; 105 int non_removable; 106 int wp_enable; 107 #ifdef CONFIG_DM_GPIO 108 struct gpio_desc cd_gpio; 109 struct gpio_desc wp_gpio; 110 #endif 111 }; 112 113 /* Return the XFERTYP flags for a given command and data packet */ 114 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 115 { 116 uint xfertyp = 0; 117 118 if (data) { 119 xfertyp |= XFERTYP_DPSEL; 120 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 121 xfertyp |= XFERTYP_DMAEN; 122 #endif 123 if (data->blocks > 1) { 124 xfertyp |= XFERTYP_MSBSEL; 125 xfertyp |= XFERTYP_BCEN; 126 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 127 xfertyp |= XFERTYP_AC12EN; 128 #endif 129 } 130 131 if (data->flags & MMC_DATA_READ) 132 xfertyp |= XFERTYP_DTDSEL; 133 } 134 135 if (cmd->resp_type & MMC_RSP_CRC) 136 xfertyp |= XFERTYP_CCCEN; 137 if (cmd->resp_type & MMC_RSP_OPCODE) 138 xfertyp |= XFERTYP_CICEN; 139 if (cmd->resp_type & MMC_RSP_136) 140 xfertyp |= XFERTYP_RSPTYP_136; 141 else if (cmd->resp_type & MMC_RSP_BUSY) 142 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 143 else if (cmd->resp_type & MMC_RSP_PRESENT) 144 xfertyp |= XFERTYP_RSPTYP_48; 145 146 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 147 xfertyp |= XFERTYP_CMDTYP_ABORT; 148 149 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 150 } 151 152 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 153 /* 154 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 155 */ 156 static void 157 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 158 { 159 struct fsl_esdhc_priv *priv = mmc->priv; 160 struct fsl_esdhc *regs = priv->esdhc_regs; 161 uint blocks; 162 char *buffer; 163 uint databuf; 164 uint size; 165 uint irqstat; 166 uint timeout; 167 168 if (data->flags & MMC_DATA_READ) { 169 blocks = data->blocks; 170 buffer = data->dest; 171 while (blocks) { 172 timeout = PIO_TIMEOUT; 173 size = data->blocksize; 174 irqstat = esdhc_read32(®s->irqstat); 175 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 176 && --timeout); 177 if (timeout <= 0) { 178 printf("\nData Read Failed in PIO Mode."); 179 return; 180 } 181 while (size && (!(irqstat & IRQSTAT_TC))) { 182 udelay(100); /* Wait before last byte transfer complete */ 183 irqstat = esdhc_read32(®s->irqstat); 184 databuf = in_le32(®s->datport); 185 *((uint *)buffer) = databuf; 186 buffer += 4; 187 size -= 4; 188 } 189 blocks--; 190 } 191 } else { 192 blocks = data->blocks; 193 buffer = (char *)data->src; 194 while (blocks) { 195 timeout = PIO_TIMEOUT; 196 size = data->blocksize; 197 irqstat = esdhc_read32(®s->irqstat); 198 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 199 && --timeout); 200 if (timeout <= 0) { 201 printf("\nData Write Failed in PIO Mode."); 202 return; 203 } 204 while (size && (!(irqstat & IRQSTAT_TC))) { 205 udelay(100); /* Wait before last byte transfer complete */ 206 databuf = *((uint *)buffer); 207 buffer += 4; 208 size -= 4; 209 irqstat = esdhc_read32(®s->irqstat); 210 out_le32(®s->datport, databuf); 211 } 212 blocks--; 213 } 214 } 215 } 216 #endif 217 218 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 219 { 220 int timeout; 221 struct fsl_esdhc_priv *priv = mmc->priv; 222 struct fsl_esdhc *regs = priv->esdhc_regs; 223 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 224 dma_addr_t addr; 225 #endif 226 uint wml_value; 227 228 wml_value = data->blocksize/4; 229 230 if (data->flags & MMC_DATA_READ) { 231 if (wml_value > WML_RD_WML_MAX) 232 wml_value = WML_RD_WML_MAX_VAL; 233 234 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 235 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 236 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 237 addr = virt_to_phys((void *)(data->dest)); 238 if (upper_32_bits(addr)) 239 printf("Error found for upper 32 bits\n"); 240 else 241 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 242 #else 243 esdhc_write32(®s->dsaddr, (u32)data->dest); 244 #endif 245 #endif 246 } else { 247 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 248 flush_dcache_range((ulong)data->src, 249 (ulong)data->src+data->blocks 250 *data->blocksize); 251 #endif 252 if (wml_value > WML_WR_WML_MAX) 253 wml_value = WML_WR_WML_MAX_VAL; 254 if (priv->wp_enable) { 255 if ((esdhc_read32(®s->prsstat) & 256 PRSSTAT_WPSPL) == 0) { 257 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 258 return -ETIMEDOUT; 259 } 260 } 261 262 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 263 wml_value << 16); 264 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 265 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 266 addr = virt_to_phys((void *)(data->src)); 267 if (upper_32_bits(addr)) 268 printf("Error found for upper 32 bits\n"); 269 else 270 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 271 #else 272 esdhc_write32(®s->dsaddr, (u32)data->src); 273 #endif 274 #endif 275 } 276 277 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 278 279 /* Calculate the timeout period for data transactions */ 280 /* 281 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 282 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 283 * So, Number of SD Clock cycles for 0.25sec should be minimum 284 * (SD Clock/sec * 0.25 sec) SD Clock cycles 285 * = (mmc->clock * 1/4) SD Clock cycles 286 * As 1) >= 2) 287 * => (2^(timeout+13)) >= mmc->clock * 1/4 288 * Taking log2 both the sides 289 * => timeout + 13 >= log2(mmc->clock/4) 290 * Rounding up to next power of 2 291 * => timeout + 13 = log2(mmc->clock/4) + 1 292 * => timeout + 13 = fls(mmc->clock/4) 293 * 294 * However, the MMC spec "It is strongly recommended for hosts to 295 * implement more than 500ms timeout value even if the card 296 * indicates the 250ms maximum busy length." Even the previous 297 * value of 300ms is known to be insufficient for some cards. 298 * So, we use 299 * => timeout + 13 = fls(mmc->clock/2) 300 */ 301 timeout = fls(mmc->clock/2); 302 timeout -= 13; 303 304 if (timeout > 14) 305 timeout = 14; 306 307 if (timeout < 0) 308 timeout = 0; 309 310 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 311 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 312 timeout++; 313 #endif 314 315 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 316 timeout = 0xE; 317 #endif 318 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 319 320 return 0; 321 } 322 323 static void check_and_invalidate_dcache_range 324 (struct mmc_cmd *cmd, 325 struct mmc_data *data) { 326 unsigned start = 0; 327 unsigned end = 0; 328 unsigned size = roundup(ARCH_DMA_MINALIGN, 329 data->blocks*data->blocksize); 330 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) 331 dma_addr_t addr; 332 333 addr = virt_to_phys((void *)(data->dest)); 334 if (upper_32_bits(addr)) 335 printf("Error found for upper 32 bits\n"); 336 else 337 start = lower_32_bits(addr); 338 #else 339 start = (unsigned)data->dest; 340 #endif 341 end = start + size; 342 invalidate_dcache_range(start, end); 343 } 344 345 /* 346 * Sends a command out on the bus. Takes the mmc pointer, 347 * a command pointer, and an optional data pointer. 348 */ 349 static int 350 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 351 { 352 int err = 0; 353 uint xfertyp; 354 uint irqstat; 355 struct fsl_esdhc_priv *priv = mmc->priv; 356 struct fsl_esdhc *regs = priv->esdhc_regs; 357 358 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 359 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 360 return 0; 361 #endif 362 363 esdhc_write32(®s->irqstat, -1); 364 365 sync(); 366 367 /* Wait for the bus to be idle */ 368 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 369 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 370 ; 371 372 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 373 ; 374 375 /* Wait at least 8 SD clock cycles before the next command */ 376 /* 377 * Note: This is way more than 8 cycles, but 1ms seems to 378 * resolve timing issues with some cards 379 */ 380 udelay(1000); 381 382 /* Set up for a data transfer if we have one */ 383 if (data) { 384 err = esdhc_setup_data(mmc, data); 385 if(err) 386 return err; 387 388 if (data->flags & MMC_DATA_READ) 389 check_and_invalidate_dcache_range(cmd, data); 390 } 391 392 /* Figure out the transfer arguments */ 393 xfertyp = esdhc_xfertyp(cmd, data); 394 395 /* Mask all irqs */ 396 esdhc_write32(®s->irqsigen, 0); 397 398 /* Send the command */ 399 esdhc_write32(®s->cmdarg, cmd->cmdarg); 400 #if defined(CONFIG_FSL_USDHC) 401 esdhc_write32(®s->mixctrl, 402 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 403 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 404 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 405 #else 406 esdhc_write32(®s->xfertyp, xfertyp); 407 #endif 408 409 /* Wait for the command to complete */ 410 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 411 ; 412 413 irqstat = esdhc_read32(®s->irqstat); 414 415 if (irqstat & CMD_ERR) { 416 err = -ECOMM; 417 goto out; 418 } 419 420 if (irqstat & IRQSTAT_CTOE) { 421 err = -ETIMEDOUT; 422 goto out; 423 } 424 425 /* Switch voltage to 1.8V if CMD11 succeeded */ 426 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 427 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 428 429 printf("Run CMD11 1.8V switch\n"); 430 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 431 udelay(5000); 432 } 433 434 /* Workaround for ESDHC errata ENGcm03648 */ 435 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 436 int timeout = 6000; 437 438 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 439 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 440 PRSSTAT_DAT0)) { 441 udelay(100); 442 timeout--; 443 } 444 445 if (timeout <= 0) { 446 printf("Timeout waiting for DAT0 to go high!\n"); 447 err = -ETIMEDOUT; 448 goto out; 449 } 450 } 451 452 /* Copy the response to the response buffer */ 453 if (cmd->resp_type & MMC_RSP_136) { 454 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 455 456 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 457 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 458 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 459 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 460 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 461 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 462 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 463 cmd->response[3] = (cmdrsp0 << 8); 464 } else 465 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 466 467 /* Wait until all of the blocks are transferred */ 468 if (data) { 469 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 470 esdhc_pio_read_write(mmc, data); 471 #else 472 do { 473 irqstat = esdhc_read32(®s->irqstat); 474 475 if (irqstat & IRQSTAT_DTOE) { 476 err = -ETIMEDOUT; 477 goto out; 478 } 479 480 if (irqstat & DATA_ERR) { 481 err = -ECOMM; 482 goto out; 483 } 484 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 485 486 /* 487 * Need invalidate the dcache here again to avoid any 488 * cache-fill during the DMA operations such as the 489 * speculative pre-fetching etc. 490 */ 491 if (data->flags & MMC_DATA_READ) 492 check_and_invalidate_dcache_range(cmd, data); 493 #endif 494 } 495 496 out: 497 /* Reset CMD and DATA portions on error */ 498 if (err) { 499 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 500 SYSCTL_RSTC); 501 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 502 ; 503 504 if (data) { 505 esdhc_write32(®s->sysctl, 506 esdhc_read32(®s->sysctl) | 507 SYSCTL_RSTD); 508 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 509 ; 510 } 511 512 /* If this was CMD11, then notify that power cycle is needed */ 513 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 514 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 515 } 516 517 esdhc_write32(®s->irqstat, -1); 518 519 return err; 520 } 521 522 static void set_sysctl(struct mmc *mmc, uint clock) 523 { 524 int div = 1; 525 #ifdef ARCH_MXC 526 int pre_div = 1; 527 #else 528 int pre_div = 2; 529 #endif 530 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; 531 struct fsl_esdhc_priv *priv = mmc->priv; 532 struct fsl_esdhc *regs = priv->esdhc_regs; 533 int sdhc_clk = priv->sdhc_clk; 534 uint clk; 535 536 if (clock < mmc->cfg->f_min) 537 clock = mmc->cfg->f_min; 538 539 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) 540 pre_div *= 2; 541 542 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) 543 div++; 544 545 pre_div >>= 1; 546 div -= 1; 547 548 clk = (pre_div << 8) | (div << 4); 549 550 #ifdef CONFIG_FSL_USDHC 551 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); 552 #else 553 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 554 #endif 555 556 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 557 558 udelay(10000); 559 560 #ifdef CONFIG_FSL_USDHC 561 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 562 #else 563 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 564 #endif 565 566 } 567 568 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 569 static void esdhc_clock_control(struct mmc *mmc, bool enable) 570 { 571 struct fsl_esdhc_priv *priv = mmc->priv; 572 struct fsl_esdhc *regs = priv->esdhc_regs; 573 u32 value; 574 u32 time_out; 575 576 value = esdhc_read32(®s->sysctl); 577 578 if (enable) 579 value |= SYSCTL_CKEN; 580 else 581 value &= ~SYSCTL_CKEN; 582 583 esdhc_write32(®s->sysctl, value); 584 585 time_out = 20; 586 value = PRSSTAT_SDSTB; 587 while (!(esdhc_read32(®s->prsstat) & value)) { 588 if (time_out == 0) { 589 printf("fsl_esdhc: Internal clock never stabilised.\n"); 590 break; 591 } 592 time_out--; 593 mdelay(1); 594 } 595 } 596 #endif 597 598 static int esdhc_set_ios(struct mmc *mmc) 599 { 600 struct fsl_esdhc_priv *priv = mmc->priv; 601 struct fsl_esdhc *regs = priv->esdhc_regs; 602 603 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 604 /* Select to use peripheral clock */ 605 esdhc_clock_control(mmc, false); 606 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 607 esdhc_clock_control(mmc, true); 608 #endif 609 /* Set the clock speed */ 610 set_sysctl(mmc, mmc->clock); 611 612 /* Set the bus width */ 613 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 614 615 if (mmc->bus_width == 4) 616 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 617 else if (mmc->bus_width == 8) 618 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 619 620 return 0; 621 } 622 623 static int esdhc_init(struct mmc *mmc) 624 { 625 struct fsl_esdhc_priv *priv = mmc->priv; 626 struct fsl_esdhc *regs = priv->esdhc_regs; 627 int timeout = 1000; 628 629 /* Reset the entire host controller */ 630 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 631 632 /* Wait until the controller is available */ 633 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 634 udelay(1000); 635 636 #if defined(CONFIG_FSL_USDHC) 637 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 638 esdhc_write32(®s->mmcboot, 0x0); 639 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 640 esdhc_write32(®s->mixctrl, 0x0); 641 esdhc_write32(®s->clktunectrlstatus, 0x0); 642 643 /* Put VEND_SPEC to default value */ 644 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); 645 646 /* Disable DLL_CTRL delay line */ 647 esdhc_write32(®s->dllctrl, 0x0); 648 #endif 649 650 #ifndef ARCH_MXC 651 /* Enable cache snooping */ 652 esdhc_write32(®s->scr, 0x00000040); 653 #endif 654 655 #ifndef CONFIG_FSL_USDHC 656 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 657 #else 658 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 659 #endif 660 661 /* Set the initial clock speed */ 662 mmc_set_clock(mmc, 400000); 663 664 /* Disable the BRR and BWR bits in IRQSTAT */ 665 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 666 667 /* Put the PROCTL reg back to the default */ 668 esdhc_write32(®s->proctl, PROCTL_INIT); 669 670 /* Set timout to the maximum value */ 671 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 672 673 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 674 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 675 #endif 676 677 return 0; 678 } 679 680 static int esdhc_getcd(struct mmc *mmc) 681 { 682 struct fsl_esdhc_priv *priv = mmc->priv; 683 struct fsl_esdhc *regs = priv->esdhc_regs; 684 int timeout = 1000; 685 686 #ifdef CONFIG_ESDHC_DETECT_QUIRK 687 if (CONFIG_ESDHC_DETECT_QUIRK) 688 return 1; 689 #endif 690 691 #ifdef CONFIG_DM_MMC 692 if (priv->non_removable) 693 return 1; 694 #ifdef CONFIG_DM_GPIO 695 if (dm_gpio_is_valid(&priv->cd_gpio)) 696 return dm_gpio_get_value(&priv->cd_gpio); 697 #endif 698 #endif 699 700 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 701 udelay(1000); 702 703 return timeout > 0; 704 } 705 706 static void esdhc_reset(struct fsl_esdhc *regs) 707 { 708 unsigned long timeout = 100; /* wait max 100 ms */ 709 710 /* reset the controller */ 711 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 712 713 /* hardware clears the bit when it is done */ 714 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 715 udelay(1000); 716 if (!timeout) 717 printf("MMC/SD: Reset never completed.\n"); 718 } 719 720 static const struct mmc_ops esdhc_ops = { 721 .send_cmd = esdhc_send_cmd, 722 .set_ios = esdhc_set_ios, 723 .init = esdhc_init, 724 .getcd = esdhc_getcd, 725 }; 726 727 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) 728 { 729 struct fsl_esdhc *regs; 730 struct mmc *mmc; 731 u32 caps, voltage_caps; 732 733 if (!priv) 734 return -EINVAL; 735 736 regs = priv->esdhc_regs; 737 738 /* First reset the eSDHC controller */ 739 esdhc_reset(regs); 740 741 #ifndef CONFIG_FSL_USDHC 742 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 743 | SYSCTL_IPGEN | SYSCTL_CKEN); 744 #else 745 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | 746 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 747 #endif 748 749 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 750 memset(&priv->cfg, 0, sizeof(priv->cfg)); 751 752 voltage_caps = 0; 753 caps = esdhc_read32(®s->hostcapblt); 754 755 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 756 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 757 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 758 #endif 759 760 /* T4240 host controller capabilities register should have VS33 bit */ 761 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 762 caps = caps | ESDHC_HOSTCAPBLT_VS33; 763 #endif 764 765 if (caps & ESDHC_HOSTCAPBLT_VS18) 766 voltage_caps |= MMC_VDD_165_195; 767 if (caps & ESDHC_HOSTCAPBLT_VS30) 768 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 769 if (caps & ESDHC_HOSTCAPBLT_VS33) 770 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 771 772 priv->cfg.name = "FSL_SDHC"; 773 priv->cfg.ops = &esdhc_ops; 774 #ifdef CONFIG_SYS_SD_VOLTAGE 775 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 776 #else 777 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 778 #endif 779 if ((priv->cfg.voltages & voltage_caps) == 0) { 780 printf("voltage not supported by controller\n"); 781 return -1; 782 } 783 784 if (priv->bus_width == 8) 785 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 786 else if (priv->bus_width == 4) 787 priv->cfg.host_caps = MMC_MODE_4BIT; 788 789 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 790 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 791 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; 792 #endif 793 794 if (priv->bus_width > 0) { 795 if (priv->bus_width < 8) 796 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 797 if (priv->bus_width < 4) 798 priv->cfg.host_caps &= ~MMC_MODE_4BIT; 799 } 800 801 if (caps & ESDHC_HOSTCAPBLT_HSS) 802 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 803 804 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 805 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 806 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 807 #endif 808 809 priv->cfg.f_min = 400000; 810 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); 811 812 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 813 814 mmc = mmc_create(&priv->cfg, priv); 815 if (mmc == NULL) 816 return -1; 817 818 priv->mmc = mmc; 819 820 return 0; 821 } 822 823 #ifndef CONFIG_DM_MMC 824 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 825 struct fsl_esdhc_priv *priv) 826 { 827 if (!cfg || !priv) 828 return -EINVAL; 829 830 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 831 priv->bus_width = cfg->max_bus_width; 832 priv->sdhc_clk = cfg->sdhc_clk; 833 priv->wp_enable = cfg->wp_enable; 834 835 return 0; 836 }; 837 838 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 839 { 840 struct fsl_esdhc_priv *priv; 841 int ret; 842 843 if (!cfg) 844 return -EINVAL; 845 846 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 847 if (!priv) 848 return -ENOMEM; 849 850 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 851 if (ret) { 852 debug("%s xlate failure\n", __func__); 853 free(priv); 854 return ret; 855 } 856 857 ret = fsl_esdhc_init(priv); 858 if (ret) { 859 debug("%s init failure\n", __func__); 860 free(priv); 861 return ret; 862 } 863 864 return 0; 865 } 866 867 int fsl_esdhc_mmc_init(bd_t *bis) 868 { 869 struct fsl_esdhc_cfg *cfg; 870 871 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 872 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 873 cfg->sdhc_clk = gd->arch.sdhc_clk; 874 return fsl_esdhc_initialize(bis, cfg); 875 } 876 #endif 877 878 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 879 void mmc_adapter_card_type_ident(void) 880 { 881 u8 card_id; 882 u8 value; 883 884 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 885 gd->arch.sdhc_adapter = card_id; 886 887 switch (card_id) { 888 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 889 value = QIXIS_READ(brdcfg[5]); 890 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 891 QIXIS_WRITE(brdcfg[5], value); 892 break; 893 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 894 value = QIXIS_READ(pwr_ctl[1]); 895 value |= QIXIS_EVDD_BY_SDHC_VS; 896 QIXIS_WRITE(pwr_ctl[1], value); 897 break; 898 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 899 value = QIXIS_READ(brdcfg[5]); 900 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 901 QIXIS_WRITE(brdcfg[5], value); 902 break; 903 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 904 break; 905 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 906 break; 907 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 908 break; 909 case QIXIS_ESDHC_NO_ADAPTER: 910 break; 911 default: 912 break; 913 } 914 } 915 #endif 916 917 #ifdef CONFIG_OF_LIBFDT 918 __weak int esdhc_status_fixup(void *blob, const char *compat) 919 { 920 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 921 if (!hwconfig("esdhc")) { 922 do_fixup_by_compat(blob, compat, "status", "disabled", 923 sizeof("disabled"), 1); 924 return 1; 925 } 926 #endif 927 do_fixup_by_compat(blob, compat, "status", "okay", 928 sizeof("okay"), 1); 929 return 0; 930 } 931 932 void fdt_fixup_esdhc(void *blob, bd_t *bd) 933 { 934 const char *compat = "fsl,esdhc"; 935 936 if (esdhc_status_fixup(blob, compat)) 937 return; 938 939 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 940 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 941 gd->arch.sdhc_clk, 1); 942 #else 943 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 944 gd->arch.sdhc_clk, 1); 945 #endif 946 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 947 do_fixup_by_compat_u32(blob, compat, "adapter-type", 948 (u32)(gd->arch.sdhc_adapter), 1); 949 #endif 950 } 951 #endif 952 953 #ifdef CONFIG_DM_MMC 954 #include <asm/arch/clock.h> 955 __weak void init_clk_usdhc(u32 index) 956 { 957 } 958 959 static int fsl_esdhc_probe(struct udevice *dev) 960 { 961 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 962 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 963 const void *fdt = gd->fdt_blob; 964 int node = dev_of_offset(dev); 965 fdt_addr_t addr; 966 unsigned int val; 967 int ret; 968 969 addr = devfdt_get_addr(dev); 970 if (addr == FDT_ADDR_T_NONE) 971 return -EINVAL; 972 973 priv->esdhc_regs = (struct fsl_esdhc *)addr; 974 priv->dev = dev; 975 976 val = fdtdec_get_int(fdt, node, "bus-width", -1); 977 if (val == 8) 978 priv->bus_width = 8; 979 else if (val == 4) 980 priv->bus_width = 4; 981 else 982 priv->bus_width = 1; 983 984 if (fdt_get_property(fdt, node, "non-removable", NULL)) { 985 priv->non_removable = 1; 986 } else { 987 priv->non_removable = 0; 988 #ifdef CONFIG_DM_GPIO 989 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 990 0, &priv->cd_gpio, GPIOD_IS_IN); 991 #endif 992 } 993 994 priv->wp_enable = 1; 995 996 #ifdef CONFIG_DM_GPIO 997 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0, 998 &priv->wp_gpio, GPIOD_IS_IN); 999 if (ret) 1000 priv->wp_enable = 0; 1001 #endif 1002 /* 1003 * TODO: 1004 * Because lack of clk driver, if SDHC clk is not enabled, 1005 * need to enable it first before this driver is invoked. 1006 * 1007 * we use MXC_ESDHC_CLK to get clk freq. 1008 * If one would like to make this function work, 1009 * the aliases should be provided in dts as this: 1010 * 1011 * aliases { 1012 * mmc0 = &usdhc1; 1013 * mmc1 = &usdhc2; 1014 * mmc2 = &usdhc3; 1015 * mmc3 = &usdhc4; 1016 * }; 1017 * Then if your board only supports mmc2 and mmc3, but we can 1018 * correctly get the seq as 2 and 3, then let mxc_get_clock 1019 * work as expected. 1020 */ 1021 1022 init_clk_usdhc(dev->seq); 1023 1024 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1025 if (priv->sdhc_clk <= 0) { 1026 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1027 return -EINVAL; 1028 } 1029 1030 ret = fsl_esdhc_init(priv); 1031 if (ret) { 1032 dev_err(dev, "fsl_esdhc_init failure\n"); 1033 return ret; 1034 } 1035 1036 upriv->mmc = priv->mmc; 1037 priv->mmc->dev = dev; 1038 1039 return 0; 1040 } 1041 1042 static const struct udevice_id fsl_esdhc_ids[] = { 1043 { .compatible = "fsl,imx6ul-usdhc", }, 1044 { .compatible = "fsl,imx6sx-usdhc", }, 1045 { .compatible = "fsl,imx6sl-usdhc", }, 1046 { .compatible = "fsl,imx6q-usdhc", }, 1047 { .compatible = "fsl,imx7d-usdhc", }, 1048 { .compatible = "fsl,imx7ulp-usdhc", }, 1049 { .compatible = "fsl,esdhc", }, 1050 { /* sentinel */ } 1051 }; 1052 1053 U_BOOT_DRIVER(fsl_esdhc) = { 1054 .name = "fsl-esdhc-mmc", 1055 .id = UCLASS_MMC, 1056 .of_match = fsl_esdhc_ids, 1057 .probe = fsl_esdhc_probe, 1058 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1059 }; 1060 #endif 1061