1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 27 IRQSTATEN_CINT | \ 28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 31 IRQSTATEN_DINT) 32 33 struct fsl_esdhc { 34 uint dsaddr; /* SDMA system address register */ 35 uint blkattr; /* Block attributes register */ 36 uint cmdarg; /* Command argument register */ 37 uint xfertyp; /* Transfer type register */ 38 uint cmdrsp0; /* Command response 0 register */ 39 uint cmdrsp1; /* Command response 1 register */ 40 uint cmdrsp2; /* Command response 2 register */ 41 uint cmdrsp3; /* Command response 3 register */ 42 uint datport; /* Buffer data port register */ 43 uint prsstat; /* Present state register */ 44 uint proctl; /* Protocol control register */ 45 uint sysctl; /* System Control Register */ 46 uint irqstat; /* Interrupt status register */ 47 uint irqstaten; /* Interrupt status enable register */ 48 uint irqsigen; /* Interrupt signal enable register */ 49 uint autoc12err; /* Auto CMD error status register */ 50 uint hostcapblt; /* Host controller capabilities register */ 51 uint wml; /* Watermark level register */ 52 uint mixctrl; /* For USDHC */ 53 char reserved1[4]; /* reserved */ 54 uint fevt; /* Force event register */ 55 uint admaes; /* ADMA error status register */ 56 uint adsaddr; /* ADMA system address register */ 57 char reserved2[100]; /* reserved */ 58 uint vendorspec; /* Vendor Specific register */ 59 char reserved3[56]; /* reserved */ 60 uint hostver; /* Host controller version register */ 61 char reserved4[4]; /* reserved */ 62 uint dmaerraddr; /* DMA error address register */ 63 char reserved5[4]; /* reserved */ 64 uint dmaerrattr; /* DMA error attribute register */ 65 char reserved6[4]; /* reserved */ 66 uint hostcapblt2; /* Host controller capabilities register 2 */ 67 char reserved7[8]; /* reserved */ 68 uint tcr; /* Tuning control register */ 69 char reserved8[28]; /* reserved */ 70 uint sddirctl; /* SD direction control register */ 71 char reserved9[712]; /* reserved */ 72 uint scr; /* eSDHC control register */ 73 }; 74 75 /* Return the XFERTYP flags for a given command and data packet */ 76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 77 { 78 uint xfertyp = 0; 79 80 if (data) { 81 xfertyp |= XFERTYP_DPSEL; 82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 83 xfertyp |= XFERTYP_DMAEN; 84 #endif 85 if (data->blocks > 1) { 86 xfertyp |= XFERTYP_MSBSEL; 87 xfertyp |= XFERTYP_BCEN; 88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 89 xfertyp |= XFERTYP_AC12EN; 90 #endif 91 } 92 93 if (data->flags & MMC_DATA_READ) 94 xfertyp |= XFERTYP_DTDSEL; 95 } 96 97 if (cmd->resp_type & MMC_RSP_CRC) 98 xfertyp |= XFERTYP_CCCEN; 99 if (cmd->resp_type & MMC_RSP_OPCODE) 100 xfertyp |= XFERTYP_CICEN; 101 if (cmd->resp_type & MMC_RSP_136) 102 xfertyp |= XFERTYP_RSPTYP_136; 103 else if (cmd->resp_type & MMC_RSP_BUSY) 104 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 105 else if (cmd->resp_type & MMC_RSP_PRESENT) 106 xfertyp |= XFERTYP_RSPTYP_48; 107 108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ 109 defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) 110 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 111 xfertyp |= XFERTYP_CMDTYP_ABORT; 112 #endif 113 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 114 } 115 116 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 117 /* 118 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 119 */ 120 static void 121 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 122 { 123 struct fsl_esdhc_cfg *cfg = mmc->priv; 124 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 125 uint blocks; 126 char *buffer; 127 uint databuf; 128 uint size; 129 uint irqstat; 130 uint timeout; 131 132 if (data->flags & MMC_DATA_READ) { 133 blocks = data->blocks; 134 buffer = data->dest; 135 while (blocks) { 136 timeout = PIO_TIMEOUT; 137 size = data->blocksize; 138 irqstat = esdhc_read32(®s->irqstat); 139 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 140 && --timeout); 141 if (timeout <= 0) { 142 printf("\nData Read Failed in PIO Mode."); 143 return; 144 } 145 while (size && (!(irqstat & IRQSTAT_TC))) { 146 udelay(100); /* Wait before last byte transfer complete */ 147 irqstat = esdhc_read32(®s->irqstat); 148 databuf = in_le32(®s->datport); 149 *((uint *)buffer) = databuf; 150 buffer += 4; 151 size -= 4; 152 } 153 blocks--; 154 } 155 } else { 156 blocks = data->blocks; 157 buffer = (char *)data->src; 158 while (blocks) { 159 timeout = PIO_TIMEOUT; 160 size = data->blocksize; 161 irqstat = esdhc_read32(®s->irqstat); 162 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 163 && --timeout); 164 if (timeout <= 0) { 165 printf("\nData Write Failed in PIO Mode."); 166 return; 167 } 168 while (size && (!(irqstat & IRQSTAT_TC))) { 169 udelay(100); /* Wait before last byte transfer complete */ 170 databuf = *((uint *)buffer); 171 buffer += 4; 172 size -= 4; 173 irqstat = esdhc_read32(®s->irqstat); 174 out_le32(®s->datport, databuf); 175 } 176 blocks--; 177 } 178 } 179 } 180 #endif 181 182 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 183 { 184 int timeout; 185 struct fsl_esdhc_cfg *cfg = mmc->priv; 186 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 187 #ifdef CONFIG_LS2085A 188 dma_addr_t addr; 189 #endif 190 uint wml_value; 191 192 wml_value = data->blocksize/4; 193 194 if (data->flags & MMC_DATA_READ) { 195 if (wml_value > WML_RD_WML_MAX) 196 wml_value = WML_RD_WML_MAX_VAL; 197 198 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 199 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 200 #ifdef CONFIG_LS2085A 201 addr = virt_to_phys((void *)(data->dest)); 202 if (upper_32_bits(addr)) 203 printf("Error found for upper 32 bits\n"); 204 else 205 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 206 #else 207 esdhc_write32(®s->dsaddr, (u32)data->dest); 208 #endif 209 #endif 210 } else { 211 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 212 flush_dcache_range((ulong)data->src, 213 (ulong)data->src+data->blocks 214 *data->blocksize); 215 #endif 216 if (wml_value > WML_WR_WML_MAX) 217 wml_value = WML_WR_WML_MAX_VAL; 218 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 219 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 220 return TIMEOUT; 221 } 222 223 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 224 wml_value << 16); 225 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 226 #ifdef CONFIG_LS2085A 227 addr = virt_to_phys((void *)(data->src)); 228 if (upper_32_bits(addr)) 229 printf("Error found for upper 32 bits\n"); 230 else 231 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 232 #else 233 esdhc_write32(®s->dsaddr, (u32)data->src); 234 #endif 235 #endif 236 } 237 238 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 239 240 /* Calculate the timeout period for data transactions */ 241 /* 242 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 243 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 244 * So, Number of SD Clock cycles for 0.25sec should be minimum 245 * (SD Clock/sec * 0.25 sec) SD Clock cycles 246 * = (mmc->clock * 1/4) SD Clock cycles 247 * As 1) >= 2) 248 * => (2^(timeout+13)) >= mmc->clock * 1/4 249 * Taking log2 both the sides 250 * => timeout + 13 >= log2(mmc->clock/4) 251 * Rounding up to next power of 2 252 * => timeout + 13 = log2(mmc->clock/4) + 1 253 * => timeout + 13 = fls(mmc->clock/4) 254 */ 255 timeout = fls(mmc->clock/4); 256 timeout -= 13; 257 258 if (timeout > 14) 259 timeout = 14; 260 261 if (timeout < 0) 262 timeout = 0; 263 264 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 265 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 266 timeout++; 267 #endif 268 269 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 270 timeout = 0xE; 271 #endif 272 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 273 274 return 0; 275 } 276 277 static void check_and_invalidate_dcache_range 278 (struct mmc_cmd *cmd, 279 struct mmc_data *data) { 280 #ifdef CONFIG_LS2085A 281 unsigned start = 0; 282 #else 283 unsigned start = (unsigned)data->dest ; 284 #endif 285 unsigned size = roundup(ARCH_DMA_MINALIGN, 286 data->blocks*data->blocksize); 287 unsigned end = start+size ; 288 #ifdef CONFIG_LS2085A 289 dma_addr_t addr; 290 291 addr = virt_to_phys((void *)(data->dest)); 292 if (upper_32_bits(addr)) 293 printf("Error found for upper 32 bits\n"); 294 else 295 start = lower_32_bits(addr); 296 #endif 297 invalidate_dcache_range(start, end); 298 } 299 300 /* 301 * Sends a command out on the bus. Takes the mmc pointer, 302 * a command pointer, and an optional data pointer. 303 */ 304 static int 305 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 306 { 307 int err = 0; 308 uint xfertyp; 309 uint irqstat; 310 struct fsl_esdhc_cfg *cfg = mmc->priv; 311 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 312 313 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 314 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 315 return 0; 316 #endif 317 318 esdhc_write32(®s->irqstat, -1); 319 320 sync(); 321 322 /* Wait for the bus to be idle */ 323 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 324 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 325 ; 326 327 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 328 ; 329 330 /* Wait at least 8 SD clock cycles before the next command */ 331 /* 332 * Note: This is way more than 8 cycles, but 1ms seems to 333 * resolve timing issues with some cards 334 */ 335 udelay(1000); 336 337 /* Set up for a data transfer if we have one */ 338 if (data) { 339 err = esdhc_setup_data(mmc, data); 340 if(err) 341 return err; 342 343 if (data->flags & MMC_DATA_READ) 344 check_and_invalidate_dcache_range(cmd, data); 345 } 346 347 /* Figure out the transfer arguments */ 348 xfertyp = esdhc_xfertyp(cmd, data); 349 350 /* Mask all irqs */ 351 esdhc_write32(®s->irqsigen, 0); 352 353 /* Send the command */ 354 esdhc_write32(®s->cmdarg, cmd->cmdarg); 355 #if defined(CONFIG_FSL_USDHC) 356 esdhc_write32(®s->mixctrl, 357 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 358 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 359 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 360 #else 361 esdhc_write32(®s->xfertyp, xfertyp); 362 #endif 363 364 /* Wait for the command to complete */ 365 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 366 ; 367 368 irqstat = esdhc_read32(®s->irqstat); 369 370 if (irqstat & CMD_ERR) { 371 err = COMM_ERR; 372 goto out; 373 } 374 375 if (irqstat & IRQSTAT_CTOE) { 376 err = TIMEOUT; 377 goto out; 378 } 379 380 /* Switch voltage to 1.8V if CMD11 succeeded */ 381 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 382 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 383 384 printf("Run CMD11 1.8V switch\n"); 385 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 386 udelay(5000); 387 } 388 389 /* Workaround for ESDHC errata ENGcm03648 */ 390 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 391 int timeout = 6000; 392 393 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 394 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 395 PRSSTAT_DAT0)) { 396 udelay(100); 397 timeout--; 398 } 399 400 if (timeout <= 0) { 401 printf("Timeout waiting for DAT0 to go high!\n"); 402 err = TIMEOUT; 403 goto out; 404 } 405 } 406 407 /* Copy the response to the response buffer */ 408 if (cmd->resp_type & MMC_RSP_136) { 409 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 410 411 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 412 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 413 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 414 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 415 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 416 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 417 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 418 cmd->response[3] = (cmdrsp0 << 8); 419 } else 420 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 421 422 /* Wait until all of the blocks are transferred */ 423 if (data) { 424 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 425 esdhc_pio_read_write(mmc, data); 426 #else 427 do { 428 irqstat = esdhc_read32(®s->irqstat); 429 430 if (irqstat & IRQSTAT_DTOE) { 431 err = TIMEOUT; 432 goto out; 433 } 434 435 if (irqstat & DATA_ERR) { 436 err = COMM_ERR; 437 goto out; 438 } 439 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 440 441 /* 442 * Need invalidate the dcache here again to avoid any 443 * cache-fill during the DMA operations such as the 444 * speculative pre-fetching etc. 445 */ 446 if (data->flags & MMC_DATA_READ) 447 check_and_invalidate_dcache_range(cmd, data); 448 #endif 449 } 450 451 out: 452 /* Reset CMD and DATA portions on error */ 453 if (err) { 454 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 455 SYSCTL_RSTC); 456 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 457 ; 458 459 if (data) { 460 esdhc_write32(®s->sysctl, 461 esdhc_read32(®s->sysctl) | 462 SYSCTL_RSTD); 463 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 464 ; 465 } 466 467 /* If this was CMD11, then notify that power cycle is needed */ 468 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 469 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 470 } 471 472 esdhc_write32(®s->irqstat, -1); 473 474 return err; 475 } 476 477 static void set_sysctl(struct mmc *mmc, uint clock) 478 { 479 int div, pre_div; 480 struct fsl_esdhc_cfg *cfg = mmc->priv; 481 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 482 int sdhc_clk = cfg->sdhc_clk; 483 uint clk; 484 485 if (clock < mmc->cfg->f_min) 486 clock = mmc->cfg->f_min; 487 488 if (sdhc_clk / 16 > clock) { 489 for (pre_div = 2; pre_div < 256; pre_div *= 2) 490 if ((sdhc_clk / pre_div) <= (clock * 16)) 491 break; 492 } else 493 pre_div = 2; 494 495 for (div = 1; div <= 16; div++) 496 if ((sdhc_clk / (div * pre_div)) <= clock) 497 break; 498 499 pre_div >>= mmc->ddr_mode ? 2 : 1; 500 div -= 1; 501 502 clk = (pre_div << 8) | (div << 4); 503 504 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 505 506 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 507 508 udelay(10000); 509 510 clk = SYSCTL_PEREN | SYSCTL_CKEN; 511 512 esdhc_setbits32(®s->sysctl, clk); 513 } 514 515 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 516 static void esdhc_clock_control(struct mmc *mmc, bool enable) 517 { 518 struct fsl_esdhc_cfg *cfg = mmc->priv; 519 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 520 u32 value; 521 u32 time_out; 522 523 value = esdhc_read32(®s->sysctl); 524 525 if (enable) 526 value |= SYSCTL_CKEN; 527 else 528 value &= ~SYSCTL_CKEN; 529 530 esdhc_write32(®s->sysctl, value); 531 532 time_out = 20; 533 value = PRSSTAT_SDSTB; 534 while (!(esdhc_read32(®s->prsstat) & value)) { 535 if (time_out == 0) { 536 printf("fsl_esdhc: Internal clock never stabilised.\n"); 537 break; 538 } 539 time_out--; 540 mdelay(1); 541 } 542 } 543 #endif 544 545 static void esdhc_set_ios(struct mmc *mmc) 546 { 547 struct fsl_esdhc_cfg *cfg = mmc->priv; 548 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 549 550 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 551 /* Select to use peripheral clock */ 552 esdhc_clock_control(mmc, false); 553 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 554 esdhc_clock_control(mmc, true); 555 #endif 556 /* Set the clock speed */ 557 set_sysctl(mmc, mmc->clock); 558 559 /* Set the bus width */ 560 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 561 562 if (mmc->bus_width == 4) 563 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 564 else if (mmc->bus_width == 8) 565 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 566 567 } 568 569 static int esdhc_init(struct mmc *mmc) 570 { 571 struct fsl_esdhc_cfg *cfg = mmc->priv; 572 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 573 int timeout = 1000; 574 575 /* Reset the entire host controller */ 576 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 577 578 /* Wait until the controller is available */ 579 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 580 udelay(1000); 581 582 #ifndef ARCH_MXC 583 /* Enable cache snooping */ 584 esdhc_write32(®s->scr, 0x00000040); 585 #endif 586 587 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 588 589 /* Set the initial clock speed */ 590 mmc_set_clock(mmc, 400000); 591 592 /* Disable the BRR and BWR bits in IRQSTAT */ 593 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 594 595 /* Put the PROCTL reg back to the default */ 596 esdhc_write32(®s->proctl, PROCTL_INIT); 597 598 /* Set timout to the maximum value */ 599 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 600 601 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 602 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 603 #endif 604 605 return 0; 606 } 607 608 static int esdhc_getcd(struct mmc *mmc) 609 { 610 struct fsl_esdhc_cfg *cfg = mmc->priv; 611 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 612 int timeout = 1000; 613 614 #ifdef CONFIG_ESDHC_DETECT_QUIRK 615 if (CONFIG_ESDHC_DETECT_QUIRK) 616 return 1; 617 #endif 618 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 619 udelay(1000); 620 621 return timeout > 0; 622 } 623 624 static void esdhc_reset(struct fsl_esdhc *regs) 625 { 626 unsigned long timeout = 100; /* wait max 100 ms */ 627 628 /* reset the controller */ 629 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 630 631 /* hardware clears the bit when it is done */ 632 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 633 udelay(1000); 634 if (!timeout) 635 printf("MMC/SD: Reset never completed.\n"); 636 } 637 638 static const struct mmc_ops esdhc_ops = { 639 .send_cmd = esdhc_send_cmd, 640 .set_ios = esdhc_set_ios, 641 .init = esdhc_init, 642 .getcd = esdhc_getcd, 643 }; 644 645 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 646 { 647 struct fsl_esdhc *regs; 648 struct mmc *mmc; 649 u32 caps, voltage_caps; 650 651 if (!cfg) 652 return -1; 653 654 regs = (struct fsl_esdhc *)cfg->esdhc_base; 655 656 /* First reset the eSDHC controller */ 657 esdhc_reset(regs); 658 659 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 660 | SYSCTL_IPGEN | SYSCTL_CKEN); 661 662 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 663 memset(&cfg->cfg, 0, sizeof(cfg->cfg)); 664 665 voltage_caps = 0; 666 caps = esdhc_read32(®s->hostcapblt); 667 668 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 669 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 670 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 671 #endif 672 673 /* T4240 host controller capabilities register should have VS33 bit */ 674 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 675 caps = caps | ESDHC_HOSTCAPBLT_VS33; 676 #endif 677 678 if (caps & ESDHC_HOSTCAPBLT_VS18) 679 voltage_caps |= MMC_VDD_165_195; 680 if (caps & ESDHC_HOSTCAPBLT_VS30) 681 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 682 if (caps & ESDHC_HOSTCAPBLT_VS33) 683 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 684 685 cfg->cfg.name = "FSL_SDHC"; 686 cfg->cfg.ops = &esdhc_ops; 687 #ifdef CONFIG_SYS_SD_VOLTAGE 688 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 689 #else 690 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 691 #endif 692 if ((cfg->cfg.voltages & voltage_caps) == 0) { 693 printf("voltage not supported by controller\n"); 694 return -1; 695 } 696 697 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 698 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 699 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; 700 #endif 701 702 if (cfg->max_bus_width > 0) { 703 if (cfg->max_bus_width < 8) 704 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 705 if (cfg->max_bus_width < 4) 706 cfg->cfg.host_caps &= ~MMC_MODE_4BIT; 707 } 708 709 if (caps & ESDHC_HOSTCAPBLT_HSS) 710 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 711 712 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 713 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 714 cfg->cfg.host_caps &= ~MMC_MODE_8BIT; 715 #endif 716 717 cfg->cfg.f_min = 400000; 718 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); 719 720 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 721 722 mmc = mmc_create(&cfg->cfg, cfg); 723 if (mmc == NULL) 724 return -1; 725 726 return 0; 727 } 728 729 int fsl_esdhc_mmc_init(bd_t *bis) 730 { 731 struct fsl_esdhc_cfg *cfg; 732 733 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 734 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 735 cfg->sdhc_clk = gd->arch.sdhc_clk; 736 return fsl_esdhc_initialize(bis, cfg); 737 } 738 739 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 740 void mmc_adapter_card_type_ident(void) 741 { 742 u8 card_id; 743 u8 value; 744 745 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 746 gd->arch.sdhc_adapter = card_id; 747 748 switch (card_id) { 749 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 750 break; 751 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 752 break; 753 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 754 value = QIXIS_READ(brdcfg[5]); 755 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 756 QIXIS_WRITE(brdcfg[5], value); 757 break; 758 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 759 break; 760 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 761 break; 762 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 763 break; 764 case QIXIS_ESDHC_NO_ADAPTER: 765 break; 766 default: 767 break; 768 } 769 } 770 #endif 771 772 #ifdef CONFIG_OF_LIBFDT 773 void fdt_fixup_esdhc(void *blob, bd_t *bd) 774 { 775 const char *compat = "fsl,esdhc"; 776 777 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 778 if (!hwconfig("esdhc")) { 779 do_fixup_by_compat(blob, compat, "status", "disabled", 780 8 + 1, 1); 781 return; 782 } 783 #endif 784 785 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 786 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 787 gd->arch.sdhc_clk, 1); 788 #else 789 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 790 gd->arch.sdhc_clk, 1); 791 #endif 792 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 793 do_fixup_by_compat_u32(blob, compat, "adapter-type", 794 (u32)(gd->arch.sdhc_adapter), 1); 795 #endif 796 do_fixup_by_compat(blob, compat, "status", "okay", 797 4 + 1, 1); 798 } 799 #endif 800