1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <command.h> 31 #include <hwconfig.h> 32 #include <mmc.h> 33 #include <part.h> 34 #include <malloc.h> 35 #include <mmc.h> 36 #include <fsl_esdhc.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct fsl_esdhc { 43 uint dsaddr; 44 uint blkattr; 45 uint cmdarg; 46 uint xfertyp; 47 uint cmdrsp0; 48 uint cmdrsp1; 49 uint cmdrsp2; 50 uint cmdrsp3; 51 uint datport; 52 uint prsstat; 53 uint proctl; 54 uint sysctl; 55 uint irqstat; 56 uint irqstaten; 57 uint irqsigen; 58 uint autoc12err; 59 uint hostcapblt; 60 uint wml; 61 uint mixctrl; 62 char reserved1[4]; 63 uint fevt; 64 char reserved2[168]; 65 uint hostver; 66 char reserved3[780]; 67 uint scr; 68 }; 69 70 /* Return the XFERTYP flags for a given command and data packet */ 71 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 72 { 73 uint xfertyp = 0; 74 75 if (data) { 76 xfertyp |= XFERTYP_DPSEL; 77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 78 xfertyp |= XFERTYP_DMAEN; 79 #endif 80 if (data->blocks > 1) { 81 xfertyp |= XFERTYP_MSBSEL; 82 xfertyp |= XFERTYP_BCEN; 83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 84 xfertyp |= XFERTYP_AC12EN; 85 #endif 86 } 87 88 if (data->flags & MMC_DATA_READ) 89 xfertyp |= XFERTYP_DTDSEL; 90 } 91 92 if (cmd->resp_type & MMC_RSP_CRC) 93 xfertyp |= XFERTYP_CCCEN; 94 if (cmd->resp_type & MMC_RSP_OPCODE) 95 xfertyp |= XFERTYP_CICEN; 96 if (cmd->resp_type & MMC_RSP_136) 97 xfertyp |= XFERTYP_RSPTYP_136; 98 else if (cmd->resp_type & MMC_RSP_BUSY) 99 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 100 else if (cmd->resp_type & MMC_RSP_PRESENT) 101 xfertyp |= XFERTYP_RSPTYP_48; 102 103 #ifdef CONFIG_MX53 104 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 105 xfertyp |= XFERTYP_CMDTYP_ABORT; 106 #endif 107 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 108 } 109 110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 111 /* 112 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 113 */ 114 static void 115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 116 { 117 struct fsl_esdhc_cfg *cfg = mmc->priv; 118 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 119 uint blocks; 120 char *buffer; 121 uint databuf; 122 uint size; 123 uint irqstat; 124 uint timeout; 125 126 if (data->flags & MMC_DATA_READ) { 127 blocks = data->blocks; 128 buffer = data->dest; 129 while (blocks) { 130 timeout = PIO_TIMEOUT; 131 size = data->blocksize; 132 irqstat = esdhc_read32(®s->irqstat); 133 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 134 && --timeout); 135 if (timeout <= 0) { 136 printf("\nData Read Failed in PIO Mode."); 137 return; 138 } 139 while (size && (!(irqstat & IRQSTAT_TC))) { 140 udelay(100); /* Wait before last byte transfer complete */ 141 irqstat = esdhc_read32(®s->irqstat); 142 databuf = in_le32(®s->datport); 143 *((uint *)buffer) = databuf; 144 buffer += 4; 145 size -= 4; 146 } 147 blocks--; 148 } 149 } else { 150 blocks = data->blocks; 151 buffer = (char *)data->src; 152 while (blocks) { 153 timeout = PIO_TIMEOUT; 154 size = data->blocksize; 155 irqstat = esdhc_read32(®s->irqstat); 156 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 157 && --timeout); 158 if (timeout <= 0) { 159 printf("\nData Write Failed in PIO Mode."); 160 return; 161 } 162 while (size && (!(irqstat & IRQSTAT_TC))) { 163 udelay(100); /* Wait before last byte transfer complete */ 164 databuf = *((uint *)buffer); 165 buffer += 4; 166 size -= 4; 167 irqstat = esdhc_read32(®s->irqstat); 168 out_le32(®s->datport, databuf); 169 } 170 blocks--; 171 } 172 } 173 } 174 #endif 175 176 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 177 { 178 int timeout; 179 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 180 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 181 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 182 uint wml_value; 183 184 wml_value = data->blocksize/4; 185 186 if (data->flags & MMC_DATA_READ) { 187 if (wml_value > WML_RD_WML_MAX) 188 wml_value = WML_RD_WML_MAX_VAL; 189 190 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 191 esdhc_write32(®s->dsaddr, (u32)data->dest); 192 } else { 193 flush_dcache_range((ulong)data->src, 194 (ulong)data->src+data->blocks 195 *data->blocksize); 196 197 if (wml_value > WML_WR_WML_MAX) 198 wml_value = WML_WR_WML_MAX_VAL; 199 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 200 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 201 return TIMEOUT; 202 } 203 204 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 205 wml_value << 16); 206 esdhc_write32(®s->dsaddr, (u32)data->src); 207 } 208 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 209 if (!(data->flags & MMC_DATA_READ)) { 210 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 211 printf("\nThe SD card is locked. " 212 "Can not write to a locked card.\n\n"); 213 return TIMEOUT; 214 } 215 esdhc_write32(®s->dsaddr, (u32)data->src); 216 } else 217 esdhc_write32(®s->dsaddr, (u32)data->dest); 218 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ 219 220 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 221 222 /* Calculate the timeout period for data transactions */ 223 /* 224 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 225 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 226 * So, Number of SD Clock cycles for 0.25sec should be minimum 227 * (SD Clock/sec * 0.25 sec) SD Clock cycles 228 * = (mmc->tran_speed * 1/4) SD Clock cycles 229 * As 1) >= 2) 230 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 231 * Taking log2 both the sides 232 * => timeout + 13 >= log2(mmc->tran_speed/4) 233 * Rounding up to next power of 2 234 * => timeout + 13 = log2(mmc->tran_speed/4) + 1 235 * => timeout + 13 = fls(mmc->tran_speed/4) 236 */ 237 timeout = fls(mmc->tran_speed/4); 238 timeout -= 13; 239 240 if (timeout > 14) 241 timeout = 14; 242 243 if (timeout < 0) 244 timeout = 0; 245 246 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 247 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 248 timeout++; 249 #endif 250 251 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 252 253 return 0; 254 } 255 256 static void check_and_invalidate_dcache_range 257 (struct mmc_cmd *cmd, 258 struct mmc_data *data) { 259 unsigned start = (unsigned)data->dest ; 260 unsigned size = roundup(ARCH_DMA_MINALIGN, 261 data->blocks*data->blocksize); 262 unsigned end = start+size ; 263 invalidate_dcache_range(start, end); 264 } 265 /* 266 * Sends a command out on the bus. Takes the mmc pointer, 267 * a command pointer, and an optional data pointer. 268 */ 269 static int 270 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 271 { 272 uint xfertyp; 273 uint irqstat; 274 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 275 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 276 277 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 278 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 279 return 0; 280 #endif 281 282 esdhc_write32(®s->irqstat, -1); 283 284 sync(); 285 286 /* Wait for the bus to be idle */ 287 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 288 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 289 ; 290 291 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 292 ; 293 294 /* Wait at least 8 SD clock cycles before the next command */ 295 /* 296 * Note: This is way more than 8 cycles, but 1ms seems to 297 * resolve timing issues with some cards 298 */ 299 udelay(1000); 300 301 /* Set up for a data transfer if we have one */ 302 if (data) { 303 int err; 304 305 err = esdhc_setup_data(mmc, data); 306 if(err) 307 return err; 308 } 309 310 /* Figure out the transfer arguments */ 311 xfertyp = esdhc_xfertyp(cmd, data); 312 313 /* Mask all irqs */ 314 esdhc_write32(®s->irqsigen, 0); 315 316 /* Send the command */ 317 esdhc_write32(®s->cmdarg, cmd->cmdarg); 318 #if defined(CONFIG_FSL_USDHC) 319 esdhc_write32(®s->mixctrl, 320 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); 321 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 322 #else 323 esdhc_write32(®s->xfertyp, xfertyp); 324 #endif 325 326 /* Wait for the command to complete */ 327 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 328 ; 329 330 irqstat = esdhc_read32(®s->irqstat); 331 332 /* Reset CMD and DATA portions on error */ 333 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { 334 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 335 SYSCTL_RSTC); 336 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 337 ; 338 339 if (data) { 340 esdhc_write32(®s->sysctl, 341 esdhc_read32(®s->sysctl) | 342 SYSCTL_RSTD); 343 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 344 ; 345 } 346 } 347 348 if (irqstat & CMD_ERR) 349 return COMM_ERR; 350 351 if (irqstat & IRQSTAT_CTOE) 352 return TIMEOUT; 353 354 /* Workaround for ESDHC errata ENGcm03648 */ 355 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 356 int timeout = 2500; 357 358 /* Poll on DATA0 line for cmd with busy signal for 250 ms */ 359 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 360 PRSSTAT_DAT0)) { 361 udelay(100); 362 timeout--; 363 } 364 365 if (timeout <= 0) { 366 printf("Timeout waiting for DAT0 to go high!\n"); 367 return TIMEOUT; 368 } 369 } 370 371 /* Copy the response to the response buffer */ 372 if (cmd->resp_type & MMC_RSP_136) { 373 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 374 375 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 376 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 377 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 378 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 379 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 380 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 381 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 382 cmd->response[3] = (cmdrsp0 << 8); 383 } else 384 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 385 386 /* Wait until all of the blocks are transferred */ 387 if (data) { 388 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 389 esdhc_pio_read_write(mmc, data); 390 #else 391 do { 392 irqstat = esdhc_read32(®s->irqstat); 393 394 if (irqstat & IRQSTAT_DTOE) 395 return TIMEOUT; 396 397 if (irqstat & DATA_ERR) 398 return COMM_ERR; 399 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 400 #endif 401 if (data->flags & MMC_DATA_READ) 402 check_and_invalidate_dcache_range(cmd, data); 403 } 404 405 esdhc_write32(®s->irqstat, -1); 406 407 return 0; 408 } 409 410 static void set_sysctl(struct mmc *mmc, uint clock) 411 { 412 int div, pre_div; 413 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 414 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 415 int sdhc_clk = cfg->sdhc_clk; 416 uint clk; 417 418 if (clock < mmc->f_min) 419 clock = mmc->f_min; 420 421 if (sdhc_clk / 16 > clock) { 422 for (pre_div = 2; pre_div < 256; pre_div *= 2) 423 if ((sdhc_clk / pre_div) <= (clock * 16)) 424 break; 425 } else 426 pre_div = 2; 427 428 for (div = 1; div <= 16; div++) 429 if ((sdhc_clk / (div * pre_div)) <= clock) 430 break; 431 432 pre_div >>= 1; 433 div -= 1; 434 435 clk = (pre_div << 8) | (div << 4); 436 437 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 438 439 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 440 441 udelay(10000); 442 443 clk = SYSCTL_PEREN | SYSCTL_CKEN; 444 445 esdhc_setbits32(®s->sysctl, clk); 446 } 447 448 static void esdhc_set_ios(struct mmc *mmc) 449 { 450 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 451 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 452 453 /* Set the clock speed */ 454 set_sysctl(mmc, mmc->clock); 455 456 /* Set the bus width */ 457 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 458 459 if (mmc->bus_width == 4) 460 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 461 else if (mmc->bus_width == 8) 462 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 463 464 } 465 466 static int esdhc_init(struct mmc *mmc) 467 { 468 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 469 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 470 int timeout = 1000; 471 472 /* Reset the entire host controller */ 473 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 474 475 /* Wait until the controller is available */ 476 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 477 udelay(1000); 478 479 #ifndef ARCH_MXC 480 /* Enable cache snooping */ 481 esdhc_write32(®s->scr, 0x00000040); 482 #endif 483 484 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 485 486 /* Set the initial clock speed */ 487 mmc_set_clock(mmc, 400000); 488 489 /* Disable the BRR and BWR bits in IRQSTAT */ 490 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 491 492 /* Put the PROCTL reg back to the default */ 493 esdhc_write32(®s->proctl, PROCTL_INIT); 494 495 /* Set timout to the maximum value */ 496 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 497 498 return 0; 499 } 500 501 static int esdhc_getcd(struct mmc *mmc) 502 { 503 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 504 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 505 int timeout = 1000; 506 507 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 508 udelay(1000); 509 510 return timeout > 0; 511 } 512 513 static void esdhc_reset(struct fsl_esdhc *regs) 514 { 515 unsigned long timeout = 100; /* wait max 100 ms */ 516 517 /* reset the controller */ 518 esdhc_write32(®s->sysctl, SYSCTL_RSTA); 519 520 /* hardware clears the bit when it is done */ 521 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 522 udelay(1000); 523 if (!timeout) 524 printf("MMC/SD: Reset never completed.\n"); 525 } 526 527 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 528 { 529 struct fsl_esdhc *regs; 530 struct mmc *mmc; 531 u32 caps, voltage_caps; 532 533 if (!cfg) 534 return -1; 535 536 mmc = malloc(sizeof(struct mmc)); 537 538 sprintf(mmc->name, "FSL_SDHC"); 539 regs = (struct fsl_esdhc *)cfg->esdhc_base; 540 541 /* First reset the eSDHC controller */ 542 esdhc_reset(regs); 543 544 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 545 | SYSCTL_IPGEN | SYSCTL_CKEN); 546 547 mmc->priv = cfg; 548 mmc->send_cmd = esdhc_send_cmd; 549 mmc->set_ios = esdhc_set_ios; 550 mmc->init = esdhc_init; 551 mmc->getcd = esdhc_getcd; 552 mmc->getwp = NULL; 553 554 voltage_caps = 0; 555 caps = regs->hostcapblt; 556 557 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 558 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 559 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 560 #endif 561 if (caps & ESDHC_HOSTCAPBLT_VS18) 562 voltage_caps |= MMC_VDD_165_195; 563 if (caps & ESDHC_HOSTCAPBLT_VS30) 564 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 565 if (caps & ESDHC_HOSTCAPBLT_VS33) 566 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 567 568 #ifdef CONFIG_SYS_SD_VOLTAGE 569 mmc->voltages = CONFIG_SYS_SD_VOLTAGE; 570 #else 571 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 572 #endif 573 if ((mmc->voltages & voltage_caps) == 0) { 574 printf("voltage not supported by controller\n"); 575 return -1; 576 } 577 578 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; 579 580 if (cfg->max_bus_width > 0) { 581 if (cfg->max_bus_width < 8) 582 mmc->host_caps &= ~MMC_MODE_8BIT; 583 if (cfg->max_bus_width < 4) 584 mmc->host_caps &= ~MMC_MODE_4BIT; 585 } 586 587 if (caps & ESDHC_HOSTCAPBLT_HSS) 588 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 589 590 mmc->f_min = 400000; 591 mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); 592 593 mmc->b_max = 0; 594 mmc_register(mmc); 595 596 return 0; 597 } 598 599 int fsl_esdhc_mmc_init(bd_t *bis) 600 { 601 struct fsl_esdhc_cfg *cfg; 602 603 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 604 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 605 cfg->sdhc_clk = gd->arch.sdhc_clk; 606 return fsl_esdhc_initialize(bis, cfg); 607 } 608 609 #ifdef CONFIG_OF_LIBFDT 610 void fdt_fixup_esdhc(void *blob, bd_t *bd) 611 { 612 const char *compat = "fsl,esdhc"; 613 614 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 615 if (!hwconfig("esdhc")) { 616 do_fixup_by_compat(blob, compat, "status", "disabled", 617 8 + 1, 1); 618 return; 619 } 620 #endif 621 622 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 623 gd->arch.sdhc_clk, 1); 624 625 do_fixup_by_compat(blob, compat, "status", "okay", 626 4 + 1, 1); 627 } 628 #endif 629