1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the pxa mmc code: 6 * (C) Copyright 2003 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <command.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 #include <dm.h> 24 #include <asm-generic/gpio.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 29 IRQSTATEN_CINT | \ 30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 33 IRQSTATEN_DINT) 34 35 struct fsl_esdhc { 36 uint dsaddr; /* SDMA system address register */ 37 uint blkattr; /* Block attributes register */ 38 uint cmdarg; /* Command argument register */ 39 uint xfertyp; /* Transfer type register */ 40 uint cmdrsp0; /* Command response 0 register */ 41 uint cmdrsp1; /* Command response 1 register */ 42 uint cmdrsp2; /* Command response 2 register */ 43 uint cmdrsp3; /* Command response 3 register */ 44 uint datport; /* Buffer data port register */ 45 uint prsstat; /* Present state register */ 46 uint proctl; /* Protocol control register */ 47 uint sysctl; /* System Control Register */ 48 uint irqstat; /* Interrupt status register */ 49 uint irqstaten; /* Interrupt status enable register */ 50 uint irqsigen; /* Interrupt signal enable register */ 51 uint autoc12err; /* Auto CMD error status register */ 52 uint hostcapblt; /* Host controller capabilities register */ 53 uint wml; /* Watermark level register */ 54 uint mixctrl; /* For USDHC */ 55 char reserved1[4]; /* reserved */ 56 uint fevt; /* Force event register */ 57 uint admaes; /* ADMA error status register */ 58 uint adsaddr; /* ADMA system address register */ 59 char reserved2[100]; /* reserved */ 60 uint vendorspec; /* Vendor Specific register */ 61 char reserved3[56]; /* reserved */ 62 uint hostver; /* Host controller version register */ 63 char reserved4[4]; /* reserved */ 64 uint dmaerraddr; /* DMA error address register */ 65 char reserved5[4]; /* reserved */ 66 uint dmaerrattr; /* DMA error attribute register */ 67 char reserved6[4]; /* reserved */ 68 uint hostcapblt2; /* Host controller capabilities register 2 */ 69 char reserved7[8]; /* reserved */ 70 uint tcr; /* Tuning control register */ 71 char reserved8[28]; /* reserved */ 72 uint sddirctl; /* SD direction control register */ 73 char reserved9[712]; /* reserved */ 74 uint scr; /* eSDHC control register */ 75 }; 76 77 /** 78 * struct fsl_esdhc_priv 79 * 80 * @esdhc_regs: registers of the sdhc controller 81 * @sdhc_clk: Current clk of the sdhc controller 82 * @bus_width: bus width, 1bit, 4bit or 8bit 83 * @cfg: mmc config 84 * @mmc: mmc 85 * Following is used when Driver Model is enabled for MMC 86 * @dev: pointer for the device 87 * @non_removable: 0: removable; 1: non-removable 88 * @cd_gpio: gpio for card detection 89 */ 90 struct fsl_esdhc_priv { 91 struct fsl_esdhc *esdhc_regs; 92 unsigned int sdhc_clk; 93 unsigned int bus_width; 94 struct mmc_config cfg; 95 struct mmc *mmc; 96 struct udevice *dev; 97 int non_removable; 98 struct gpio_desc cd_gpio; 99 }; 100 101 /* Return the XFERTYP flags for a given command and data packet */ 102 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 103 { 104 uint xfertyp = 0; 105 106 if (data) { 107 xfertyp |= XFERTYP_DPSEL; 108 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 109 xfertyp |= XFERTYP_DMAEN; 110 #endif 111 if (data->blocks > 1) { 112 xfertyp |= XFERTYP_MSBSEL; 113 xfertyp |= XFERTYP_BCEN; 114 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 115 xfertyp |= XFERTYP_AC12EN; 116 #endif 117 } 118 119 if (data->flags & MMC_DATA_READ) 120 xfertyp |= XFERTYP_DTDSEL; 121 } 122 123 if (cmd->resp_type & MMC_RSP_CRC) 124 xfertyp |= XFERTYP_CCCEN; 125 if (cmd->resp_type & MMC_RSP_OPCODE) 126 xfertyp |= XFERTYP_CICEN; 127 if (cmd->resp_type & MMC_RSP_136) 128 xfertyp |= XFERTYP_RSPTYP_136; 129 else if (cmd->resp_type & MMC_RSP_BUSY) 130 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 131 else if (cmd->resp_type & MMC_RSP_PRESENT) 132 xfertyp |= XFERTYP_RSPTYP_48; 133 134 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 135 xfertyp |= XFERTYP_CMDTYP_ABORT; 136 137 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 138 } 139 140 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 141 /* 142 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 143 */ 144 static void 145 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) 146 { 147 struct fsl_esdhc_priv *priv = mmc->priv; 148 struct fsl_esdhc *regs = priv->esdhc_regs; 149 uint blocks; 150 char *buffer; 151 uint databuf; 152 uint size; 153 uint irqstat; 154 uint timeout; 155 156 if (data->flags & MMC_DATA_READ) { 157 blocks = data->blocks; 158 buffer = data->dest; 159 while (blocks) { 160 timeout = PIO_TIMEOUT; 161 size = data->blocksize; 162 irqstat = esdhc_read32(®s->irqstat); 163 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) 164 && --timeout); 165 if (timeout <= 0) { 166 printf("\nData Read Failed in PIO Mode."); 167 return; 168 } 169 while (size && (!(irqstat & IRQSTAT_TC))) { 170 udelay(100); /* Wait before last byte transfer complete */ 171 irqstat = esdhc_read32(®s->irqstat); 172 databuf = in_le32(®s->datport); 173 *((uint *)buffer) = databuf; 174 buffer += 4; 175 size -= 4; 176 } 177 blocks--; 178 } 179 } else { 180 blocks = data->blocks; 181 buffer = (char *)data->src; 182 while (blocks) { 183 timeout = PIO_TIMEOUT; 184 size = data->blocksize; 185 irqstat = esdhc_read32(®s->irqstat); 186 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) 187 && --timeout); 188 if (timeout <= 0) { 189 printf("\nData Write Failed in PIO Mode."); 190 return; 191 } 192 while (size && (!(irqstat & IRQSTAT_TC))) { 193 udelay(100); /* Wait before last byte transfer complete */ 194 databuf = *((uint *)buffer); 195 buffer += 4; 196 size -= 4; 197 irqstat = esdhc_read32(®s->irqstat); 198 out_le32(®s->datport, databuf); 199 } 200 blocks--; 201 } 202 } 203 } 204 #endif 205 206 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 207 { 208 int timeout; 209 struct fsl_esdhc_priv *priv = mmc->priv; 210 struct fsl_esdhc *regs = priv->esdhc_regs; 211 #ifdef CONFIG_FSL_LAYERSCAPE 212 dma_addr_t addr; 213 #endif 214 uint wml_value; 215 216 wml_value = data->blocksize/4; 217 218 if (data->flags & MMC_DATA_READ) { 219 if (wml_value > WML_RD_WML_MAX) 220 wml_value = WML_RD_WML_MAX_VAL; 221 222 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); 223 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 224 #ifdef CONFIG_FSL_LAYERSCAPE 225 addr = virt_to_phys((void *)(data->dest)); 226 if (upper_32_bits(addr)) 227 printf("Error found for upper 32 bits\n"); 228 else 229 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 230 #else 231 esdhc_write32(®s->dsaddr, (u32)data->dest); 232 #endif 233 #endif 234 } else { 235 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 236 flush_dcache_range((ulong)data->src, 237 (ulong)data->src+data->blocks 238 *data->blocksize); 239 #endif 240 if (wml_value > WML_WR_WML_MAX) 241 wml_value = WML_WR_WML_MAX_VAL; 242 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { 243 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 244 return TIMEOUT; 245 } 246 247 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, 248 wml_value << 16); 249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 250 #ifdef CONFIG_FSL_LAYERSCAPE 251 addr = virt_to_phys((void *)(data->src)); 252 if (upper_32_bits(addr)) 253 printf("Error found for upper 32 bits\n"); 254 else 255 esdhc_write32(®s->dsaddr, lower_32_bits(addr)); 256 #else 257 esdhc_write32(®s->dsaddr, (u32)data->src); 258 #endif 259 #endif 260 } 261 262 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); 263 264 /* Calculate the timeout period for data transactions */ 265 /* 266 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 267 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 268 * So, Number of SD Clock cycles for 0.25sec should be minimum 269 * (SD Clock/sec * 0.25 sec) SD Clock cycles 270 * = (mmc->clock * 1/4) SD Clock cycles 271 * As 1) >= 2) 272 * => (2^(timeout+13)) >= mmc->clock * 1/4 273 * Taking log2 both the sides 274 * => timeout + 13 >= log2(mmc->clock/4) 275 * Rounding up to next power of 2 276 * => timeout + 13 = log2(mmc->clock/4) + 1 277 * => timeout + 13 = fls(mmc->clock/4) 278 * 279 * However, the MMC spec "It is strongly recommended for hosts to 280 * implement more than 500ms timeout value even if the card 281 * indicates the 250ms maximum busy length." Even the previous 282 * value of 300ms is known to be insufficient for some cards. 283 * So, we use 284 * => timeout + 13 = fls(mmc->clock/2) 285 */ 286 timeout = fls(mmc->clock/2); 287 timeout -= 13; 288 289 if (timeout > 14) 290 timeout = 14; 291 292 if (timeout < 0) 293 timeout = 0; 294 295 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 296 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 297 timeout++; 298 #endif 299 300 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 301 timeout = 0xE; 302 #endif 303 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 304 305 return 0; 306 } 307 308 static void check_and_invalidate_dcache_range 309 (struct mmc_cmd *cmd, 310 struct mmc_data *data) { 311 unsigned start = 0; 312 unsigned end = 0; 313 unsigned size = roundup(ARCH_DMA_MINALIGN, 314 data->blocks*data->blocksize); 315 #ifdef CONFIG_FSL_LAYERSCAPE 316 dma_addr_t addr; 317 318 addr = virt_to_phys((void *)(data->dest)); 319 if (upper_32_bits(addr)) 320 printf("Error found for upper 32 bits\n"); 321 else 322 start = lower_32_bits(addr); 323 #else 324 start = (unsigned)data->dest; 325 #endif 326 end = start + size; 327 invalidate_dcache_range(start, end); 328 } 329 330 /* 331 * Sends a command out on the bus. Takes the mmc pointer, 332 * a command pointer, and an optional data pointer. 333 */ 334 static int 335 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 336 { 337 int err = 0; 338 uint xfertyp; 339 uint irqstat; 340 struct fsl_esdhc_priv *priv = mmc->priv; 341 struct fsl_esdhc *regs = priv->esdhc_regs; 342 343 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 344 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 345 return 0; 346 #endif 347 348 esdhc_write32(®s->irqstat, -1); 349 350 sync(); 351 352 /* Wait for the bus to be idle */ 353 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || 354 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) 355 ; 356 357 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) 358 ; 359 360 /* Wait at least 8 SD clock cycles before the next command */ 361 /* 362 * Note: This is way more than 8 cycles, but 1ms seems to 363 * resolve timing issues with some cards 364 */ 365 udelay(1000); 366 367 /* Set up for a data transfer if we have one */ 368 if (data) { 369 err = esdhc_setup_data(mmc, data); 370 if(err) 371 return err; 372 373 if (data->flags & MMC_DATA_READ) 374 check_and_invalidate_dcache_range(cmd, data); 375 } 376 377 /* Figure out the transfer arguments */ 378 xfertyp = esdhc_xfertyp(cmd, data); 379 380 /* Mask all irqs */ 381 esdhc_write32(®s->irqsigen, 0); 382 383 /* Send the command */ 384 esdhc_write32(®s->cmdarg, cmd->cmdarg); 385 #if defined(CONFIG_FSL_USDHC) 386 esdhc_write32(®s->mixctrl, 387 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 388 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 389 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); 390 #else 391 esdhc_write32(®s->xfertyp, xfertyp); 392 #endif 393 394 /* Wait for the command to complete */ 395 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) 396 ; 397 398 irqstat = esdhc_read32(®s->irqstat); 399 400 if (irqstat & CMD_ERR) { 401 err = COMM_ERR; 402 goto out; 403 } 404 405 if (irqstat & IRQSTAT_CTOE) { 406 err = TIMEOUT; 407 goto out; 408 } 409 410 /* Switch voltage to 1.8V if CMD11 succeeded */ 411 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 412 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 413 414 printf("Run CMD11 1.8V switch\n"); 415 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 416 udelay(5000); 417 } 418 419 /* Workaround for ESDHC errata ENGcm03648 */ 420 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 421 int timeout = 6000; 422 423 /* Poll on DATA0 line for cmd with busy signal for 600 ms */ 424 while (timeout > 0 && !(esdhc_read32(®s->prsstat) & 425 PRSSTAT_DAT0)) { 426 udelay(100); 427 timeout--; 428 } 429 430 if (timeout <= 0) { 431 printf("Timeout waiting for DAT0 to go high!\n"); 432 err = TIMEOUT; 433 goto out; 434 } 435 } 436 437 /* Copy the response to the response buffer */ 438 if (cmd->resp_type & MMC_RSP_136) { 439 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 440 441 cmdrsp3 = esdhc_read32(®s->cmdrsp3); 442 cmdrsp2 = esdhc_read32(®s->cmdrsp2); 443 cmdrsp1 = esdhc_read32(®s->cmdrsp1); 444 cmdrsp0 = esdhc_read32(®s->cmdrsp0); 445 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 446 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 447 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 448 cmd->response[3] = (cmdrsp0 << 8); 449 } else 450 cmd->response[0] = esdhc_read32(®s->cmdrsp0); 451 452 /* Wait until all of the blocks are transferred */ 453 if (data) { 454 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 455 esdhc_pio_read_write(mmc, data); 456 #else 457 do { 458 irqstat = esdhc_read32(®s->irqstat); 459 460 if (irqstat & IRQSTAT_DTOE) { 461 err = TIMEOUT; 462 goto out; 463 } 464 465 if (irqstat & DATA_ERR) { 466 err = COMM_ERR; 467 goto out; 468 } 469 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); 470 471 /* 472 * Need invalidate the dcache here again to avoid any 473 * cache-fill during the DMA operations such as the 474 * speculative pre-fetching etc. 475 */ 476 if (data->flags & MMC_DATA_READ) 477 check_and_invalidate_dcache_range(cmd, data); 478 #endif 479 } 480 481 out: 482 /* Reset CMD and DATA portions on error */ 483 if (err) { 484 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | 485 SYSCTL_RSTC); 486 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) 487 ; 488 489 if (data) { 490 esdhc_write32(®s->sysctl, 491 esdhc_read32(®s->sysctl) | 492 SYSCTL_RSTD); 493 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) 494 ; 495 } 496 497 /* If this was CMD11, then notify that power cycle is needed */ 498 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 499 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 500 } 501 502 esdhc_write32(®s->irqstat, -1); 503 504 return err; 505 } 506 507 static void set_sysctl(struct mmc *mmc, uint clock) 508 { 509 int div, pre_div; 510 struct fsl_esdhc_priv *priv = mmc->priv; 511 struct fsl_esdhc *regs = priv->esdhc_regs; 512 int sdhc_clk = priv->sdhc_clk; 513 uint clk; 514 515 if (clock < mmc->cfg->f_min) 516 clock = mmc->cfg->f_min; 517 518 if (sdhc_clk / 16 > clock) { 519 for (pre_div = 2; pre_div < 256; pre_div *= 2) 520 if ((sdhc_clk / pre_div) <= (clock * 16)) 521 break; 522 } else 523 pre_div = 2; 524 525 for (div = 1; div <= 16; div++) 526 if ((sdhc_clk / (div * pre_div)) <= clock) 527 break; 528 529 pre_div >>= mmc->ddr_mode ? 2 : 1; 530 div -= 1; 531 532 clk = (pre_div << 8) | (div << 4); 533 534 #ifdef CONFIG_FSL_USDHC 535 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 536 #else 537 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); 538 #endif 539 540 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); 541 542 udelay(10000); 543 544 #ifdef CONFIG_FSL_USDHC 545 esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); 546 #else 547 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 548 #endif 549 550 } 551 552 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 553 static void esdhc_clock_control(struct mmc *mmc, bool enable) 554 { 555 struct fsl_esdhc_priv *priv = mmc->priv; 556 struct fsl_esdhc *regs = priv->esdhc_regs; 557 u32 value; 558 u32 time_out; 559 560 value = esdhc_read32(®s->sysctl); 561 562 if (enable) 563 value |= SYSCTL_CKEN; 564 else 565 value &= ~SYSCTL_CKEN; 566 567 esdhc_write32(®s->sysctl, value); 568 569 time_out = 20; 570 value = PRSSTAT_SDSTB; 571 while (!(esdhc_read32(®s->prsstat) & value)) { 572 if (time_out == 0) { 573 printf("fsl_esdhc: Internal clock never stabilised.\n"); 574 break; 575 } 576 time_out--; 577 mdelay(1); 578 } 579 } 580 #endif 581 582 static void esdhc_set_ios(struct mmc *mmc) 583 { 584 struct fsl_esdhc_priv *priv = mmc->priv; 585 struct fsl_esdhc *regs = priv->esdhc_regs; 586 587 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 588 /* Select to use peripheral clock */ 589 esdhc_clock_control(mmc, false); 590 esdhc_setbits32(®s->scr, ESDHCCTL_PCS); 591 esdhc_clock_control(mmc, true); 592 #endif 593 /* Set the clock speed */ 594 set_sysctl(mmc, mmc->clock); 595 596 /* Set the bus width */ 597 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 598 599 if (mmc->bus_width == 4) 600 esdhc_setbits32(®s->proctl, PROCTL_DTW_4); 601 else if (mmc->bus_width == 8) 602 esdhc_setbits32(®s->proctl, PROCTL_DTW_8); 603 604 } 605 606 static int esdhc_init(struct mmc *mmc) 607 { 608 struct fsl_esdhc_priv *priv = mmc->priv; 609 struct fsl_esdhc *regs = priv->esdhc_regs; 610 int timeout = 1000; 611 612 /* Reset the entire host controller */ 613 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 614 615 /* Wait until the controller is available */ 616 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 617 udelay(1000); 618 619 #ifndef ARCH_MXC 620 /* Enable cache snooping */ 621 esdhc_write32(®s->scr, 0x00000040); 622 #endif 623 624 #ifndef CONFIG_FSL_USDHC 625 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 626 #endif 627 628 /* Set the initial clock speed */ 629 mmc_set_clock(mmc, 400000); 630 631 /* Disable the BRR and BWR bits in IRQSTAT */ 632 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 633 634 /* Put the PROCTL reg back to the default */ 635 esdhc_write32(®s->proctl, PROCTL_INIT); 636 637 /* Set timout to the maximum value */ 638 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 639 640 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT 641 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); 642 #endif 643 644 return 0; 645 } 646 647 static int esdhc_getcd(struct mmc *mmc) 648 { 649 struct fsl_esdhc_priv *priv = mmc->priv; 650 struct fsl_esdhc *regs = priv->esdhc_regs; 651 int timeout = 1000; 652 653 #ifdef CONFIG_ESDHC_DETECT_QUIRK 654 if (CONFIG_ESDHC_DETECT_QUIRK) 655 return 1; 656 #endif 657 658 #ifdef CONFIG_DM_MMC 659 if (priv->non_removable) 660 return 1; 661 662 if (dm_gpio_is_valid(&priv->cd_gpio)) 663 return dm_gpio_get_value(&priv->cd_gpio); 664 #endif 665 666 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) 667 udelay(1000); 668 669 return timeout > 0; 670 } 671 672 static void esdhc_reset(struct fsl_esdhc *regs) 673 { 674 unsigned long timeout = 100; /* wait max 100 ms */ 675 676 /* reset the controller */ 677 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); 678 679 /* hardware clears the bit when it is done */ 680 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) 681 udelay(1000); 682 if (!timeout) 683 printf("MMC/SD: Reset never completed.\n"); 684 } 685 686 static const struct mmc_ops esdhc_ops = { 687 .send_cmd = esdhc_send_cmd, 688 .set_ios = esdhc_set_ios, 689 .init = esdhc_init, 690 .getcd = esdhc_getcd, 691 }; 692 693 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 694 struct fsl_esdhc_priv *priv) 695 { 696 if (!cfg || !priv) 697 return -EINVAL; 698 699 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 700 priv->bus_width = cfg->max_bus_width; 701 priv->sdhc_clk = cfg->sdhc_clk; 702 703 return 0; 704 }; 705 706 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) 707 { 708 struct fsl_esdhc *regs; 709 struct mmc *mmc; 710 u32 caps, voltage_caps; 711 712 if (!priv) 713 return -EINVAL; 714 715 regs = priv->esdhc_regs; 716 717 /* First reset the eSDHC controller */ 718 esdhc_reset(regs); 719 720 #ifndef CONFIG_FSL_USDHC 721 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 722 | SYSCTL_IPGEN | SYSCTL_CKEN); 723 #endif 724 725 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); 726 memset(&priv->cfg, 0, sizeof(priv->cfg)); 727 728 voltage_caps = 0; 729 caps = esdhc_read32(®s->hostcapblt); 730 731 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 732 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 733 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 734 #endif 735 736 /* T4240 host controller capabilities register should have VS33 bit */ 737 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 738 caps = caps | ESDHC_HOSTCAPBLT_VS33; 739 #endif 740 741 if (caps & ESDHC_HOSTCAPBLT_VS18) 742 voltage_caps |= MMC_VDD_165_195; 743 if (caps & ESDHC_HOSTCAPBLT_VS30) 744 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 745 if (caps & ESDHC_HOSTCAPBLT_VS33) 746 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 747 748 priv->cfg.name = "FSL_SDHC"; 749 priv->cfg.ops = &esdhc_ops; 750 #ifdef CONFIG_SYS_SD_VOLTAGE 751 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; 752 #else 753 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 754 #endif 755 if ((priv->cfg.voltages & voltage_caps) == 0) { 756 printf("voltage not supported by controller\n"); 757 return -1; 758 } 759 760 if (priv->bus_width == 8) 761 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 762 else if (priv->bus_width == 4) 763 priv->cfg.host_caps = MMC_MODE_4BIT; 764 765 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 766 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 767 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; 768 #endif 769 770 if (priv->bus_width > 0) { 771 if (priv->bus_width < 8) 772 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 773 if (priv->bus_width < 4) 774 priv->cfg.host_caps &= ~MMC_MODE_4BIT; 775 } 776 777 if (caps & ESDHC_HOSTCAPBLT_HSS) 778 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 779 780 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 781 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 782 priv->cfg.host_caps &= ~MMC_MODE_8BIT; 783 #endif 784 785 priv->cfg.f_min = 400000; 786 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); 787 788 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 789 790 mmc = mmc_create(&priv->cfg, priv); 791 if (mmc == NULL) 792 return -1; 793 794 priv->mmc = mmc; 795 796 return 0; 797 } 798 799 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 800 { 801 struct fsl_esdhc_priv *priv; 802 int ret; 803 804 if (!cfg) 805 return -EINVAL; 806 807 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 808 if (!priv) 809 return -ENOMEM; 810 811 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 812 if (ret) { 813 debug("%s xlate failure\n", __func__); 814 free(priv); 815 return ret; 816 } 817 818 ret = fsl_esdhc_init(priv); 819 if (ret) { 820 debug("%s init failure\n", __func__); 821 free(priv); 822 return ret; 823 } 824 825 return 0; 826 } 827 828 int fsl_esdhc_mmc_init(bd_t *bis) 829 { 830 struct fsl_esdhc_cfg *cfg; 831 832 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 833 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 834 cfg->sdhc_clk = gd->arch.sdhc_clk; 835 return fsl_esdhc_initialize(bis, cfg); 836 } 837 838 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 839 void mmc_adapter_card_type_ident(void) 840 { 841 u8 card_id; 842 u8 value; 843 844 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 845 gd->arch.sdhc_adapter = card_id; 846 847 switch (card_id) { 848 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 849 value = QIXIS_READ(brdcfg[5]); 850 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 851 QIXIS_WRITE(brdcfg[5], value); 852 break; 853 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 854 value = QIXIS_READ(pwr_ctl[1]); 855 value |= QIXIS_EVDD_BY_SDHC_VS; 856 QIXIS_WRITE(pwr_ctl[1], value); 857 break; 858 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 859 value = QIXIS_READ(brdcfg[5]); 860 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 861 QIXIS_WRITE(brdcfg[5], value); 862 break; 863 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 864 break; 865 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 866 break; 867 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 868 break; 869 case QIXIS_ESDHC_NO_ADAPTER: 870 break; 871 default: 872 break; 873 } 874 } 875 #endif 876 877 #ifdef CONFIG_OF_LIBFDT 878 void fdt_fixup_esdhc(void *blob, bd_t *bd) 879 { 880 const char *compat = "fsl,esdhc"; 881 882 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 883 if (!hwconfig("esdhc")) { 884 do_fixup_by_compat(blob, compat, "status", "disabled", 885 8 + 1, 1); 886 return; 887 } 888 #endif 889 890 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 891 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 892 gd->arch.sdhc_clk, 1); 893 #else 894 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 895 gd->arch.sdhc_clk, 1); 896 #endif 897 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 898 do_fixup_by_compat_u32(blob, compat, "adapter-type", 899 (u32)(gd->arch.sdhc_adapter), 1); 900 #endif 901 do_fixup_by_compat(blob, compat, "status", "okay", 902 4 + 1, 1); 903 } 904 #endif 905 906 #ifdef CONFIG_DM_MMC 907 #include <asm/arch/clock.h> 908 static int fsl_esdhc_probe(struct udevice *dev) 909 { 910 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 911 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 912 const void *fdt = gd->fdt_blob; 913 int node = dev->of_offset; 914 fdt_addr_t addr; 915 unsigned int val; 916 int ret; 917 918 addr = dev_get_addr(dev); 919 if (addr == FDT_ADDR_T_NONE) 920 return -EINVAL; 921 922 priv->esdhc_regs = (struct fsl_esdhc *)addr; 923 priv->dev = dev; 924 925 val = fdtdec_get_int(fdt, node, "bus-width", -1); 926 if (val == 8) 927 priv->bus_width = 8; 928 else if (val == 4) 929 priv->bus_width = 4; 930 else 931 priv->bus_width = 1; 932 933 if (fdt_get_property(fdt, node, "non-removable", NULL)) { 934 priv->non_removable = 1; 935 } else { 936 priv->non_removable = 0; 937 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, 938 &priv->cd_gpio, GPIOD_IS_IN); 939 } 940 941 /* 942 * TODO: 943 * Because lack of clk driver, if SDHC clk is not enabled, 944 * need to enable it first before this driver is invoked. 945 * 946 * we use MXC_ESDHC_CLK to get clk freq. 947 * If one would like to make this function work, 948 * the aliases should be provided in dts as this: 949 * 950 * aliases { 951 * mmc0 = &usdhc1; 952 * mmc1 = &usdhc2; 953 * mmc2 = &usdhc3; 954 * mmc3 = &usdhc4; 955 * }; 956 * Then if your board only supports mmc2 and mmc3, but we can 957 * correctly get the seq as 2 and 3, then let mxc_get_clock 958 * work as expected. 959 */ 960 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 961 if (priv->sdhc_clk <= 0) { 962 dev_err(dev, "Unable to get clk for %s\n", dev->name); 963 return -EINVAL; 964 } 965 966 ret = fsl_esdhc_init(priv); 967 if (ret) { 968 dev_err(dev, "fsl_esdhc_init failure\n"); 969 return ret; 970 } 971 972 upriv->mmc = priv->mmc; 973 974 return 0; 975 } 976 977 static const struct udevice_id fsl_esdhc_ids[] = { 978 { .compatible = "fsl,imx6ul-usdhc", }, 979 { .compatible = "fsl,imx6sx-usdhc", }, 980 { .compatible = "fsl,imx6sl-usdhc", }, 981 { .compatible = "fsl,imx6q-usdhc", }, 982 { .compatible = "fsl,imx7d-usdhc", }, 983 { /* sentinel */ } 984 }; 985 986 U_BOOT_DRIVER(fsl_esdhc) = { 987 .name = "fsl-esdhc-mmc", 988 .id = UCLASS_MMC, 989 .of_match = fsl_esdhc_ids, 990 .probe = fsl_esdhc_probe, 991 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 992 }; 993 #endif 994