1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dwmmc.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <malloc.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/power.h> 17 #include <asm/gpio.h> 18 #include <asm-generic/errno.h> 19 20 #define DWMMC_MAX_CH_NUM 4 21 #define DWMMC_MAX_FREQ 52000000 22 #define DWMMC_MIN_FREQ 400000 23 #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 24 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 25 26 /* Exynos implmentation specific drver private data */ 27 struct dwmci_exynos_priv_data { 28 u32 sdr_timing; 29 }; 30 31 /* 32 * Function used as callback function to initialise the 33 * CLKSEL register for every mmc channel. 34 */ 35 static void exynos_dwmci_clksel(struct dwmci_host *host) 36 { 37 struct dwmci_exynos_priv_data *priv = host->priv; 38 39 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); 40 } 41 42 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) 43 { 44 unsigned long sclk; 45 int8_t clk_div; 46 47 /* 48 * Since SDCLKIN is divided inside controller by the DIVRATIO 49 * value set in the CLKSEL register, we need to use the same output 50 * clock value to calculate the CLKDIV value. 51 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) 52 */ 53 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) 54 & DWMCI_DIVRATIO_MASK) + 1; 55 sclk = get_mmc_clk(host->dev_index); 56 57 /* 58 * Assume to know divider value. 59 * When clock unit is broken, need to set "host->div" 60 */ 61 return sclk / clk_div / (host->div + 1); 62 } 63 64 static void exynos_dwmci_board_init(struct dwmci_host *host) 65 { 66 struct dwmci_exynos_priv_data *priv = host->priv; 67 68 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 69 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 70 dwmci_writel(host, EMMCP_SEND0, 0); 71 dwmci_writel(host, EMMCP_CTRL0, 72 MPSCTRL_SECURE_READ_BIT | 73 MPSCTRL_SECURE_WRITE_BIT | 74 MPSCTRL_NON_SECURE_READ_BIT | 75 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 76 } 77 78 /* Set to timing value at initial time */ 79 if (priv->sdr_timing) 80 exynos_dwmci_clksel(host); 81 } 82 83 static int exynos_dwmci_core_init(struct dwmci_host *host, int index) 84 { 85 unsigned int div; 86 unsigned long freq, sclk; 87 struct dwmci_exynos_priv_data *priv = host->priv; 88 89 if (host->bus_hz) 90 freq = host->bus_hz; 91 else 92 freq = DWMMC_MAX_FREQ; 93 94 /* request mmc clock vlaue of 52MHz. */ 95 sclk = get_mmc_clk(index); 96 div = DIV_ROUND_UP(sclk, freq); 97 /* set the clock divisor for mmc */ 98 set_mmc_clk(index, div); 99 100 host->name = "EXYNOS DWMMC"; 101 #ifdef CONFIG_EXYNOS5420 102 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 103 #endif 104 host->board_init = exynos_dwmci_board_init; 105 106 if (!priv->sdr_timing) { 107 if (index == 0) 108 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 109 else if (index == 2) 110 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 111 } 112 113 host->caps = MMC_MODE_DDR_52MHz; 114 host->clksel = exynos_dwmci_clksel; 115 host->dev_index = index; 116 host->get_mmc_clk = exynos_dwmci_get_clk; 117 /* Add the mmc channel to be registered with mmc core */ 118 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 119 printf("DWMMC%d registration failed\n", index); 120 return -1; 121 } 122 return 0; 123 } 124 125 /* 126 * This function adds the mmc channel to be registered with mmc core. 127 * index - mmc channel number. 128 * regbase - register base address of mmc channel specified in 'index'. 129 * bus_width - operating bus width of mmc channel specified in 'index'. 130 * clksel - value to be written into CLKSEL register in case of FDT. 131 * NULL in case od non-FDT. 132 */ 133 int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) 134 { 135 struct dwmci_host *host = NULL; 136 struct dwmci_exynos_priv_data *priv; 137 138 host = malloc(sizeof(struct dwmci_host)); 139 if (!host) { 140 error("dwmci_host malloc fail!\n"); 141 return -ENOMEM; 142 } 143 144 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 145 if (!priv) { 146 error("dwmci_exynos_priv_data malloc fail!\n"); 147 return -ENOMEM; 148 } 149 150 host->ioaddr = (void *)regbase; 151 host->buswidth = bus_width; 152 153 if (clksel) 154 priv->sdr_timing = clksel; 155 156 host->priv = priv; 157 158 return exynos_dwmci_core_init(host, index); 159 } 160 161 #ifdef CONFIG_OF_CONTROL 162 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; 163 164 static int do_dwmci_init(struct dwmci_host *host) 165 { 166 int index, flag, err; 167 168 index = host->dev_index; 169 170 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 171 err = exynos_pinmux_config(host->dev_id, flag); 172 if (err) { 173 printf("DWMMC%d not configure\n", index); 174 return err; 175 } 176 177 return exynos_dwmci_core_init(host, index); 178 } 179 180 static int exynos_dwmci_get_config(const void *blob, int node, 181 struct dwmci_host *host) 182 { 183 int err = 0; 184 u32 base, timing[3]; 185 struct dwmci_exynos_priv_data *priv; 186 187 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 188 if (!priv) { 189 error("dwmci_exynos_priv_data malloc fail!\n"); 190 return -ENOMEM; 191 } 192 193 /* Extract device id for each mmc channel */ 194 host->dev_id = pinmux_decode_periph_id(blob, node); 195 196 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); 197 if (host->dev_index == host->dev_id) 198 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; 199 200 /* Get the bus width from the device node */ 201 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 202 if (host->buswidth <= 0) { 203 printf("DWMMC%d: Can't get bus-width\n", host->dev_index); 204 return -EINVAL; 205 } 206 207 /* Set the base address from the device node */ 208 base = fdtdec_get_addr(blob, node, "reg"); 209 if (!base) { 210 printf("DWMMC%d: Can't get base address\n", host->dev_index); 211 return -EINVAL; 212 } 213 host->ioaddr = (void *)base; 214 215 /* Extract the timing info from the node */ 216 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); 217 if (err) { 218 printf("DWMMC%d: Can't get sdr-timings for devider\n", 219 host->dev_index); 220 return -EINVAL; 221 } 222 223 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 224 DWMCI_SET_DRV_CLK(timing[1]) | 225 DWMCI_SET_DIV_RATIO(timing[2])); 226 227 /* sdr_timing didn't assigned anything, use the default value */ 228 if (!priv->sdr_timing) { 229 if (host->dev_index == 0) 230 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 231 else if (host->dev_index == 2) 232 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 233 } 234 235 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); 236 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); 237 host->div = fdtdec_get_int(blob, node, "div", 0); 238 239 host->priv = priv; 240 241 return 0; 242 } 243 244 static int exynos_dwmci_process_node(const void *blob, 245 int node_list[], int count) 246 { 247 struct dwmci_host *host; 248 int i, node, err; 249 250 for (i = 0; i < count; i++) { 251 node = node_list[i]; 252 if (node <= 0) 253 continue; 254 host = &dwmci_host[i]; 255 err = exynos_dwmci_get_config(blob, node, host); 256 if (err) { 257 printf("%s: failed to decode dev %d\n", __func__, i); 258 return err; 259 } 260 261 do_dwmci_init(host); 262 } 263 return 0; 264 } 265 266 int exynos_dwmmc_init(const void *blob) 267 { 268 int compat_id; 269 int node_list[DWMMC_MAX_CH_NUM]; 270 int boot_dev_node; 271 int err = 0, count; 272 273 compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; 274 275 count = fdtdec_find_aliases_for_id(blob, "mmc", 276 compat_id, node_list, DWMMC_MAX_CH_NUM); 277 278 /* For DWMMC always set boot device as mmc 0 */ 279 if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) { 280 boot_dev_node = node_list[2]; 281 node_list[2] = node_list[0]; 282 node_list[0] = boot_dev_node; 283 } 284 285 err = exynos_dwmci_process_node(blob, node_list, count); 286 287 return err; 288 } 289 #endif 290