1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 */ 6 7 #include <common.h> 8 #include <dwmmc.h> 9 #include <fdtdec.h> 10 #include <linux/libfdt.h> 11 #include <malloc.h> 12 #include <errno.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/power.h> 17 #include <asm/gpio.h> 18 19 #define DWMMC_MAX_CH_NUM 4 20 #define DWMMC_MAX_FREQ 52000000 21 #define DWMMC_MIN_FREQ 400000 22 #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 23 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 24 25 #ifdef CONFIG_DM_MMC 26 #include <dm.h> 27 DECLARE_GLOBAL_DATA_PTR; 28 29 struct exynos_mmc_plat { 30 struct mmc_config cfg; 31 struct mmc mmc; 32 }; 33 #endif 34 35 /* Exynos implmentation specific drver private data */ 36 struct dwmci_exynos_priv_data { 37 #ifdef CONFIG_DM_MMC 38 struct dwmci_host host; 39 #endif 40 u32 sdr_timing; 41 }; 42 43 /* 44 * Function used as callback function to initialise the 45 * CLKSEL register for every mmc channel. 46 */ 47 static void exynos_dwmci_clksel(struct dwmci_host *host) 48 { 49 #ifdef CONFIG_DM_MMC 50 struct dwmci_exynos_priv_data *priv = 51 container_of(host, struct dwmci_exynos_priv_data, host); 52 #else 53 struct dwmci_exynos_priv_data *priv = host->priv; 54 #endif 55 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); 56 } 57 58 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) 59 { 60 unsigned long sclk; 61 int8_t clk_div; 62 63 /* 64 * Since SDCLKIN is divided inside controller by the DIVRATIO 65 * value set in the CLKSEL register, we need to use the same output 66 * clock value to calculate the CLKDIV value. 67 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) 68 */ 69 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) 70 & DWMCI_DIVRATIO_MASK) + 1; 71 sclk = get_mmc_clk(host->dev_index); 72 73 /* 74 * Assume to know divider value. 75 * When clock unit is broken, need to set "host->div" 76 */ 77 return sclk / clk_div / (host->div + 1); 78 } 79 80 static void exynos_dwmci_board_init(struct dwmci_host *host) 81 { 82 struct dwmci_exynos_priv_data *priv = host->priv; 83 84 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 85 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 86 dwmci_writel(host, EMMCP_SEND0, 0); 87 dwmci_writel(host, EMMCP_CTRL0, 88 MPSCTRL_SECURE_READ_BIT | 89 MPSCTRL_SECURE_WRITE_BIT | 90 MPSCTRL_NON_SECURE_READ_BIT | 91 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 92 } 93 94 /* Set to timing value at initial time */ 95 if (priv->sdr_timing) 96 exynos_dwmci_clksel(host); 97 } 98 99 static int exynos_dwmci_core_init(struct dwmci_host *host) 100 { 101 unsigned int div; 102 unsigned long freq, sclk; 103 104 if (host->bus_hz) 105 freq = host->bus_hz; 106 else 107 freq = DWMMC_MAX_FREQ; 108 109 /* request mmc clock vlaue of 52MHz. */ 110 sclk = get_mmc_clk(host->dev_index); 111 div = DIV_ROUND_UP(sclk, freq); 112 /* set the clock divisor for mmc */ 113 set_mmc_clk(host->dev_index, div); 114 115 host->name = "EXYNOS DWMMC"; 116 #ifdef CONFIG_EXYNOS5420 117 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 118 #endif 119 host->board_init = exynos_dwmci_board_init; 120 121 host->caps = MMC_MODE_DDR_52MHz; 122 host->clksel = exynos_dwmci_clksel; 123 host->get_mmc_clk = exynos_dwmci_get_clk; 124 125 #ifndef CONFIG_DM_MMC 126 /* Add the mmc channel to be registered with mmc core */ 127 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 128 printf("DWMMC%d registration failed\n", host->dev_index); 129 return -1; 130 } 131 #endif 132 133 return 0; 134 } 135 136 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; 137 138 static int do_dwmci_init(struct dwmci_host *host) 139 { 140 int flag, err; 141 142 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 143 err = exynos_pinmux_config(host->dev_id, flag); 144 if (err) { 145 printf("DWMMC%d not configure\n", host->dev_index); 146 return err; 147 } 148 149 return exynos_dwmci_core_init(host); 150 } 151 152 static int exynos_dwmci_get_config(const void *blob, int node, 153 struct dwmci_host *host, 154 struct dwmci_exynos_priv_data *priv) 155 { 156 int err = 0; 157 u32 base, timing[3]; 158 159 /* Extract device id for each mmc channel */ 160 host->dev_id = pinmux_decode_periph_id(blob, node); 161 162 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); 163 if (host->dev_index == host->dev_id) 164 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; 165 166 if (host->dev_index > 4) { 167 printf("DWMMC%d: Can't get the dev index\n", host->dev_index); 168 return -EINVAL; 169 } 170 171 /* Get the bus width from the device node (Default is 4bit buswidth) */ 172 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); 173 174 /* Set the base address from the device node */ 175 base = fdtdec_get_addr(blob, node, "reg"); 176 if (!base) { 177 printf("DWMMC%d: Can't get base address\n", host->dev_index); 178 return -EINVAL; 179 } 180 host->ioaddr = (void *)base; 181 182 /* Extract the timing info from the node */ 183 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); 184 if (err) { 185 printf("DWMMC%d: Can't get sdr-timings for devider\n", 186 host->dev_index); 187 return -EINVAL; 188 } 189 190 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 191 DWMCI_SET_DRV_CLK(timing[1]) | 192 DWMCI_SET_DIV_RATIO(timing[2])); 193 194 /* sdr_timing didn't assigned anything, use the default value */ 195 if (!priv->sdr_timing) { 196 if (host->dev_index == 0) 197 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 198 else if (host->dev_index == 2) 199 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 200 } 201 202 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); 203 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); 204 host->div = fdtdec_get_int(blob, node, "div", 0); 205 206 return 0; 207 } 208 209 static int exynos_dwmci_process_node(const void *blob, 210 int node_list[], int count) 211 { 212 struct dwmci_exynos_priv_data *priv; 213 struct dwmci_host *host; 214 int i, node, err; 215 216 for (i = 0; i < count; i++) { 217 node = node_list[i]; 218 if (node <= 0) 219 continue; 220 host = &dwmci_host[i]; 221 222 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 223 if (!priv) { 224 pr_err("dwmci_exynos_priv_data malloc fail!\n"); 225 return -ENOMEM; 226 } 227 228 err = exynos_dwmci_get_config(blob, node, host, priv); 229 if (err) { 230 printf("%s: failed to decode dev %d\n", __func__, i); 231 free(priv); 232 return err; 233 } 234 host->priv = priv; 235 236 do_dwmci_init(host); 237 } 238 return 0; 239 } 240 241 int exynos_dwmmc_init(const void *blob) 242 { 243 int node_list[DWMMC_MAX_CH_NUM]; 244 int boot_dev_node; 245 int err = 0, count; 246 247 count = fdtdec_find_aliases_for_id(blob, "mmc", 248 COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list, 249 DWMMC_MAX_CH_NUM); 250 251 /* For DWMMC always set boot device as mmc 0 */ 252 if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) { 253 boot_dev_node = node_list[2]; 254 node_list[2] = node_list[0]; 255 node_list[0] = boot_dev_node; 256 } 257 258 err = exynos_dwmci_process_node(blob, node_list, count); 259 260 return err; 261 } 262 263 #ifdef CONFIG_DM_MMC 264 static int exynos_dwmmc_probe(struct udevice *dev) 265 { 266 struct exynos_mmc_plat *plat = dev_get_platdata(dev); 267 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 268 struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); 269 struct dwmci_host *host = &priv->host; 270 int err; 271 272 err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host, 273 priv); 274 if (err) 275 return err; 276 err = do_dwmci_init(host); 277 if (err) 278 return err; 279 280 dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); 281 host->mmc = &plat->mmc; 282 host->mmc->priv = &priv->host; 283 host->priv = dev; 284 upriv->mmc = host->mmc; 285 286 return dwmci_probe(dev); 287 } 288 289 static int exynos_dwmmc_bind(struct udevice *dev) 290 { 291 struct exynos_mmc_plat *plat = dev_get_platdata(dev); 292 293 return dwmci_bind(dev, &plat->mmc, &plat->cfg); 294 } 295 296 static const struct udevice_id exynos_dwmmc_ids[] = { 297 { .compatible = "samsung,exynos4412-dw-mshc" }, 298 { .compatible = "samsung,exynos-dwmmc" }, 299 { } 300 }; 301 302 U_BOOT_DRIVER(exynos_dwmmc_drv) = { 303 .name = "exynos_dwmmc", 304 .id = UCLASS_MMC, 305 .of_match = exynos_dwmmc_ids, 306 .bind = exynos_dwmmc_bind, 307 .ops = &dm_dwmci_ops, 308 .probe = exynos_dwmmc_probe, 309 .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data), 310 .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat), 311 }; 312 #endif 313