1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dwmmc.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <malloc.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/gpio.h> 17 #include <asm-generic/errno.h> 18 19 #define DWMMC_MAX_CH_NUM 4 20 #define DWMMC_MAX_FREQ 52000000 21 #define DWMMC_MIN_FREQ 400000 22 #define DWMMC_MMC0_CLKSEL_VAL 0x03030001 23 #define DWMMC_MMC2_CLKSEL_VAL 0x03020001 24 25 /* 26 * Function used as callback function to initialise the 27 * CLKSEL register for every mmc channel. 28 */ 29 static void exynos_dwmci_clksel(struct dwmci_host *host) 30 { 31 dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); 32 } 33 34 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) 35 { 36 unsigned long sclk; 37 int8_t clk_div; 38 39 /* 40 * Since SDCLKIN is divided inside controller by the DIVRATIO 41 * value set in the CLKSEL register, we need to use the same output 42 * clock value to calculate the CLKDIV value. 43 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) 44 */ 45 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) 46 & DWMCI_DIVRATIO_MASK) + 1; 47 sclk = get_mmc_clk(host->dev_index); 48 49 /* 50 * Assume to know divider value. 51 * When clock unit is broken, need to set "host->div" 52 */ 53 return sclk / clk_div / (host->div + 1); 54 } 55 56 static void exynos_dwmci_board_init(struct dwmci_host *host) 57 { 58 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 59 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 60 dwmci_writel(host, EMMCP_SEND0, 0); 61 dwmci_writel(host, EMMCP_CTRL0, 62 MPSCTRL_SECURE_READ_BIT | 63 MPSCTRL_SECURE_WRITE_BIT | 64 MPSCTRL_NON_SECURE_READ_BIT | 65 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 66 } 67 } 68 69 static int exynos_dwmci_core_init(struct dwmci_host *host, int index) 70 { 71 unsigned int div; 72 unsigned long freq, sclk; 73 74 if (host->bus_hz) 75 freq = host->bus_hz; 76 else 77 freq = DWMMC_MAX_FREQ; 78 79 /* request mmc clock vlaue of 52MHz. */ 80 sclk = get_mmc_clk(index); 81 div = DIV_ROUND_UP(sclk, freq); 82 /* set the clock divisor for mmc */ 83 set_mmc_clk(index, div); 84 85 host->name = "EXYNOS DWMMC"; 86 #ifdef CONFIG_EXYNOS5420 87 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 88 #endif 89 host->board_init = exynos_dwmci_board_init; 90 91 if (!host->clksel_val) { 92 if (index == 0) 93 host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; 94 else if (index == 2) 95 host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; 96 } 97 98 host->caps = MMC_MODE_DDR_52MHz; 99 host->clksel = exynos_dwmci_clksel; 100 host->dev_index = index; 101 host->get_mmc_clk = exynos_dwmci_get_clk; 102 /* Add the mmc channel to be registered with mmc core */ 103 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 104 debug("dwmmc%d registration failed\n", index); 105 return -1; 106 } 107 return 0; 108 } 109 110 /* 111 * This function adds the mmc channel to be registered with mmc core. 112 * index - mmc channel number. 113 * regbase - register base address of mmc channel specified in 'index'. 114 * bus_width - operating bus width of mmc channel specified in 'index'. 115 * clksel - value to be written into CLKSEL register in case of FDT. 116 * NULL in case od non-FDT. 117 */ 118 int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) 119 { 120 struct dwmci_host *host = NULL; 121 122 host = malloc(sizeof(struct dwmci_host)); 123 if (!host) { 124 error("dwmci_host malloc fail!\n"); 125 return -ENOMEM; 126 } 127 128 host->ioaddr = (void *)regbase; 129 host->buswidth = bus_width; 130 131 if (clksel) 132 host->clksel_val = clksel; 133 134 return exynos_dwmci_core_init(host, index); 135 } 136 137 #ifdef CONFIG_OF_CONTROL 138 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; 139 140 static int do_dwmci_init(struct dwmci_host *host) 141 { 142 int index, flag, err; 143 144 index = host->dev_index; 145 146 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 147 err = exynos_pinmux_config(host->dev_id, flag); 148 if (err) { 149 debug("DWMMC not configure\n"); 150 return err; 151 } 152 153 return exynos_dwmci_core_init(host, index); 154 } 155 156 static int exynos_dwmci_get_config(const void *blob, int node, 157 struct dwmci_host *host) 158 { 159 int err = 0; 160 u32 base, clksel_val, timing[3]; 161 162 /* Extract device id for each mmc channel */ 163 host->dev_id = pinmux_decode_periph_id(blob, node); 164 165 /* Get the bus width from the device node */ 166 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 167 if (host->buswidth <= 0) { 168 debug("DWMMC: Can't get bus-width\n"); 169 return -EINVAL; 170 } 171 172 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); 173 if (host->dev_index == host->dev_id) 174 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; 175 176 /* Set the base address from the device node */ 177 base = fdtdec_get_addr(blob, node, "reg"); 178 if (!base) { 179 debug("DWMMC: Can't get base address\n"); 180 return -EINVAL; 181 } 182 host->ioaddr = (void *)base; 183 184 /* Extract the timing info from the node */ 185 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); 186 if (err) { 187 debug("Can't get sdr-timings for devider\n"); 188 return -EINVAL; 189 } 190 191 clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 192 DWMCI_SET_DRV_CLK(timing[1]) | 193 DWMCI_SET_DIV_RATIO(timing[2])); 194 if (clksel_val) 195 host->clksel_val = clksel_val; 196 197 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); 198 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); 199 host->div = fdtdec_get_int(blob, node, "div", 0); 200 201 return 0; 202 } 203 204 static int exynos_dwmci_process_node(const void *blob, 205 int node_list[], int count) 206 { 207 struct dwmci_host *host; 208 int i, node, err; 209 210 for (i = 0; i < count; i++) { 211 node = node_list[i]; 212 if (node <= 0) 213 continue; 214 host = &dwmci_host[i]; 215 err = exynos_dwmci_get_config(blob, node, host); 216 if (err) { 217 debug("%s: failed to decode dev %d\n", __func__, i); 218 return err; 219 } 220 221 do_dwmci_init(host); 222 } 223 return 0; 224 } 225 226 int exynos_dwmmc_init(const void *blob) 227 { 228 int compat_id; 229 int node_list[DWMMC_MAX_CH_NUM]; 230 int err = 0, count; 231 232 compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; 233 234 count = fdtdec_find_aliases_for_id(blob, "mmc", 235 compat_id, node_list, DWMMC_MAX_CH_NUM); 236 err = exynos_dwmci_process_node(blob, node_list, count); 237 238 return err; 239 } 240 #endif 241