1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 */ 6 7 #include <common.h> 8 #include <dwmmc.h> 9 #include <fdtdec.h> 10 #include <linux/libfdt.h> 11 #include <malloc.h> 12 #include <errno.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/power.h> 17 #include <asm/gpio.h> 18 19 #define DWMMC_MAX_CH_NUM 4 20 #define DWMMC_MAX_FREQ 52000000 21 #define DWMMC_MIN_FREQ 400000 22 #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 23 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 24 25 #ifdef CONFIG_DM_MMC 26 #include <dm.h> 27 DECLARE_GLOBAL_DATA_PTR; 28 29 struct exynos_mmc_plat { 30 struct mmc_config cfg; 31 struct mmc mmc; 32 }; 33 #endif 34 35 /* Exynos implmentation specific drver private data */ 36 struct dwmci_exynos_priv_data { 37 #ifdef CONFIG_DM_MMC 38 struct dwmci_host host; 39 #endif 40 u32 sdr_timing; 41 }; 42 43 /* 44 * Function used as callback function to initialise the 45 * CLKSEL register for every mmc channel. 46 */ 47 static void exynos_dwmci_clksel(struct dwmci_host *host) 48 { 49 struct dwmci_exynos_priv_data *priv = host->priv; 50 51 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); 52 } 53 54 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) 55 { 56 unsigned long sclk; 57 int8_t clk_div; 58 59 /* 60 * Since SDCLKIN is divided inside controller by the DIVRATIO 61 * value set in the CLKSEL register, we need to use the same output 62 * clock value to calculate the CLKDIV value. 63 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) 64 */ 65 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) 66 & DWMCI_DIVRATIO_MASK) + 1; 67 sclk = get_mmc_clk(host->dev_index); 68 69 /* 70 * Assume to know divider value. 71 * When clock unit is broken, need to set "host->div" 72 */ 73 return sclk / clk_div / (host->div + 1); 74 } 75 76 static void exynos_dwmci_board_init(struct dwmci_host *host) 77 { 78 struct dwmci_exynos_priv_data *priv = host->priv; 79 80 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 81 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 82 dwmci_writel(host, EMMCP_SEND0, 0); 83 dwmci_writel(host, EMMCP_CTRL0, 84 MPSCTRL_SECURE_READ_BIT | 85 MPSCTRL_SECURE_WRITE_BIT | 86 MPSCTRL_NON_SECURE_READ_BIT | 87 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 88 } 89 90 /* Set to timing value at initial time */ 91 if (priv->sdr_timing) 92 exynos_dwmci_clksel(host); 93 } 94 95 static int exynos_dwmci_core_init(struct dwmci_host *host) 96 { 97 unsigned int div; 98 unsigned long freq, sclk; 99 100 if (host->bus_hz) 101 freq = host->bus_hz; 102 else 103 freq = DWMMC_MAX_FREQ; 104 105 /* request mmc clock vlaue of 52MHz. */ 106 sclk = get_mmc_clk(host->dev_index); 107 div = DIV_ROUND_UP(sclk, freq); 108 /* set the clock divisor for mmc */ 109 set_mmc_clk(host->dev_index, div); 110 111 host->name = "EXYNOS DWMMC"; 112 #ifdef CONFIG_EXYNOS5420 113 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 114 #endif 115 host->board_init = exynos_dwmci_board_init; 116 117 host->caps = MMC_MODE_DDR_52MHz; 118 host->clksel = exynos_dwmci_clksel; 119 host->get_mmc_clk = exynos_dwmci_get_clk; 120 121 #ifndef CONFIG_DM_MMC 122 /* Add the mmc channel to be registered with mmc core */ 123 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 124 printf("DWMMC%d registration failed\n", host->dev_index); 125 return -1; 126 } 127 #endif 128 129 return 0; 130 } 131 132 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; 133 134 static int do_dwmci_init(struct dwmci_host *host) 135 { 136 int flag, err; 137 138 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; 139 err = exynos_pinmux_config(host->dev_id, flag); 140 if (err) { 141 printf("DWMMC%d not configure\n", host->dev_index); 142 return err; 143 } 144 145 return exynos_dwmci_core_init(host); 146 } 147 148 static int exynos_dwmci_get_config(const void *blob, int node, 149 struct dwmci_host *host) 150 { 151 int err = 0; 152 u32 base, timing[3]; 153 struct dwmci_exynos_priv_data *priv; 154 155 priv = malloc(sizeof(struct dwmci_exynos_priv_data)); 156 if (!priv) { 157 pr_err("dwmci_exynos_priv_data malloc fail!\n"); 158 return -ENOMEM; 159 } 160 161 /* Extract device id for each mmc channel */ 162 host->dev_id = pinmux_decode_periph_id(blob, node); 163 164 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); 165 if (host->dev_index == host->dev_id) 166 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; 167 168 if (host->dev_index > 4) { 169 printf("DWMMC%d: Can't get the dev index\n", host->dev_index); 170 free(priv); 171 return -EINVAL; 172 } 173 174 /* Get the bus width from the device node (Default is 4bit buswidth) */ 175 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); 176 177 /* Set the base address from the device node */ 178 base = fdtdec_get_addr(blob, node, "reg"); 179 if (!base) { 180 printf("DWMMC%d: Can't get base address\n", host->dev_index); 181 free(priv); 182 return -EINVAL; 183 } 184 host->ioaddr = (void *)base; 185 186 /* Extract the timing info from the node */ 187 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); 188 if (err) { 189 printf("DWMMC%d: Can't get sdr-timings for devider\n", 190 host->dev_index); 191 free(priv); 192 return -EINVAL; 193 } 194 195 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 196 DWMCI_SET_DRV_CLK(timing[1]) | 197 DWMCI_SET_DIV_RATIO(timing[2])); 198 199 /* sdr_timing didn't assigned anything, use the default value */ 200 if (!priv->sdr_timing) { 201 if (host->dev_index == 0) 202 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; 203 else if (host->dev_index == 2) 204 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; 205 } 206 207 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); 208 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); 209 host->div = fdtdec_get_int(blob, node, "div", 0); 210 211 host->priv = priv; 212 213 return 0; 214 } 215 216 static int exynos_dwmci_process_node(const void *blob, 217 int node_list[], int count) 218 { 219 struct dwmci_host *host; 220 int i, node, err; 221 222 for (i = 0; i < count; i++) { 223 node = node_list[i]; 224 if (node <= 0) 225 continue; 226 host = &dwmci_host[i]; 227 err = exynos_dwmci_get_config(blob, node, host); 228 if (err) { 229 printf("%s: failed to decode dev %d\n", __func__, i); 230 return err; 231 } 232 233 do_dwmci_init(host); 234 } 235 return 0; 236 } 237 238 int exynos_dwmmc_init(const void *blob) 239 { 240 int node_list[DWMMC_MAX_CH_NUM]; 241 int boot_dev_node; 242 int err = 0, count; 243 244 count = fdtdec_find_aliases_for_id(blob, "mmc", 245 COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list, 246 DWMMC_MAX_CH_NUM); 247 248 /* For DWMMC always set boot device as mmc 0 */ 249 if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) { 250 boot_dev_node = node_list[2]; 251 node_list[2] = node_list[0]; 252 node_list[0] = boot_dev_node; 253 } 254 255 err = exynos_dwmci_process_node(blob, node_list, count); 256 257 return err; 258 } 259 260 #ifdef CONFIG_DM_MMC 261 static int exynos_dwmmc_probe(struct udevice *dev) 262 { 263 struct exynos_mmc_plat *plat = dev_get_platdata(dev); 264 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 265 struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); 266 struct dwmci_host *host = &priv->host; 267 int err; 268 269 err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host); 270 if (err) 271 return err; 272 err = do_dwmci_init(host); 273 if (err) 274 return err; 275 276 dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); 277 host->mmc = &plat->mmc; 278 host->mmc->priv = &priv->host; 279 host->priv = dev; 280 upriv->mmc = host->mmc; 281 282 return dwmci_probe(dev); 283 } 284 285 static int exynos_dwmmc_bind(struct udevice *dev) 286 { 287 struct exynos_mmc_plat *plat = dev_get_platdata(dev); 288 289 return dwmci_bind(dev, &plat->mmc, &plat->cfg); 290 } 291 292 static const struct udevice_id exynos_dwmmc_ids[] = { 293 { .compatible = "samsung,exynos4412-dw-mshc" }, 294 { } 295 }; 296 297 U_BOOT_DRIVER(exynos_dwmmc_drv) = { 298 .name = "exynos_dwmmc", 299 .id = UCLASS_MMC, 300 .of_match = exynos_dwmmc_ids, 301 .bind = exynos_dwmmc_bind, 302 .ops = &dm_dwmci_ops, 303 .probe = exynos_dwmmc_probe, 304 .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data), 305 .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat), 306 }; 307 #endif 308