1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dwmmc.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <malloc.h> 13 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/pinmux.h> 16 17 #define DWMMC_MAX_CH_NUM 4 18 #define DWMMC_MAX_FREQ 52000000 19 #define DWMMC_MIN_FREQ 400000 20 #define DWMMC_MMC0_CLKSEL_VAL 0x03030001 21 #define DWMMC_MMC2_CLKSEL_VAL 0x03020001 22 23 /* 24 * Function used as callback function to initialise the 25 * CLKSEL register for every mmc channel. 26 */ 27 static void exynos_dwmci_clksel(struct dwmci_host *host) 28 { 29 dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); 30 } 31 32 unsigned int exynos_dwmci_get_clk(int dev_index) 33 { 34 return get_mmc_clk(dev_index); 35 } 36 37 static void exynos_dwmci_board_init(struct dwmci_host *host) 38 { 39 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { 40 dwmci_writel(host, EMMCP_MPSBEGIN0, 0); 41 dwmci_writel(host, EMMCP_SEND0, 0); 42 dwmci_writel(host, EMMCP_CTRL0, 43 MPSCTRL_SECURE_READ_BIT | 44 MPSCTRL_SECURE_WRITE_BIT | 45 MPSCTRL_NON_SECURE_READ_BIT | 46 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); 47 } 48 } 49 50 /* 51 * This function adds the mmc channel to be registered with mmc core. 52 * index - mmc channel number. 53 * regbase - register base address of mmc channel specified in 'index'. 54 * bus_width - operating bus width of mmc channel specified in 'index'. 55 * clksel - value to be written into CLKSEL register in case of FDT. 56 * NULL in case od non-FDT. 57 */ 58 int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) 59 { 60 struct dwmci_host *host = NULL; 61 unsigned int div; 62 unsigned long freq, sclk; 63 host = malloc(sizeof(struct dwmci_host)); 64 if (!host) { 65 printf("dwmci_host malloc fail!\n"); 66 return 1; 67 } 68 /* request mmc clock vlaue of 52MHz. */ 69 freq = 52000000; 70 sclk = get_mmc_clk(index); 71 div = DIV_ROUND_UP(sclk, freq); 72 /* set the clock divisor for mmc */ 73 set_mmc_clk(index, div); 74 75 host->name = "EXYNOS DWMMC"; 76 host->ioaddr = (void *)regbase; 77 host->buswidth = bus_width; 78 #ifdef CONFIG_EXYNOS5420 79 host->quirks = DWMCI_QUIRK_DISABLE_SMU; 80 #endif 81 host->board_init = exynos_dwmci_board_init; 82 83 if (clksel) { 84 host->clksel_val = clksel; 85 } else { 86 if (0 == index) 87 host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; 88 if (2 == index) 89 host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; 90 } 91 92 host->clksel = exynos_dwmci_clksel; 93 host->dev_index = index; 94 host->get_mmc_clk = exynos_dwmci_get_clk; 95 /* Add the mmc channel to be registered with mmc core */ 96 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { 97 debug("dwmmc%d registration failed\n", index); 98 return -1; 99 } 100 return 0; 101 } 102 103 #ifdef CONFIG_OF_CONTROL 104 int exynos_dwmmc_init(const void *blob) 105 { 106 int index, bus_width; 107 int node_list[DWMMC_MAX_CH_NUM]; 108 int err = 0, dev_id, flag, count, i; 109 u32 clksel_val, base, timing[3]; 110 111 count = fdtdec_find_aliases_for_id(blob, "mmc", 112 COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, 113 DWMMC_MAX_CH_NUM); 114 115 for (i = 0; i < count; i++) { 116 int node = node_list[i]; 117 118 if (node <= 0) 119 continue; 120 121 /* Extract device id for each mmc channel */ 122 dev_id = pinmux_decode_periph_id(blob, node); 123 124 /* Get the bus width from the device node */ 125 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); 126 if (bus_width <= 0) { 127 debug("DWMMC: Can't get bus-width\n"); 128 return -1; 129 } 130 if (8 == bus_width) 131 flag = PINMUX_FLAG_8BIT_MODE; 132 else 133 flag = PINMUX_FLAG_NONE; 134 135 /* config pinmux for each mmc channel */ 136 err = exynos_pinmux_config(dev_id, flag); 137 if (err) { 138 debug("DWMMC not configured\n"); 139 return err; 140 } 141 142 index = dev_id - PERIPH_ID_SDMMC0; 143 144 /* Get the base address from the device node */ 145 base = fdtdec_get_addr(blob, node, "reg"); 146 if (!base) { 147 debug("DWMMC: Can't get base address\n"); 148 return -1; 149 } 150 /* Extract the timing info from the node */ 151 err = fdtdec_get_int_array(blob, node, "samsung,timing", 152 timing, 3); 153 if (err) { 154 debug("Can't get sdr-timings for divider\n"); 155 return -1; 156 } 157 158 clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | 159 DWMCI_SET_DRV_CLK(timing[1]) | 160 DWMCI_SET_DIV_RATIO(timing[2])); 161 /* Initialise each mmc channel */ 162 err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); 163 if (err) 164 debug("dwmmc Channel-%d init failed\n", index); 165 } 166 return 0; 167 } 168 #endif 169