1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 6 */ 7 8 #include <bouncebuf.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <memalign.h> 13 #include <mmc.h> 14 #include <dwmmc.h> 15 16 #define PAGE_SIZE 4096 17 18 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 19 { 20 unsigned long timeout = 1000; 21 u32 ctrl; 22 23 dwmci_writel(host, DWMCI_CTRL, value); 24 25 while (timeout--) { 26 ctrl = dwmci_readl(host, DWMCI_CTRL); 27 if (!(ctrl & DWMCI_RESET_ALL)) 28 return 1; 29 } 30 return 0; 31 } 32 33 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 34 u32 desc0, u32 desc1, u32 desc2) 35 { 36 struct dwmci_idmac *desc = idmac; 37 38 desc->flags = desc0; 39 desc->cnt = desc1; 40 desc->addr = desc2; 41 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 42 } 43 44 static void dwmci_prepare_data(struct dwmci_host *host, 45 struct mmc_data *data, 46 struct dwmci_idmac *cur_idmac, 47 void *bounce_buffer) 48 { 49 unsigned long ctrl; 50 unsigned int i = 0, flags, cnt, blk_cnt; 51 ulong data_start, data_end; 52 53 54 blk_cnt = data->blocks; 55 56 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 57 58 data_start = (ulong)cur_idmac; 59 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 60 61 do { 62 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 63 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 64 if (blk_cnt <= 8) { 65 flags |= DWMCI_IDMAC_LD; 66 cnt = data->blocksize * blk_cnt; 67 } else 68 cnt = data->blocksize * 8; 69 70 dwmci_set_idma_desc(cur_idmac, flags, cnt, 71 (ulong)bounce_buffer + (i * PAGE_SIZE)); 72 73 if (blk_cnt <= 8) 74 break; 75 blk_cnt -= 8; 76 cur_idmac++; 77 i++; 78 } while(1); 79 80 data_end = (ulong)cur_idmac; 81 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 82 83 ctrl = dwmci_readl(host, DWMCI_CTRL); 84 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 85 dwmci_writel(host, DWMCI_CTRL, ctrl); 86 87 ctrl = dwmci_readl(host, DWMCI_BMOD); 88 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 89 dwmci_writel(host, DWMCI_BMOD, ctrl); 90 91 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 92 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 93 } 94 95 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len) 96 { 97 u32 timeout = 20000; 98 99 *len = dwmci_readl(host, DWMCI_STATUS); 100 while (--timeout && (*len & bit)) { 101 udelay(200); 102 *len = dwmci_readl(host, DWMCI_STATUS); 103 } 104 105 if (!timeout) { 106 debug("%s: FIFO underflow timeout\n", __func__); 107 return -ETIMEDOUT; 108 } 109 110 return 0; 111 } 112 113 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 114 { 115 int ret = 0; 116 u32 timeout = 240000; 117 u32 mask, size, i, len = 0; 118 u32 *buf = NULL; 119 ulong start = get_timer(0); 120 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 121 RX_WMARK_SHIFT) + 1) * 2; 122 123 size = data->blocksize * data->blocks / 4; 124 if (data->flags == MMC_DATA_READ) 125 buf = (unsigned int *)data->dest; 126 else 127 buf = (unsigned int *)data->src; 128 129 for (;;) { 130 mask = dwmci_readl(host, DWMCI_RINTSTS); 131 /* Error during data transfer. */ 132 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 133 debug("%s: DATA ERROR!\n", __func__); 134 ret = -EINVAL; 135 break; 136 } 137 138 if (host->fifo_mode && size) { 139 len = 0; 140 if (data->flags == MMC_DATA_READ && 141 (mask & DWMCI_INTMSK_RXDR)) { 142 while (size) { 143 ret = dwmci_fifo_ready(host, 144 DWMCI_FIFO_EMPTY, 145 &len); 146 if (ret < 0) 147 break; 148 149 len = (len >> DWMCI_FIFO_SHIFT) & 150 DWMCI_FIFO_MASK; 151 len = min(size, len); 152 for (i = 0; i < len; i++) 153 *buf++ = 154 dwmci_readl(host, DWMCI_DATA); 155 size = size > len ? (size - len) : 0; 156 } 157 dwmci_writel(host, DWMCI_RINTSTS, 158 DWMCI_INTMSK_RXDR); 159 } else if (data->flags == MMC_DATA_WRITE && 160 (mask & DWMCI_INTMSK_TXDR)) { 161 while (size) { 162 ret = dwmci_fifo_ready(host, 163 DWMCI_FIFO_FULL, 164 &len); 165 if (ret < 0) 166 break; 167 168 len = fifo_depth - ((len >> 169 DWMCI_FIFO_SHIFT) & 170 DWMCI_FIFO_MASK); 171 len = min(size, len); 172 for (i = 0; i < len; i++) 173 dwmci_writel(host, DWMCI_DATA, 174 *buf++); 175 size = size > len ? (size - len) : 0; 176 } 177 dwmci_writel(host, DWMCI_RINTSTS, 178 DWMCI_INTMSK_TXDR); 179 } 180 } 181 182 /* Data arrived correctly. */ 183 if (mask & DWMCI_INTMSK_DTO) { 184 ret = 0; 185 break; 186 } 187 188 /* Check for timeout. */ 189 if (get_timer(start) > timeout) { 190 debug("%s: Timeout waiting for data!\n", 191 __func__); 192 ret = -ETIMEDOUT; 193 break; 194 } 195 } 196 197 dwmci_writel(host, DWMCI_RINTSTS, mask); 198 199 return ret; 200 } 201 202 static int dwmci_set_transfer_mode(struct dwmci_host *host, 203 struct mmc_data *data) 204 { 205 unsigned long mode; 206 207 mode = DWMCI_CMD_DATA_EXP; 208 if (data->flags & MMC_DATA_WRITE) 209 mode |= DWMCI_CMD_RW; 210 211 return mode; 212 } 213 214 #ifdef CONFIG_DM_MMC 215 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 216 struct mmc_data *data) 217 { 218 struct mmc *mmc = mmc_get_mmc_dev(dev); 219 #else 220 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 221 struct mmc_data *data) 222 { 223 #endif 224 struct dwmci_host *host = mmc->priv; 225 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 226 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 227 int ret = 0, flags = 0, i; 228 unsigned int timeout = 500; 229 u32 retry = 100000; 230 u32 mask, ctrl; 231 ulong start = get_timer(0); 232 struct bounce_buffer bbstate; 233 234 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 235 if (get_timer(start) > timeout) { 236 debug("%s: Timeout on data busy\n", __func__); 237 return -ETIMEDOUT; 238 } 239 } 240 241 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 242 243 if (data) { 244 if (host->fifo_mode) { 245 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 246 dwmci_writel(host, DWMCI_BYTCNT, 247 data->blocksize * data->blocks); 248 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 249 } else { 250 if (data->flags == MMC_DATA_READ) { 251 bounce_buffer_start(&bbstate, (void*)data->dest, 252 data->blocksize * 253 data->blocks, GEN_BB_WRITE); 254 } else { 255 bounce_buffer_start(&bbstate, (void*)data->src, 256 data->blocksize * 257 data->blocks, GEN_BB_READ); 258 } 259 dwmci_prepare_data(host, data, cur_idmac, 260 bbstate.bounce_buffer); 261 } 262 } 263 264 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 265 266 if (data) 267 flags = dwmci_set_transfer_mode(host, data); 268 269 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 270 return -1; 271 272 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 273 flags |= DWMCI_CMD_ABORT_STOP; 274 else 275 flags |= DWMCI_CMD_PRV_DAT_WAIT; 276 277 if (cmd->resp_type & MMC_RSP_PRESENT) { 278 flags |= DWMCI_CMD_RESP_EXP; 279 if (cmd->resp_type & MMC_RSP_136) 280 flags |= DWMCI_CMD_RESP_LENGTH; 281 } 282 283 if (cmd->resp_type & MMC_RSP_CRC) 284 flags |= DWMCI_CMD_CHECK_CRC; 285 286 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 287 288 debug("Sending CMD%d\n",cmd->cmdidx); 289 290 dwmci_writel(host, DWMCI_CMD, flags); 291 292 for (i = 0; i < retry; i++) { 293 mask = dwmci_readl(host, DWMCI_RINTSTS); 294 if (mask & DWMCI_INTMSK_CDONE) { 295 if (!data) 296 dwmci_writel(host, DWMCI_RINTSTS, mask); 297 break; 298 } 299 } 300 301 if (i == retry) { 302 debug("%s: Timeout.\n", __func__); 303 return -ETIMEDOUT; 304 } 305 306 if (mask & DWMCI_INTMSK_RTO) { 307 /* 308 * Timeout here is not necessarily fatal. (e)MMC cards 309 * will splat here when they receive CMD55 as they do 310 * not support this command and that is exactly the way 311 * to tell them apart from SD cards. Thus, this output 312 * below shall be debug(). eMMC cards also do not favor 313 * CMD8, please keep that in mind. 314 */ 315 debug("%s: Response Timeout.\n", __func__); 316 return -ETIMEDOUT; 317 } else if (mask & DWMCI_INTMSK_RE) { 318 debug("%s: Response Error.\n", __func__); 319 return -EIO; 320 } 321 322 323 if (cmd->resp_type & MMC_RSP_PRESENT) { 324 if (cmd->resp_type & MMC_RSP_136) { 325 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 326 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 327 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 328 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 329 } else { 330 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 331 } 332 } 333 334 if (data) { 335 ret = dwmci_data_transfer(host, data); 336 337 /* only dma mode need it */ 338 if (!host->fifo_mode) { 339 ctrl = dwmci_readl(host, DWMCI_CTRL); 340 ctrl &= ~(DWMCI_DMA_EN); 341 dwmci_writel(host, DWMCI_CTRL, ctrl); 342 bounce_buffer_stop(&bbstate); 343 } 344 } 345 346 udelay(100); 347 348 return ret; 349 } 350 351 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 352 { 353 u32 div, status; 354 int timeout = 10000; 355 unsigned long sclk; 356 357 if ((freq == host->clock) || (freq == 0)) 358 return 0; 359 /* 360 * If host->get_mmc_clk isn't defined, 361 * then assume that host->bus_hz is source clock value. 362 * host->bus_hz should be set by user. 363 */ 364 if (host->get_mmc_clk) 365 sclk = host->get_mmc_clk(host, freq); 366 else if (host->bus_hz) 367 sclk = host->bus_hz; 368 else { 369 debug("%s: Didn't get source clock value.\n", __func__); 370 return -EINVAL; 371 } 372 373 if (sclk == freq) 374 div = 0; /* bypass mode */ 375 else 376 div = DIV_ROUND_UP(sclk, 2 * freq); 377 378 dwmci_writel(host, DWMCI_CLKENA, 0); 379 dwmci_writel(host, DWMCI_CLKSRC, 0); 380 381 dwmci_writel(host, DWMCI_CLKDIV, div); 382 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 383 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 384 385 do { 386 status = dwmci_readl(host, DWMCI_CMD); 387 if (timeout-- < 0) { 388 debug("%s: Timeout!\n", __func__); 389 return -ETIMEDOUT; 390 } 391 } while (status & DWMCI_CMD_START); 392 393 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 394 DWMCI_CLKEN_LOW_PWR); 395 396 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 397 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 398 399 timeout = 10000; 400 do { 401 status = dwmci_readl(host, DWMCI_CMD); 402 if (timeout-- < 0) { 403 debug("%s: Timeout!\n", __func__); 404 return -ETIMEDOUT; 405 } 406 } while (status & DWMCI_CMD_START); 407 408 host->clock = freq; 409 410 return 0; 411 } 412 413 #ifdef CONFIG_DM_MMC 414 static int dwmci_set_ios(struct udevice *dev) 415 { 416 struct mmc *mmc = mmc_get_mmc_dev(dev); 417 #else 418 static int dwmci_set_ios(struct mmc *mmc) 419 { 420 #endif 421 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 422 u32 ctype, regs; 423 424 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 425 426 dwmci_setup_bus(host, mmc->clock); 427 switch (mmc->bus_width) { 428 case 8: 429 ctype = DWMCI_CTYPE_8BIT; 430 break; 431 case 4: 432 ctype = DWMCI_CTYPE_4BIT; 433 break; 434 default: 435 ctype = DWMCI_CTYPE_1BIT; 436 break; 437 } 438 439 dwmci_writel(host, DWMCI_CTYPE, ctype); 440 441 regs = dwmci_readl(host, DWMCI_UHS_REG); 442 if (mmc->ddr_mode) 443 regs |= DWMCI_DDR_MODE; 444 else 445 regs &= ~DWMCI_DDR_MODE; 446 447 dwmci_writel(host, DWMCI_UHS_REG, regs); 448 449 if (host->clksel) 450 host->clksel(host); 451 452 return 0; 453 } 454 455 static int dwmci_init(struct mmc *mmc) 456 { 457 struct dwmci_host *host = mmc->priv; 458 459 if (host->board_init) 460 host->board_init(host); 461 462 dwmci_writel(host, DWMCI_PWREN, 1); 463 464 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 465 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 466 return -EIO; 467 } 468 469 /* Enumerate at 400KHz */ 470 dwmci_setup_bus(host, mmc->cfg->f_min); 471 472 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 473 dwmci_writel(host, DWMCI_INTMASK, 0); 474 475 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 476 477 dwmci_writel(host, DWMCI_IDINTEN, 0); 478 dwmci_writel(host, DWMCI_BMOD, 1); 479 480 if (!host->fifoth_val) { 481 uint32_t fifo_size; 482 483 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 484 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 485 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | 486 TX_WMARK(fifo_size / 2); 487 } 488 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 489 490 dwmci_writel(host, DWMCI_CLKENA, 0); 491 dwmci_writel(host, DWMCI_CLKSRC, 0); 492 493 return 0; 494 } 495 496 #ifdef CONFIG_DM_MMC 497 int dwmci_probe(struct udevice *dev) 498 { 499 struct mmc *mmc = mmc_get_mmc_dev(dev); 500 501 return dwmci_init(mmc); 502 } 503 504 const struct dm_mmc_ops dm_dwmci_ops = { 505 .send_cmd = dwmci_send_cmd, 506 .set_ios = dwmci_set_ios, 507 }; 508 509 #else 510 static const struct mmc_ops dwmci_ops = { 511 .send_cmd = dwmci_send_cmd, 512 .set_ios = dwmci_set_ios, 513 .init = dwmci_init, 514 }; 515 #endif 516 517 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 518 u32 max_clk, u32 min_clk) 519 { 520 cfg->name = host->name; 521 #ifndef CONFIG_DM_MMC 522 cfg->ops = &dwmci_ops; 523 #endif 524 cfg->f_min = min_clk; 525 cfg->f_max = max_clk; 526 527 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 528 529 cfg->host_caps = host->caps; 530 531 if (host->buswidth == 8) { 532 cfg->host_caps |= MMC_MODE_8BIT; 533 cfg->host_caps &= ~MMC_MODE_4BIT; 534 } else { 535 cfg->host_caps |= MMC_MODE_4BIT; 536 cfg->host_caps &= ~MMC_MODE_8BIT; 537 } 538 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 539 540 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 541 } 542 543 #ifdef CONFIG_BLK 544 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 545 { 546 return mmc_bind(dev, mmc, cfg); 547 } 548 #else 549 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 550 { 551 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 552 553 host->mmc = mmc_create(&host->cfg, host); 554 if (host->mmc == NULL) 555 return -1; 556 557 return 0; 558 } 559 #endif 560