xref: /openbmc/u-boot/drivers/mmc/dw_mmc.c (revision 50ffc3b64aa3c8113f0a9fc31ea96e596d60054a)
1 /*
2  * (C) Copyright 2012 SAMSUNG Electronics
3  * Jaehoon Chung <jh80.chung@samsung.com>
4  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,  MA 02111-1307 USA
19  *
20  */
21 
22 #include <common.h>
23 #include <malloc.h>
24 #include <mmc.h>
25 #include <dwmmc.h>
26 #include <asm-generic/errno.h>
27 
28 #define PAGE_SIZE 4096
29 
30 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
31 {
32 	unsigned long timeout = 1000;
33 	u32 ctrl;
34 
35 	dwmci_writel(host, DWMCI_CTRL, value);
36 
37 	while (timeout--) {
38 		ctrl = dwmci_readl(host, DWMCI_CTRL);
39 		if (!(ctrl & DWMCI_RESET_ALL))
40 			return 1;
41 	}
42 	return 0;
43 }
44 
45 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
46 		u32 desc0, u32 desc1, u32 desc2)
47 {
48 	struct dwmci_idmac *desc = idmac;
49 
50 	desc->flags = desc0;
51 	desc->cnt = desc1;
52 	desc->addr = desc2;
53 	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
54 }
55 
56 static void dwmci_prepare_data(struct dwmci_host *host,
57 		struct mmc_data *data)
58 {
59 	unsigned long ctrl;
60 	unsigned int i = 0, flags, cnt, blk_cnt;
61 	ulong data_start, data_end, start_addr;
62 	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks);
63 
64 
65 	blk_cnt = data->blocks;
66 
67 	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
68 
69 	data_start = (ulong)cur_idmac;
70 	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
71 
72 	if (data->flags == MMC_DATA_READ)
73 		start_addr = (unsigned int)data->dest;
74 	else
75 		start_addr = (unsigned int)data->src;
76 
77 	do {
78 		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
79 		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
80 		if (blk_cnt <= 8) {
81 			flags |= DWMCI_IDMAC_LD;
82 			cnt = data->blocksize * blk_cnt;
83 		} else
84 			cnt = data->blocksize * 8;
85 
86 		dwmci_set_idma_desc(cur_idmac, flags, cnt,
87 				start_addr + (i * PAGE_SIZE));
88 
89 		if(blk_cnt < 8)
90 			break;
91 		blk_cnt -= 8;
92 		cur_idmac++;
93 		i++;
94 	} while(1);
95 
96 	data_end = (ulong)cur_idmac;
97 	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
98 
99 	ctrl = dwmci_readl(host, DWMCI_CTRL);
100 	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
101 	dwmci_writel(host, DWMCI_CTRL, ctrl);
102 
103 	ctrl = dwmci_readl(host, DWMCI_BMOD);
104 	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
105 	dwmci_writel(host, DWMCI_BMOD, ctrl);
106 
107 	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
108 	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
109 }
110 
111 static int dwmci_set_transfer_mode(struct dwmci_host *host,
112 		struct mmc_data *data)
113 {
114 	unsigned long mode;
115 
116 	mode = DWMCI_CMD_DATA_EXP;
117 	if (data->flags & MMC_DATA_WRITE)
118 		mode |= DWMCI_CMD_RW;
119 
120 	return mode;
121 }
122 
123 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
124 		struct mmc_data *data)
125 {
126 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
127 	int flags = 0, i;
128 	unsigned int timeout = 100000;
129 	u32 retry = 10000;
130 	u32 mask, ctrl;
131 	ulong start = get_timer(0);
132 
133 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
134 		if (get_timer(start) > timeout) {
135 			printf("Timeout on data busy\n");
136 			return TIMEOUT;
137 		}
138 	}
139 
140 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
141 
142 	if (data)
143 		dwmci_prepare_data(host, data);
144 
145 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
146 
147 	if (data)
148 		flags = dwmci_set_transfer_mode(host, data);
149 
150 	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
151 		return -1;
152 
153 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
154 		flags |= DWMCI_CMD_ABORT_STOP;
155 	else
156 		flags |= DWMCI_CMD_PRV_DAT_WAIT;
157 
158 	if (cmd->resp_type & MMC_RSP_PRESENT) {
159 		flags |= DWMCI_CMD_RESP_EXP;
160 		if (cmd->resp_type & MMC_RSP_136)
161 			flags |= DWMCI_CMD_RESP_LENGTH;
162 	}
163 
164 	if (cmd->resp_type & MMC_RSP_CRC)
165 		flags |= DWMCI_CMD_CHECK_CRC;
166 
167 	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
168 
169 	debug("Sending CMD%d\n",cmd->cmdidx);
170 
171 	dwmci_writel(host, DWMCI_CMD, flags);
172 
173 	for (i = 0; i < retry; i++) {
174 		mask = dwmci_readl(host, DWMCI_RINTSTS);
175 		if (mask & DWMCI_INTMSK_CDONE) {
176 			if (!data)
177 				dwmci_writel(host, DWMCI_RINTSTS, mask);
178 			break;
179 		}
180 	}
181 
182 	if (i == retry)
183 		return TIMEOUT;
184 
185 	if (mask & DWMCI_INTMSK_RTO) {
186 		debug("Response Timeout..\n");
187 		return TIMEOUT;
188 	} else if (mask & DWMCI_INTMSK_RE) {
189 		debug("Response Error..\n");
190 		return -1;
191 	}
192 
193 
194 	if (cmd->resp_type & MMC_RSP_PRESENT) {
195 		if (cmd->resp_type & MMC_RSP_136) {
196 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
197 			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
198 			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
199 			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
200 		} else {
201 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
202 		}
203 	}
204 
205 	if (data) {
206 		do {
207 			mask = dwmci_readl(host, DWMCI_RINTSTS);
208 			if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
209 				debug("DATA ERROR!\n");
210 				return -1;
211 			}
212 		} while (!(mask & DWMCI_INTMSK_DTO));
213 
214 		dwmci_writel(host, DWMCI_RINTSTS, mask);
215 
216 		ctrl = dwmci_readl(host, DWMCI_CTRL);
217 		ctrl &= ~(DWMCI_DMA_EN);
218 		dwmci_writel(host, DWMCI_CTRL, ctrl);
219 	}
220 
221 	udelay(100);
222 
223 	return 0;
224 }
225 
226 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
227 {
228 	u32 div, status;
229 	int timeout = 10000;
230 	unsigned long sclk;
231 
232 	if ((freq == host->clock) || (freq == 0))
233 		return 0;
234 	/*
235 	 * If host->mmc_clk didn't define,
236 	 * then assume that host->bus_hz is source clock value.
237 	 * host->bus_hz should be set from user.
238 	 */
239 	if (host->mmc_clk)
240 		sclk = host->mmc_clk(host->dev_index);
241 	else if (host->bus_hz)
242 		sclk = host->bus_hz;
243 	else {
244 		printf("Didn't get source clock value..\n");
245 		return -EINVAL;
246 	}
247 
248 	div = DIV_ROUND_UP(sclk, 2 * freq);
249 
250 	dwmci_writel(host, DWMCI_CLKENA, 0);
251 	dwmci_writel(host, DWMCI_CLKSRC, 0);
252 
253 	dwmci_writel(host, DWMCI_CLKDIV, div);
254 	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
255 			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
256 
257 	do {
258 		status = dwmci_readl(host, DWMCI_CMD);
259 		if (timeout-- < 0) {
260 			printf("TIMEOUT error!!\n");
261 			return -ETIMEDOUT;
262 		}
263 	} while (status & DWMCI_CMD_START);
264 
265 	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
266 			DWMCI_CLKEN_LOW_PWR);
267 
268 	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
269 			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
270 
271 	timeout = 10000;
272 	do {
273 		status = dwmci_readl(host, DWMCI_CMD);
274 		if (timeout-- < 0) {
275 			printf("TIMEOUT error!!\n");
276 			return -ETIMEDOUT;
277 		}
278 	} while (status & DWMCI_CMD_START);
279 
280 	host->clock = freq;
281 
282 	return 0;
283 }
284 
285 static void dwmci_set_ios(struct mmc *mmc)
286 {
287 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
288 	u32 ctype;
289 
290 	debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
291 
292 	dwmci_setup_bus(host, mmc->clock);
293 	switch (mmc->bus_width) {
294 	case 8:
295 		ctype = DWMCI_CTYPE_8BIT;
296 		break;
297 	case 4:
298 		ctype = DWMCI_CTYPE_4BIT;
299 		break;
300 	default:
301 		ctype = DWMCI_CTYPE_1BIT;
302 		break;
303 	}
304 
305 	dwmci_writel(host, DWMCI_CTYPE, ctype);
306 
307 	if (host->clksel)
308 		host->clksel(host);
309 }
310 
311 static int dwmci_init(struct mmc *mmc)
312 {
313 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
314 	u32 fifo_size;
315 
316 	dwmci_writel(host, DWMCI_PWREN, 1);
317 
318 	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
319 		debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
320 		return -1;
321 	}
322 
323 	/* Enumerate at 400KHz */
324 	dwmci_setup_bus(host, mmc->f_min);
325 
326 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
327 	dwmci_writel(host, DWMCI_INTMASK, 0);
328 
329 	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
330 
331 	dwmci_writel(host, DWMCI_IDINTEN, 0);
332 	dwmci_writel(host, DWMCI_BMOD, 1);
333 
334 	if (!host->fifoth_val) {
335 		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
336 		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
337 		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
338 			TX_WMARK(fifo_size / 2);
339 	}
340 	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
341 
342 	dwmci_writel(host, DWMCI_CLKENA, 0);
343 	dwmci_writel(host, DWMCI_CLKSRC, 0);
344 
345 	return 0;
346 }
347 
348 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
349 {
350 	struct mmc *mmc;
351 	int err = 0;
352 
353 	mmc = malloc(sizeof(struct mmc));
354 	if (!mmc) {
355 		printf("mmc malloc fail!\n");
356 		return -1;
357 	}
358 
359 	mmc->priv = host;
360 	host->mmc = mmc;
361 
362 	sprintf(mmc->name, "%s", host->name);
363 	mmc->send_cmd = dwmci_send_cmd;
364 	mmc->set_ios = dwmci_set_ios;
365 	mmc->init = dwmci_init;
366 	mmc->f_min = min_clk;
367 	mmc->f_max = max_clk;
368 
369 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
370 
371 	mmc->host_caps = host->caps;
372 
373 	if (host->buswidth == 8) {
374 		mmc->host_caps |= MMC_MODE_8BIT;
375 		mmc->host_caps &= ~MMC_MODE_4BIT;
376 	} else {
377 		mmc->host_caps |= MMC_MODE_4BIT;
378 		mmc->host_caps &= ~MMC_MODE_8BIT;
379 	}
380 	mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
381 
382 	err = mmc_register(mmc);
383 
384 	return err;
385 }
386