1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <bouncebuf.h> 10 #include <common.h> 11 #include <malloc.h> 12 #include <mmc.h> 13 #include <dwmmc.h> 14 #include <asm-generic/errno.h> 15 16 #define PAGE_SIZE 4096 17 18 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 19 { 20 unsigned long timeout = 1000; 21 u32 ctrl; 22 23 dwmci_writel(host, DWMCI_CTRL, value); 24 25 while (timeout--) { 26 ctrl = dwmci_readl(host, DWMCI_CTRL); 27 if (!(ctrl & DWMCI_RESET_ALL)) 28 return 1; 29 } 30 return 0; 31 } 32 33 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 34 u32 desc0, u32 desc1, u32 desc2) 35 { 36 struct dwmci_idmac *desc = idmac; 37 38 desc->flags = desc0; 39 desc->cnt = desc1; 40 desc->addr = desc2; 41 desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); 42 } 43 44 static void dwmci_prepare_data(struct dwmci_host *host, 45 struct mmc_data *data, 46 struct dwmci_idmac *cur_idmac, 47 void *bounce_buffer) 48 { 49 unsigned long ctrl; 50 unsigned int i = 0, flags, cnt, blk_cnt; 51 ulong data_start, data_end; 52 53 54 blk_cnt = data->blocks; 55 56 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 57 58 data_start = (ulong)cur_idmac; 59 dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); 60 61 do { 62 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 63 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 64 if (blk_cnt <= 8) { 65 flags |= DWMCI_IDMAC_LD; 66 cnt = data->blocksize * blk_cnt; 67 } else 68 cnt = data->blocksize * 8; 69 70 dwmci_set_idma_desc(cur_idmac, flags, cnt, 71 (u32)bounce_buffer + (i * PAGE_SIZE)); 72 73 if (blk_cnt <= 8) 74 break; 75 blk_cnt -= 8; 76 cur_idmac++; 77 i++; 78 } while(1); 79 80 data_end = (ulong)cur_idmac; 81 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 82 83 ctrl = dwmci_readl(host, DWMCI_CTRL); 84 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 85 dwmci_writel(host, DWMCI_CTRL, ctrl); 86 87 ctrl = dwmci_readl(host, DWMCI_BMOD); 88 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 89 dwmci_writel(host, DWMCI_BMOD, ctrl); 90 91 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 92 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 93 } 94 95 static int dwmci_set_transfer_mode(struct dwmci_host *host, 96 struct mmc_data *data) 97 { 98 unsigned long mode; 99 100 mode = DWMCI_CMD_DATA_EXP; 101 if (data->flags & MMC_DATA_WRITE) 102 mode |= DWMCI_CMD_RW; 103 104 return mode; 105 } 106 107 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 108 struct mmc_data *data) 109 { 110 struct dwmci_host *host = mmc->priv; 111 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 112 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 113 int flags = 0, i; 114 unsigned int timeout = 100000; 115 u32 retry = 10000; 116 u32 mask, ctrl; 117 ulong start = get_timer(0); 118 struct bounce_buffer bbstate; 119 120 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 121 if (get_timer(start) > timeout) { 122 printf("Timeout on data busy\n"); 123 return TIMEOUT; 124 } 125 } 126 127 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 128 129 if (data) { 130 if (data->flags == MMC_DATA_READ) { 131 bounce_buffer_start(&bbstate, (void*)data->dest, 132 data->blocksize * 133 data->blocks, GEN_BB_WRITE); 134 } else { 135 bounce_buffer_start(&bbstate, (void*)data->src, 136 data->blocksize * 137 data->blocks, GEN_BB_READ); 138 } 139 dwmci_prepare_data(host, data, cur_idmac, 140 bbstate.bounce_buffer); 141 } 142 143 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 144 145 if (data) 146 flags = dwmci_set_transfer_mode(host, data); 147 148 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 149 return -1; 150 151 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 152 flags |= DWMCI_CMD_ABORT_STOP; 153 else 154 flags |= DWMCI_CMD_PRV_DAT_WAIT; 155 156 if (cmd->resp_type & MMC_RSP_PRESENT) { 157 flags |= DWMCI_CMD_RESP_EXP; 158 if (cmd->resp_type & MMC_RSP_136) 159 flags |= DWMCI_CMD_RESP_LENGTH; 160 } 161 162 if (cmd->resp_type & MMC_RSP_CRC) 163 flags |= DWMCI_CMD_CHECK_CRC; 164 165 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 166 167 debug("Sending CMD%d\n",cmd->cmdidx); 168 169 dwmci_writel(host, DWMCI_CMD, flags); 170 171 for (i = 0; i < retry; i++) { 172 mask = dwmci_readl(host, DWMCI_RINTSTS); 173 if (mask & DWMCI_INTMSK_CDONE) { 174 if (!data) 175 dwmci_writel(host, DWMCI_RINTSTS, mask); 176 break; 177 } 178 } 179 180 if (i == retry) 181 return TIMEOUT; 182 183 if (mask & DWMCI_INTMSK_RTO) { 184 debug("Response Timeout..\n"); 185 return TIMEOUT; 186 } else if (mask & DWMCI_INTMSK_RE) { 187 debug("Response Error..\n"); 188 return -1; 189 } 190 191 192 if (cmd->resp_type & MMC_RSP_PRESENT) { 193 if (cmd->resp_type & MMC_RSP_136) { 194 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 195 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 196 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 197 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 198 } else { 199 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 200 } 201 } 202 203 if (data) { 204 do { 205 mask = dwmci_readl(host, DWMCI_RINTSTS); 206 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 207 debug("DATA ERROR!\n"); 208 return -1; 209 } 210 } while (!(mask & DWMCI_INTMSK_DTO)); 211 212 dwmci_writel(host, DWMCI_RINTSTS, mask); 213 214 ctrl = dwmci_readl(host, DWMCI_CTRL); 215 ctrl &= ~(DWMCI_DMA_EN); 216 dwmci_writel(host, DWMCI_CTRL, ctrl); 217 218 bounce_buffer_stop(&bbstate); 219 } 220 221 udelay(100); 222 223 return 0; 224 } 225 226 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 227 { 228 u32 div, status; 229 int timeout = 10000; 230 unsigned long sclk; 231 232 if ((freq == host->clock) || (freq == 0)) 233 return 0; 234 /* 235 * If host->get_mmc_clk didn't define, 236 * then assume that host->bus_hz is source clock value. 237 * host->bus_hz should be set from user. 238 */ 239 if (host->get_mmc_clk) 240 sclk = host->get_mmc_clk(host); 241 else if (host->bus_hz) 242 sclk = host->bus_hz; 243 else { 244 printf("Didn't get source clock value..\n"); 245 return -EINVAL; 246 } 247 248 if (sclk == freq) 249 div = 0; /* bypass mode */ 250 else 251 div = DIV_ROUND_UP(sclk, 2 * freq); 252 253 dwmci_writel(host, DWMCI_CLKENA, 0); 254 dwmci_writel(host, DWMCI_CLKSRC, 0); 255 256 dwmci_writel(host, DWMCI_CLKDIV, div); 257 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 258 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 259 260 do { 261 status = dwmci_readl(host, DWMCI_CMD); 262 if (timeout-- < 0) { 263 printf("TIMEOUT error!!\n"); 264 return -ETIMEDOUT; 265 } 266 } while (status & DWMCI_CMD_START); 267 268 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 269 DWMCI_CLKEN_LOW_PWR); 270 271 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 272 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 273 274 timeout = 10000; 275 do { 276 status = dwmci_readl(host, DWMCI_CMD); 277 if (timeout-- < 0) { 278 printf("TIMEOUT error!!\n"); 279 return -ETIMEDOUT; 280 } 281 } while (status & DWMCI_CMD_START); 282 283 host->clock = freq; 284 285 return 0; 286 } 287 288 static void dwmci_set_ios(struct mmc *mmc) 289 { 290 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 291 u32 ctype, regs; 292 293 debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); 294 295 dwmci_setup_bus(host, mmc->clock); 296 switch (mmc->bus_width) { 297 case 8: 298 ctype = DWMCI_CTYPE_8BIT; 299 break; 300 case 4: 301 ctype = DWMCI_CTYPE_4BIT; 302 break; 303 default: 304 ctype = DWMCI_CTYPE_1BIT; 305 break; 306 } 307 308 dwmci_writel(host, DWMCI_CTYPE, ctype); 309 310 regs = dwmci_readl(host, DWMCI_UHS_REG); 311 if (mmc->card_caps & MMC_MODE_DDR_52MHz) 312 regs |= DWMCI_DDR_MODE; 313 else 314 regs &= DWMCI_DDR_MODE; 315 316 dwmci_writel(host, DWMCI_UHS_REG, regs); 317 318 if (host->clksel) 319 host->clksel(host); 320 } 321 322 static int dwmci_init(struct mmc *mmc) 323 { 324 struct dwmci_host *host = mmc->priv; 325 326 if (host->board_init) 327 host->board_init(host); 328 329 dwmci_writel(host, DWMCI_PWREN, 1); 330 331 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 332 debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); 333 return -1; 334 } 335 336 /* Enumerate at 400KHz */ 337 dwmci_setup_bus(host, mmc->cfg->f_min); 338 339 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 340 dwmci_writel(host, DWMCI_INTMASK, 0); 341 342 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 343 344 dwmci_writel(host, DWMCI_IDINTEN, 0); 345 dwmci_writel(host, DWMCI_BMOD, 1); 346 347 if (host->fifoth_val) { 348 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 349 } 350 351 dwmci_writel(host, DWMCI_CLKENA, 0); 352 dwmci_writel(host, DWMCI_CLKSRC, 0); 353 354 return 0; 355 } 356 357 static const struct mmc_ops dwmci_ops = { 358 .send_cmd = dwmci_send_cmd, 359 .set_ios = dwmci_set_ios, 360 .init = dwmci_init, 361 }; 362 363 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 364 { 365 host->cfg.name = host->name; 366 host->cfg.ops = &dwmci_ops; 367 host->cfg.f_min = min_clk; 368 host->cfg.f_max = max_clk; 369 370 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 371 372 host->cfg.host_caps = host->caps; 373 374 if (host->buswidth == 8) { 375 host->cfg.host_caps |= MMC_MODE_8BIT; 376 host->cfg.host_caps &= ~MMC_MODE_4BIT; 377 } else { 378 host->cfg.host_caps |= MMC_MODE_4BIT; 379 host->cfg.host_caps &= ~MMC_MODE_8BIT; 380 } 381 host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; 382 383 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 384 385 host->mmc = mmc_create(&host->cfg, host); 386 if (host->mmc == NULL) 387 return -1; 388 389 return 0; 390 } 391