1 /* 2 * Davinci MMC Controller Driver 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <command.h> 12 #include <errno.h> 13 #include <mmc.h> 14 #include <part.h> 15 #include <malloc.h> 16 #include <asm/io.h> 17 #include <asm/arch/sdmmc_defs.h> 18 19 #define DAVINCI_MAX_BLOCKS (32) 20 #define WATCHDOG_COUNT (100000) 21 22 #define get_val(addr) REG(addr) 23 #define set_val(addr, val) REG(addr) = (val) 24 #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val))) 25 #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val))) 26 27 /* Set davinci clock prescalar value based on the required clock in HZ */ 28 static void dmmc_set_clock(struct mmc *mmc, uint clock) 29 { 30 struct davinci_mmc *host = mmc->priv; 31 struct davinci_mmc_regs *regs = host->reg_base; 32 uint clkrt, sysclk2, act_clock; 33 34 if (clock < mmc->cfg->f_min) 35 clock = mmc->cfg->f_min; 36 if (clock > mmc->cfg->f_max) 37 clock = mmc->cfg->f_max; 38 39 set_val(®s->mmcclk, 0); 40 sysclk2 = host->input_clk; 41 clkrt = (sysclk2 / (2 * clock)) - 1; 42 43 /* Calculate the actual clock for the divider used */ 44 act_clock = (sysclk2 / (2 * (clkrt + 1))); 45 46 /* Adjust divider if actual clock exceeds the required clock */ 47 if (act_clock > clock) 48 clkrt++; 49 50 /* check clock divider boundary and correct it */ 51 if (clkrt > 0xFF) 52 clkrt = 0xFF; 53 54 set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN)); 55 } 56 57 /* Status bit wait loop for MMCST1 */ 58 static int 59 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status) 60 { 61 uint wdog = WATCHDOG_COUNT; 62 63 while (--wdog && ((get_val(®s->mmcst1) & status) != status)) 64 udelay(10); 65 66 if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT)) 67 udelay(100); 68 69 if (wdog == 0) 70 return -ECOMM; 71 72 return 0; 73 } 74 75 /* Busy bit wait loop for MMCST1 */ 76 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs) 77 { 78 uint wdog = WATCHDOG_COUNT; 79 80 while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY)) 81 udelay(10); 82 83 if (wdog == 0) 84 return -ECOMM; 85 86 return 0; 87 } 88 89 /* Status bit wait loop for MMCST0 - Checks for error bits as well */ 90 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, 91 uint *cur_st, uint st_ready, uint st_error) 92 { 93 uint wdog = WATCHDOG_COUNT; 94 uint mmcstatus = *cur_st; 95 96 while (wdog--) { 97 if (mmcstatus & st_ready) { 98 *cur_st = mmcstatus; 99 mmcstatus = get_val(®s->mmcst1); 100 return 0; 101 } else if (mmcstatus & st_error) { 102 if (mmcstatus & MMCST0_TOUTRS) 103 return -ETIMEDOUT; 104 printf("[ ST0 ERROR %x]\n", mmcstatus); 105 /* 106 * Ignore CRC errors as some MMC cards fail to 107 * initialize on DM365-EVM on the SD1 slot 108 */ 109 if (mmcstatus & MMCST0_CRCRS) 110 return 0; 111 return -ECOMM; 112 } 113 udelay(10); 114 115 mmcstatus = get_val(®s->mmcst0); 116 } 117 118 printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus, 119 get_val(®s->mmcst1)); 120 return -ECOMM; 121 } 122 123 /* 124 * Sends a command out on the bus. Takes the mmc pointer, 125 * a command pointer, and an optional data pointer. 126 */ 127 static int 128 dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 129 { 130 struct davinci_mmc *host = mmc->priv; 131 volatile struct davinci_mmc_regs *regs = host->reg_base; 132 uint mmcstatus, status_rdy, status_err; 133 uint i, cmddata, bytes_left = 0; 134 int fifo_words, fifo_bytes, err; 135 char *data_buf = NULL; 136 137 /* Clear status registers */ 138 mmcstatus = get_val(®s->mmcst0); 139 fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8; 140 fifo_bytes = fifo_words << 2; 141 142 /* Wait for any previous busy signal to be cleared */ 143 dmmc_busy_wait(regs); 144 145 cmddata = cmd->cmdidx; 146 cmddata |= MMCCMD_PPLEN; 147 148 /* Send init clock for CMD0 */ 149 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE) 150 cmddata |= MMCCMD_INITCK; 151 152 switch (cmd->resp_type) { 153 case MMC_RSP_R1b: 154 cmddata |= MMCCMD_BSYEXP; 155 /* Fall-through */ 156 case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */ 157 cmddata |= MMCCMD_RSPFMT_R1567; 158 break; 159 case MMC_RSP_R2: 160 cmddata |= MMCCMD_RSPFMT_R2; 161 break; 162 case MMC_RSP_R3: /* R3, R4 */ 163 cmddata |= MMCCMD_RSPFMT_R3; 164 break; 165 } 166 167 set_val(®s->mmcim, 0); 168 169 if (data) { 170 /* clear previous data transfer if any and set new one */ 171 bytes_left = (data->blocksize * data->blocks); 172 173 /* Reset FIFO - Always use 32 byte fifo threshold */ 174 set_val(®s->mmcfifoctl, 175 (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); 176 177 if (host->version == MMC_CTLR_VERSION_2) 178 cmddata |= MMCCMD_DMATRIG; 179 180 cmddata |= MMCCMD_WDATX; 181 if (data->flags == MMC_DATA_READ) { 182 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); 183 } else if (data->flags == MMC_DATA_WRITE) { 184 set_val(®s->mmcfifoctl, 185 (MMCFIFOCTL_FIFOLEV | 186 MMCFIFOCTL_FIFODIR)); 187 cmddata |= MMCCMD_DTRW; 188 } 189 190 set_val(®s->mmctod, 0xFFFF); 191 set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK)); 192 set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK)); 193 194 if (data->flags == MMC_DATA_WRITE) { 195 uint val; 196 data_buf = (char *)data->src; 197 /* For write, fill FIFO with data before issue of CMD */ 198 for (i = 0; (i < fifo_words) && bytes_left; i++) { 199 memcpy((char *)&val, data_buf, 4); 200 set_val(®s->mmcdxr, val); 201 data_buf += 4; 202 bytes_left -= 4; 203 } 204 } 205 } else { 206 set_val(®s->mmcblen, 0); 207 set_val(®s->mmcnblk, 0); 208 } 209 210 set_val(®s->mmctor, 0x1FFF); 211 212 /* Send the command */ 213 set_val(®s->mmcarghl, cmd->cmdarg); 214 set_val(®s->mmccmd, cmddata); 215 216 status_rdy = MMCST0_RSPDNE; 217 status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD | 218 MMCST0_CRCWR | MMCST0_CRCRD); 219 if (cmd->resp_type & MMC_RSP_CRC) 220 status_err |= MMCST0_CRCRS; 221 222 mmcstatus = get_val(®s->mmcst0); 223 err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err); 224 if (err) 225 return err; 226 227 /* For R1b wait for busy done */ 228 if (cmd->resp_type == MMC_RSP_R1b) 229 dmmc_busy_wait(regs); 230 231 /* Collect response from controller for specific commands */ 232 if (mmcstatus & MMCST0_RSPDNE) { 233 /* Copy the response to the response buffer */ 234 if (cmd->resp_type & MMC_RSP_136) { 235 cmd->response[0] = get_val(®s->mmcrsp67); 236 cmd->response[1] = get_val(®s->mmcrsp45); 237 cmd->response[2] = get_val(®s->mmcrsp23); 238 cmd->response[3] = get_val(®s->mmcrsp01); 239 } else if (cmd->resp_type & MMC_RSP_PRESENT) { 240 cmd->response[0] = get_val(®s->mmcrsp67); 241 } 242 } 243 244 if (data == NULL) 245 return 0; 246 247 if (data->flags == MMC_DATA_READ) { 248 /* check for DATDNE along with DRRDY as the controller might 249 * set the DATDNE without DRRDY for smaller transfers with 250 * less than FIFO threshold bytes 251 */ 252 status_rdy = MMCST0_DRRDY | MMCST0_DATDNE; 253 status_err = MMCST0_TOUTRD | MMCST0_CRCRD; 254 data_buf = data->dest; 255 } else { 256 status_rdy = MMCST0_DXRDY | MMCST0_DATDNE; 257 status_err = MMCST0_CRCWR; 258 } 259 260 /* Wait until all of the blocks are transferred */ 261 while (bytes_left) { 262 err = dmmc_check_status(regs, &mmcstatus, status_rdy, 263 status_err); 264 if (err) 265 return err; 266 267 if (data->flags == MMC_DATA_READ) { 268 /* 269 * MMC controller sets the Data receive ready bit 270 * (DRRDY) in MMCST0 even before the entire FIFO is 271 * full. This results in erratic behavior if we start 272 * reading the FIFO soon after DRRDY. Wait for the 273 * FIFO full bit in MMCST1 for proper FIFO clearing. 274 */ 275 if (bytes_left > fifo_bytes) 276 dmmc_wait_fifo_status(regs, 0x4a); 277 else if (bytes_left == fifo_bytes) { 278 dmmc_wait_fifo_status(regs, 0x40); 279 if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) 280 udelay(600); 281 } 282 283 for (i = 0; bytes_left && (i < fifo_words); i++) { 284 cmddata = get_val(®s->mmcdrr); 285 memcpy(data_buf, (char *)&cmddata, 4); 286 data_buf += 4; 287 bytes_left -= 4; 288 } 289 } else { 290 /* 291 * MMC controller sets the Data transmit ready bit 292 * (DXRDY) in MMCST0 even before the entire FIFO is 293 * empty. This results in erratic behavior if we start 294 * writing the FIFO soon after DXRDY. Wait for the 295 * FIFO empty bit in MMCST1 for proper FIFO clearing. 296 */ 297 dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP); 298 for (i = 0; bytes_left && (i < fifo_words); i++) { 299 memcpy((char *)&cmddata, data_buf, 4); 300 set_val(®s->mmcdxr, cmddata); 301 data_buf += 4; 302 bytes_left -= 4; 303 } 304 dmmc_busy_wait(regs); 305 } 306 } 307 308 err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err); 309 if (err) 310 return err; 311 312 return 0; 313 } 314 315 /* Initialize Davinci MMC controller */ 316 static int dmmc_init(struct mmc *mmc) 317 { 318 struct davinci_mmc *host = mmc->priv; 319 struct davinci_mmc_regs *regs = host->reg_base; 320 321 /* Clear status registers explicitly - soft reset doesn't clear it 322 * If Uboot is invoked from UBL with SDMMC Support, the status 323 * registers can have uncleared bits 324 */ 325 get_val(®s->mmcst0); 326 get_val(®s->mmcst1); 327 328 /* Hold software reset */ 329 set_bit(®s->mmcctl, MMCCTL_DATRST); 330 set_bit(®s->mmcctl, MMCCTL_CMDRST); 331 udelay(10); 332 333 set_val(®s->mmcclk, 0x0); 334 set_val(®s->mmctor, 0x1FFF); 335 set_val(®s->mmctod, 0xFFFF); 336 337 /* Clear software reset */ 338 clear_bit(®s->mmcctl, MMCCTL_DATRST); 339 clear_bit(®s->mmcctl, MMCCTL_CMDRST); 340 341 udelay(10); 342 343 /* Reset FIFO - Always use the maximum fifo threshold */ 344 set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); 345 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); 346 347 return 0; 348 } 349 350 /* Set buswidth or clock as indicated by the MMC framework */ 351 static int dmmc_set_ios(struct mmc *mmc) 352 { 353 struct davinci_mmc *host = mmc->priv; 354 struct davinci_mmc_regs *regs = host->reg_base; 355 356 /* Set the bus width */ 357 if (mmc->bus_width == 4) 358 set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); 359 else 360 clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); 361 362 /* Set clock speed */ 363 if (mmc->clock) 364 dmmc_set_clock(mmc, mmc->clock); 365 366 return 0; 367 } 368 369 static const struct mmc_ops dmmc_ops = { 370 .send_cmd = dmmc_send_cmd, 371 .set_ios = dmmc_set_ios, 372 .init = dmmc_init, 373 }; 374 375 /* Called from board_mmc_init during startup. Can be called multiple times 376 * depending on the number of slots available on board and controller 377 */ 378 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) 379 { 380 host->cfg.name = "davinci"; 381 host->cfg.ops = &dmmc_ops; 382 host->cfg.f_min = 200000; 383 host->cfg.f_max = 25000000; 384 host->cfg.voltages = host->voltages; 385 host->cfg.host_caps = host->host_caps; 386 387 host->cfg.b_max = DAVINCI_MAX_BLOCKS; 388 389 mmc_create(&host->cfg, host); 390 391 return 0; 392 } 393