1 /* 2 * Davinci MMC Controller Driver 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <config.h> 22 #include <common.h> 23 #include <command.h> 24 #include <mmc.h> 25 #include <part.h> 26 #include <malloc.h> 27 #include <asm/io.h> 28 #include <asm/arch/sdmmc_defs.h> 29 30 #define DAVINCI_MAX_BLOCKS (32) 31 #define WATCHDOG_COUNT (100000) 32 33 #define get_val(addr) REG(addr) 34 #define set_val(addr, val) REG(addr) = (val) 35 #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val))) 36 #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val))) 37 38 /* Set davinci clock prescalar value based on the required clock in HZ */ 39 static void dmmc_set_clock(struct mmc *mmc, uint clock) 40 { 41 struct davinci_mmc *host = mmc->priv; 42 struct davinci_mmc_regs *regs = host->reg_base; 43 uint clkrt, sysclk2, act_clock; 44 45 if (clock < mmc->f_min) 46 clock = mmc->f_min; 47 if (clock > mmc->f_max) 48 clock = mmc->f_max; 49 50 set_val(®s->mmcclk, 0); 51 sysclk2 = host->input_clk; 52 clkrt = (sysclk2 / (2 * clock)) - 1; 53 54 /* Calculate the actual clock for the divider used */ 55 act_clock = (sysclk2 / (2 * (clkrt + 1))); 56 57 /* Adjust divider if actual clock exceeds the required clock */ 58 if (act_clock > clock) 59 clkrt++; 60 61 /* check clock divider boundary and correct it */ 62 if (clkrt > 0xFF) 63 clkrt = 0xFF; 64 65 set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN)); 66 } 67 68 /* Status bit wait loop for MMCST1 */ 69 static int 70 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status) 71 { 72 uint wdog = WATCHDOG_COUNT; 73 74 while (--wdog && ((get_val(®s->mmcst1) & status) != status)) 75 udelay(10); 76 77 if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT)) 78 udelay(100); 79 80 if (wdog == 0) 81 return COMM_ERR; 82 83 return 0; 84 } 85 86 /* Busy bit wait loop for MMCST1 */ 87 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs) 88 { 89 uint wdog = WATCHDOG_COUNT; 90 91 while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY)) 92 udelay(10); 93 94 if (wdog == 0) 95 return COMM_ERR; 96 97 return 0; 98 } 99 100 /* Status bit wait loop for MMCST0 - Checks for error bits as well */ 101 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, 102 uint *cur_st, uint st_ready, uint st_error) 103 { 104 uint wdog = WATCHDOG_COUNT; 105 uint mmcstatus = *cur_st; 106 107 while (wdog--) { 108 if (mmcstatus & st_ready) { 109 *cur_st = mmcstatus; 110 mmcstatus = get_val(®s->mmcst1); 111 return 0; 112 } else if (mmcstatus & st_error) { 113 if (mmcstatus & MMCST0_TOUTRS) 114 return TIMEOUT; 115 printf("[ ST0 ERROR %x]\n", mmcstatus); 116 /* 117 * Ignore CRC errors as some MMC cards fail to 118 * initialize on DM365-EVM on the SD1 slot 119 */ 120 if (mmcstatus & MMCST0_CRCRS) 121 return 0; 122 return COMM_ERR; 123 } 124 udelay(10); 125 126 mmcstatus = get_val(®s->mmcst0); 127 } 128 129 printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus, 130 get_val(®s->mmcst1)); 131 return COMM_ERR; 132 } 133 134 /* 135 * Sends a command out on the bus. Takes the mmc pointer, 136 * a command pointer, and an optional data pointer. 137 */ 138 static int 139 dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 140 { 141 struct davinci_mmc *host = mmc->priv; 142 volatile struct davinci_mmc_regs *regs = host->reg_base; 143 uint mmcstatus, status_rdy, status_err; 144 uint i, cmddata, bytes_left = 0; 145 int fifo_words, fifo_bytes, err; 146 char *data_buf = NULL; 147 148 /* Clear status registers */ 149 mmcstatus = get_val(®s->mmcst0); 150 fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8; 151 fifo_bytes = fifo_words << 2; 152 153 /* Wait for any previous busy signal to be cleared */ 154 dmmc_busy_wait(regs); 155 156 cmddata = cmd->cmdidx; 157 cmddata |= MMCCMD_PPLEN; 158 159 /* Send init clock for CMD0 */ 160 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE) 161 cmddata |= MMCCMD_INITCK; 162 163 switch (cmd->resp_type) { 164 case MMC_RSP_R1b: 165 cmddata |= MMCCMD_BSYEXP; 166 /* Fall-through */ 167 case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */ 168 cmddata |= MMCCMD_RSPFMT_R1567; 169 break; 170 case MMC_RSP_R2: 171 cmddata |= MMCCMD_RSPFMT_R2; 172 break; 173 case MMC_RSP_R3: /* R3, R4 */ 174 cmddata |= MMCCMD_RSPFMT_R3; 175 break; 176 } 177 178 set_val(®s->mmcim, 0); 179 180 if (data) { 181 /* clear previous data transfer if any and set new one */ 182 bytes_left = (data->blocksize * data->blocks); 183 184 /* Reset FIFO - Always use 32 byte fifo threshold */ 185 set_val(®s->mmcfifoctl, 186 (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); 187 188 if (host->version == MMC_CTLR_VERSION_2) 189 cmddata |= MMCCMD_DMATRIG; 190 191 cmddata |= MMCCMD_WDATX; 192 if (data->flags == MMC_DATA_READ) { 193 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); 194 } else if (data->flags == MMC_DATA_WRITE) { 195 set_val(®s->mmcfifoctl, 196 (MMCFIFOCTL_FIFOLEV | 197 MMCFIFOCTL_FIFODIR)); 198 cmddata |= MMCCMD_DTRW; 199 } 200 201 set_val(®s->mmctod, 0xFFFF); 202 set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK)); 203 set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK)); 204 205 if (data->flags == MMC_DATA_WRITE) { 206 uint val; 207 data_buf = (char *)data->src; 208 /* For write, fill FIFO with data before issue of CMD */ 209 for (i = 0; (i < fifo_words) && bytes_left; i++) { 210 memcpy((char *)&val, data_buf, 4); 211 set_val(®s->mmcdxr, val); 212 data_buf += 4; 213 bytes_left -= 4; 214 } 215 } 216 } else { 217 set_val(®s->mmcblen, 0); 218 set_val(®s->mmcnblk, 0); 219 } 220 221 set_val(®s->mmctor, 0x1FFF); 222 223 /* Send the command */ 224 set_val(®s->mmcarghl, cmd->cmdarg); 225 set_val(®s->mmccmd, cmddata); 226 227 status_rdy = MMCST0_RSPDNE; 228 status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD | 229 MMCST0_CRCWR | MMCST0_CRCRD); 230 if (cmd->resp_type & MMC_RSP_CRC) 231 status_err |= MMCST0_CRCRS; 232 233 mmcstatus = get_val(®s->mmcst0); 234 err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err); 235 if (err) 236 return err; 237 238 /* For R1b wait for busy done */ 239 if (cmd->resp_type == MMC_RSP_R1b) 240 dmmc_busy_wait(regs); 241 242 /* Collect response from controller for specific commands */ 243 if (mmcstatus & MMCST0_RSPDNE) { 244 /* Copy the response to the response buffer */ 245 if (cmd->resp_type & MMC_RSP_136) { 246 cmd->response[0] = get_val(®s->mmcrsp67); 247 cmd->response[1] = get_val(®s->mmcrsp45); 248 cmd->response[2] = get_val(®s->mmcrsp23); 249 cmd->response[3] = get_val(®s->mmcrsp01); 250 } else if (cmd->resp_type & MMC_RSP_PRESENT) { 251 cmd->response[0] = get_val(®s->mmcrsp67); 252 } 253 } 254 255 if (data == NULL) 256 return 0; 257 258 if (data->flags == MMC_DATA_READ) { 259 /* check for DATDNE along with DRRDY as the controller might 260 * set the DATDNE without DRRDY for smaller transfers with 261 * less than FIFO threshold bytes 262 */ 263 status_rdy = MMCST0_DRRDY | MMCST0_DATDNE; 264 status_err = MMCST0_TOUTRD | MMCST0_CRCRD; 265 data_buf = data->dest; 266 } else { 267 status_rdy = MMCST0_DXRDY | MMCST0_DATDNE; 268 status_err = MMCST0_CRCWR; 269 } 270 271 /* Wait until all of the blocks are transferred */ 272 while (bytes_left) { 273 err = dmmc_check_status(regs, &mmcstatus, status_rdy, 274 status_err); 275 if (err) 276 return err; 277 278 if (data->flags == MMC_DATA_READ) { 279 /* 280 * MMC controller sets the Data receive ready bit 281 * (DRRDY) in MMCST0 even before the entire FIFO is 282 * full. This results in erratic behavior if we start 283 * reading the FIFO soon after DRRDY. Wait for the 284 * FIFO full bit in MMCST1 for proper FIFO clearing. 285 */ 286 if (bytes_left > fifo_bytes) 287 dmmc_wait_fifo_status(regs, 0x4a); 288 else if (bytes_left == fifo_bytes) 289 dmmc_wait_fifo_status(regs, 0x40); 290 291 for (i = 0; bytes_left && (i < fifo_words); i++) { 292 cmddata = get_val(®s->mmcdrr); 293 memcpy(data_buf, (char *)&cmddata, 4); 294 data_buf += 4; 295 bytes_left -= 4; 296 } 297 } else { 298 /* 299 * MMC controller sets the Data transmit ready bit 300 * (DXRDY) in MMCST0 even before the entire FIFO is 301 * empty. This results in erratic behavior if we start 302 * writing the FIFO soon after DXRDY. Wait for the 303 * FIFO empty bit in MMCST1 for proper FIFO clearing. 304 */ 305 dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP); 306 for (i = 0; bytes_left && (i < fifo_words); i++) { 307 memcpy((char *)&cmddata, data_buf, 4); 308 set_val(®s->mmcdxr, cmddata); 309 data_buf += 4; 310 bytes_left -= 4; 311 } 312 dmmc_busy_wait(regs); 313 } 314 } 315 316 err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err); 317 if (err) 318 return err; 319 320 return 0; 321 } 322 323 /* Initialize Davinci MMC controller */ 324 static int dmmc_init(struct mmc *mmc) 325 { 326 struct davinci_mmc *host = mmc->priv; 327 struct davinci_mmc_regs *regs = host->reg_base; 328 329 /* Clear status registers explicitly - soft reset doesn't clear it 330 * If Uboot is invoked from UBL with SDMMC Support, the status 331 * registers can have uncleared bits 332 */ 333 get_val(®s->mmcst0); 334 get_val(®s->mmcst1); 335 336 /* Hold software reset */ 337 set_bit(®s->mmcctl, MMCCTL_DATRST); 338 set_bit(®s->mmcctl, MMCCTL_CMDRST); 339 udelay(10); 340 341 set_val(®s->mmcclk, 0x0); 342 set_val(®s->mmctor, 0x1FFF); 343 set_val(®s->mmctod, 0xFFFF); 344 345 /* Clear software reset */ 346 clear_bit(®s->mmcctl, MMCCTL_DATRST); 347 clear_bit(®s->mmcctl, MMCCTL_CMDRST); 348 349 udelay(10); 350 351 /* Reset FIFO - Always use the maximum fifo threshold */ 352 set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); 353 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); 354 355 return 0; 356 } 357 358 /* Set buswidth or clock as indicated by the GENERIC_MMC framework */ 359 static void dmmc_set_ios(struct mmc *mmc) 360 { 361 struct davinci_mmc *host = mmc->priv; 362 struct davinci_mmc_regs *regs = host->reg_base; 363 364 /* Set the bus width */ 365 if (mmc->bus_width == 4) 366 set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); 367 else 368 clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); 369 370 /* Set clock speed */ 371 if (mmc->clock) 372 dmmc_set_clock(mmc, mmc->clock); 373 } 374 375 /* Called from board_mmc_init during startup. Can be called multiple times 376 * depending on the number of slots available on board and controller 377 */ 378 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) 379 { 380 struct mmc *mmc; 381 382 mmc = malloc(sizeof(struct mmc)); 383 memset(mmc, 0, sizeof(struct mmc)); 384 385 sprintf(mmc->name, "davinci"); 386 mmc->priv = host; 387 mmc->send_cmd = dmmc_send_cmd; 388 mmc->set_ios = dmmc_set_ios; 389 mmc->init = dmmc_init; 390 mmc->getcd = NULL; 391 mmc->getwp = NULL; 392 393 mmc->f_min = 200000; 394 mmc->f_max = 25000000; 395 mmc->voltages = host->voltages; 396 mmc->host_caps = host->host_caps; 397 398 mmc->b_max = DAVINCI_MAX_BLOCKS; 399 400 mmc_register(mmc); 401 402 return 0; 403 } 404