1 /* 2 * Davinci MMC Controller Driver 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <config.h> 22 #include <common.h> 23 #include <command.h> 24 #include <mmc.h> 25 #include <part.h> 26 #include <malloc.h> 27 #include <asm/io.h> 28 #include <asm/arch/sdmmc_defs.h> 29 30 #define DAVINCI_MAX_BLOCKS (32) 31 #define WATCHDOG_COUNT (100000) 32 33 #define get_val(addr) REG(addr) 34 #define set_val(addr, val) REG(addr) = (val) 35 #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val))) 36 #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val))) 37 38 /* Set davinci clock prescalar value based on the required clock in HZ */ 39 static void dmmc_set_clock(struct mmc *mmc, uint clock) 40 { 41 struct davinci_mmc *host = mmc->priv; 42 struct davinci_mmc_regs *regs = host->reg_base; 43 uint clkrt, sysclk2, act_clock; 44 45 if (clock < mmc->f_min) 46 clock = mmc->f_min; 47 if (clock > mmc->f_max) 48 clock = mmc->f_max; 49 50 set_val(®s->mmcclk, 0); 51 sysclk2 = host->input_clk; 52 clkrt = (sysclk2 / (2 * clock)) - 1; 53 54 /* Calculate the actual clock for the divider used */ 55 act_clock = (sysclk2 / (2 * (clkrt + 1))); 56 57 /* Adjust divider if actual clock exceeds the required clock */ 58 if (act_clock > clock) 59 clkrt++; 60 61 /* check clock divider boundary and correct it */ 62 if (clkrt > 0xFF) 63 clkrt = 0xFF; 64 65 set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN)); 66 } 67 68 /* Status bit wait loop for MMCST1 */ 69 static int 70 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status) 71 { 72 uint mmcstatus1, wdog = WATCHDOG_COUNT; 73 mmcstatus1 = get_val(®s->mmcst1); 74 while (--wdog && ((get_val(®s->mmcst1) & status) != status)) 75 udelay(10); 76 77 if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT)) 78 udelay(100); 79 80 if (wdog == 0) 81 return COMM_ERR; 82 83 return 0; 84 } 85 86 /* Busy bit wait loop for MMCST1 */ 87 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs) 88 { 89 uint mmcstatus1, wdog = WATCHDOG_COUNT; 90 91 mmcstatus1 = get_val(®s->mmcst1); 92 while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY)) 93 udelay(10); 94 95 if (wdog == 0) 96 return COMM_ERR; 97 98 return 0; 99 } 100 101 /* Status bit wait loop for MMCST0 - Checks for error bits as well */ 102 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, 103 uint *cur_st, uint st_ready, uint st_error) 104 { 105 uint wdog = WATCHDOG_COUNT; 106 uint mmcstatus = *cur_st; 107 108 while (wdog--) { 109 if (mmcstatus & st_ready) { 110 *cur_st = mmcstatus; 111 mmcstatus = get_val(®s->mmcst1); 112 return 0; 113 } else if (mmcstatus & st_error) { 114 if (mmcstatus & MMCST0_TOUTRS) 115 return TIMEOUT; 116 printf("[ ST0 ERROR %x]\n", mmcstatus); 117 /* 118 * Ignore CRC errors as some MMC cards fail to 119 * initialize on DM365-EVM on the SD1 slot 120 */ 121 if (mmcstatus & MMCST0_CRCRS) 122 return 0; 123 return COMM_ERR; 124 } 125 udelay(10); 126 127 mmcstatus = get_val(®s->mmcst0); 128 } 129 130 printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus, 131 get_val(®s->mmcst1)); 132 return COMM_ERR; 133 } 134 135 /* 136 * Sends a command out on the bus. Takes the mmc pointer, 137 * a command pointer, and an optional data pointer. 138 */ 139 static int 140 dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 141 { 142 struct davinci_mmc *host = mmc->priv; 143 volatile struct davinci_mmc_regs *regs = host->reg_base; 144 uint mmcstatus, status_rdy, status_err; 145 uint i, cmddata, bytes_left = 0; 146 int fifo_words, fifo_bytes, err; 147 char *data_buf = NULL; 148 149 /* Clear status registers */ 150 mmcstatus = get_val(®s->mmcst0); 151 fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8; 152 fifo_bytes = fifo_words << 2; 153 154 /* Wait for any previous busy signal to be cleared */ 155 dmmc_busy_wait(regs); 156 157 cmddata = cmd->cmdidx; 158 cmddata |= MMCCMD_PPLEN; 159 160 /* Send init clock for CMD0 */ 161 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE) 162 cmddata |= MMCCMD_INITCK; 163 164 switch (cmd->resp_type) { 165 case MMC_RSP_R1b: 166 cmddata |= MMCCMD_BSYEXP; 167 /* Fall-through */ 168 case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */ 169 cmddata |= MMCCMD_RSPFMT_R1567; 170 break; 171 case MMC_RSP_R2: 172 cmddata |= MMCCMD_RSPFMT_R2; 173 break; 174 case MMC_RSP_R3: /* R3, R4 */ 175 cmddata |= MMCCMD_RSPFMT_R3; 176 break; 177 } 178 179 set_val(®s->mmcim, 0); 180 181 if (data) { 182 /* clear previous data transfer if any and set new one */ 183 bytes_left = (data->blocksize * data->blocks); 184 185 /* Reset FIFO - Always use 32 byte fifo threshold */ 186 set_val(®s->mmcfifoctl, 187 (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); 188 189 if (host->version == MMC_CTLR_VERSION_2) 190 cmddata |= MMCCMD_DMATRIG; 191 192 cmddata |= MMCCMD_WDATX; 193 if (data->flags == MMC_DATA_READ) { 194 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); 195 } else if (data->flags == MMC_DATA_WRITE) { 196 set_val(®s->mmcfifoctl, 197 (MMCFIFOCTL_FIFOLEV | 198 MMCFIFOCTL_FIFODIR)); 199 cmddata |= MMCCMD_DTRW; 200 } 201 202 set_val(®s->mmctod, 0xFFFF); 203 set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK)); 204 set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK)); 205 206 if (data->flags == MMC_DATA_WRITE) { 207 uint val; 208 data_buf = (char *)data->src; 209 /* For write, fill FIFO with data before issue of CMD */ 210 for (i = 0; (i < fifo_words) && bytes_left; i++) { 211 memcpy((char *)&val, data_buf, 4); 212 set_val(®s->mmcdxr, val); 213 data_buf += 4; 214 bytes_left -= 4; 215 } 216 } 217 } else { 218 set_val(®s->mmcblen, 0); 219 set_val(®s->mmcnblk, 0); 220 } 221 222 set_val(®s->mmctor, 0x1FFF); 223 224 /* Send the command */ 225 set_val(®s->mmcarghl, cmd->cmdarg); 226 set_val(®s->mmccmd, cmddata); 227 228 status_rdy = MMCST0_RSPDNE; 229 status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD | 230 MMCST0_CRCWR | MMCST0_CRCRD); 231 if (cmd->resp_type & MMC_RSP_CRC) 232 status_err |= MMCST0_CRCRS; 233 234 mmcstatus = get_val(®s->mmcst0); 235 err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err); 236 if (err) 237 return err; 238 239 /* For R1b wait for busy done */ 240 if (cmd->resp_type == MMC_RSP_R1b) 241 dmmc_busy_wait(regs); 242 243 /* Collect response from controller for specific commands */ 244 if (mmcstatus & MMCST0_RSPDNE) { 245 /* Copy the response to the response buffer */ 246 if (cmd->resp_type & MMC_RSP_136) { 247 cmd->response[0] = get_val(®s->mmcrsp67); 248 cmd->response[1] = get_val(®s->mmcrsp45); 249 cmd->response[2] = get_val(®s->mmcrsp23); 250 cmd->response[3] = get_val(®s->mmcrsp01); 251 } else if (cmd->resp_type & MMC_RSP_PRESENT) { 252 cmd->response[0] = get_val(®s->mmcrsp67); 253 } 254 } 255 256 if (data == NULL) 257 return 0; 258 259 if (data->flags == MMC_DATA_READ) { 260 /* check for DATDNE along with DRRDY as the controller might 261 * set the DATDNE without DRRDY for smaller transfers with 262 * less than FIFO threshold bytes 263 */ 264 status_rdy = MMCST0_DRRDY | MMCST0_DATDNE; 265 status_err = MMCST0_TOUTRD | MMCST0_CRCRD; 266 data_buf = data->dest; 267 } else { 268 status_rdy = MMCST0_DXRDY | MMCST0_DATDNE; 269 status_err = MMCST0_CRCWR; 270 } 271 272 /* Wait until all of the blocks are transferred */ 273 while (bytes_left) { 274 err = dmmc_check_status(regs, &mmcstatus, status_rdy, 275 status_err); 276 if (err) 277 return err; 278 279 if (data->flags == MMC_DATA_READ) { 280 /* 281 * MMC controller sets the Data receive ready bit 282 * (DRRDY) in MMCST0 even before the entire FIFO is 283 * full. This results in erratic behavior if we start 284 * reading the FIFO soon after DRRDY. Wait for the 285 * FIFO full bit in MMCST1 for proper FIFO clearing. 286 */ 287 if (bytes_left > fifo_bytes) 288 dmmc_wait_fifo_status(regs, 0x4a); 289 else if (bytes_left == fifo_bytes) 290 dmmc_wait_fifo_status(regs, 0x40); 291 292 for (i = 0; bytes_left && (i < fifo_words); i++) { 293 cmddata = get_val(®s->mmcdrr); 294 memcpy(data_buf, (char *)&cmddata, 4); 295 data_buf += 4; 296 bytes_left -= 4; 297 } 298 } else { 299 /* 300 * MMC controller sets the Data transmit ready bit 301 * (DXRDY) in MMCST0 even before the entire FIFO is 302 * empty. This results in erratic behavior if we start 303 * writing the FIFO soon after DXRDY. Wait for the 304 * FIFO empty bit in MMCST1 for proper FIFO clearing. 305 */ 306 dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP); 307 for (i = 0; bytes_left && (i < fifo_words); i++) { 308 memcpy((char *)&cmddata, data_buf, 4); 309 set_val(®s->mmcdxr, cmddata); 310 data_buf += 4; 311 bytes_left -= 4; 312 } 313 dmmc_busy_wait(regs); 314 } 315 } 316 317 err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err); 318 if (err) 319 return err; 320 321 return 0; 322 } 323 324 /* Initialize Davinci MMC controller */ 325 static int dmmc_init(struct mmc *mmc) 326 { 327 struct davinci_mmc *host = mmc->priv; 328 struct davinci_mmc_regs *regs = host->reg_base; 329 330 /* Clear status registers explicitly - soft reset doesn't clear it 331 * If Uboot is invoked from UBL with SDMMC Support, the status 332 * registers can have uncleared bits 333 */ 334 get_val(®s->mmcst0); 335 get_val(®s->mmcst1); 336 337 /* Hold software reset */ 338 set_bit(®s->mmcctl, MMCCTL_DATRST); 339 set_bit(®s->mmcctl, MMCCTL_CMDRST); 340 udelay(10); 341 342 set_val(®s->mmcclk, 0x0); 343 set_val(®s->mmctor, 0x1FFF); 344 set_val(®s->mmctod, 0xFFFF); 345 346 /* Clear software reset */ 347 clear_bit(®s->mmcctl, MMCCTL_DATRST); 348 clear_bit(®s->mmcctl, MMCCTL_CMDRST); 349 350 udelay(10); 351 352 /* Reset FIFO - Always use the maximum fifo threshold */ 353 set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); 354 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); 355 356 return 0; 357 } 358 359 /* Set buswidth or clock as indicated by the GENERIC_MMC framework */ 360 static void dmmc_set_ios(struct mmc *mmc) 361 { 362 struct davinci_mmc *host = mmc->priv; 363 struct davinci_mmc_regs *regs = host->reg_base; 364 365 /* Set the bus width */ 366 if (mmc->bus_width == 4) 367 set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); 368 else 369 clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); 370 371 /* Set clock speed */ 372 if (mmc->clock) 373 dmmc_set_clock(mmc, mmc->clock); 374 } 375 376 /* Called from board_mmc_init during startup. Can be called multiple times 377 * depending on the number of slots available on board and controller 378 */ 379 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) 380 { 381 struct mmc *mmc; 382 383 mmc = malloc(sizeof(struct mmc)); 384 memset(mmc, 0, sizeof(struct mmc)); 385 386 sprintf(mmc->name, "davinci"); 387 mmc->priv = host; 388 mmc->send_cmd = dmmc_send_cmd; 389 mmc->set_ios = dmmc_set_ios; 390 mmc->init = dmmc_init; 391 392 mmc->f_min = 200000; 393 mmc->f_max = 25000000; 394 mmc->voltages = host->voltages; 395 mmc->host_caps = host->host_caps; 396 397 mmc->b_max = DAVINCI_MAX_BLOCKS; 398 399 mmc_register(mmc); 400 401 return 0; 402 } 403