1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Davinci MMC Controller Driver
4 *
5 * Copyright (C) 2010 Texas Instruments Incorporated
6 */
7
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <mmc.h>
13 #include <command.h>
14 #include <part.h>
15 #include <malloc.h>
16 #include <asm/io.h>
17 #include <asm/arch/sdmmc_defs.h>
18 #include <asm-generic/gpio.h>
19
20 #define DAVINCI_MAX_BLOCKS (32)
21 #define WATCHDOG_COUNT (100000)
22
23 #define get_val(addr) REG(addr)
24 #define set_val(addr, val) REG(addr) = (val)
25 #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
26 #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
27
28 #ifdef CONFIG_DM_MMC
29 struct davinci_of_data {
30 const char *name;
31 u8 version;
32 };
33
34 /* Davinci MMC board definitions */
35 struct davinci_mmc_priv {
36 struct davinci_mmc_regs *reg_base; /* Register base address */
37 uint input_clk; /* Input clock to MMC controller */
38 uint version; /* MMC Controller version */
39 struct gpio_desc cd_gpio; /* Card Detect GPIO */
40 struct gpio_desc wp_gpio; /* Write Protect GPIO */
41 };
42
43 struct davinci_mmc_plat
44 {
45 struct mmc_config cfg;
46 struct mmc mmc;
47 };
48 #endif
49
50 /* Set davinci clock prescalar value based on the required clock in HZ */
51 #if !CONFIG_IS_ENABLED(DM_MMC)
dmmc_set_clock(struct mmc * mmc,uint clock)52 static void dmmc_set_clock(struct mmc *mmc, uint clock)
53 {
54 struct davinci_mmc *host = mmc->priv;
55 #else
56
57 static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
58 {
59 struct davinci_mmc_priv *host = dev_get_priv(dev);
60 struct mmc *mmc = mmc_get_mmc_dev(dev);
61 #endif
62 struct davinci_mmc_regs *regs = host->reg_base;
63 uint clkrt, sysclk2, act_clock;
64
65 if (clock < mmc->cfg->f_min)
66 clock = mmc->cfg->f_min;
67 if (clock > mmc->cfg->f_max)
68 clock = mmc->cfg->f_max;
69
70 set_val(®s->mmcclk, 0);
71 sysclk2 = host->input_clk;
72 clkrt = (sysclk2 / (2 * clock)) - 1;
73
74 /* Calculate the actual clock for the divider used */
75 act_clock = (sysclk2 / (2 * (clkrt + 1)));
76
77 /* Adjust divider if actual clock exceeds the required clock */
78 if (act_clock > clock)
79 clkrt++;
80
81 /* check clock divider boundary and correct it */
82 if (clkrt > 0xFF)
83 clkrt = 0xFF;
84
85 set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
86 }
87
88 /* Status bit wait loop for MMCST1 */
89 static int
90 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
91 {
92 uint wdog = WATCHDOG_COUNT;
93
94 while (--wdog && ((get_val(®s->mmcst1) & status) != status))
95 udelay(10);
96
97 if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
98 udelay(100);
99
100 if (wdog == 0)
101 return -ECOMM;
102
103 return 0;
104 }
105
106 /* Busy bit wait loop for MMCST1 */
107 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
108 {
109 uint wdog = WATCHDOG_COUNT;
110
111 while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
112 udelay(10);
113
114 if (wdog == 0)
115 return -ECOMM;
116
117 return 0;
118 }
119
120 /* Status bit wait loop for MMCST0 - Checks for error bits as well */
121 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
122 uint *cur_st, uint st_ready, uint st_error)
123 {
124 uint wdog = WATCHDOG_COUNT;
125 uint mmcstatus = *cur_st;
126
127 while (wdog--) {
128 if (mmcstatus & st_ready) {
129 *cur_st = mmcstatus;
130 mmcstatus = get_val(®s->mmcst1);
131 return 0;
132 } else if (mmcstatus & st_error) {
133 if (mmcstatus & MMCST0_TOUTRS)
134 return -ETIMEDOUT;
135 printf("[ ST0 ERROR %x]\n", mmcstatus);
136 /*
137 * Ignore CRC errors as some MMC cards fail to
138 * initialize on DM365-EVM on the SD1 slot
139 */
140 if (mmcstatus & MMCST0_CRCRS)
141 return 0;
142 return -ECOMM;
143 }
144 udelay(10);
145
146 mmcstatus = get_val(®s->mmcst0);
147 }
148
149 printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
150 get_val(®s->mmcst1));
151 return -ECOMM;
152 }
153
154 /*
155 * Sends a command out on the bus. Takes the device pointer,
156 * a command pointer, and an optional data pointer.
157 */
158 #if !CONFIG_IS_ENABLED(DM_MMC)
159 static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
160 {
161 struct davinci_mmc *host = mmc->priv;
162 #else
163 static int
164 davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
165 {
166 struct davinci_mmc_priv *host = dev_get_priv(dev);
167 #endif
168 volatile struct davinci_mmc_regs *regs = host->reg_base;
169 uint mmcstatus, status_rdy, status_err;
170 uint i, cmddata, bytes_left = 0;
171 int fifo_words, fifo_bytes, err;
172 char *data_buf = NULL;
173
174 /* Clear status registers */
175 mmcstatus = get_val(®s->mmcst0);
176 fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
177 fifo_bytes = fifo_words << 2;
178
179 /* Wait for any previous busy signal to be cleared */
180 dmmc_busy_wait(regs);
181
182 cmddata = cmd->cmdidx;
183 cmddata |= MMCCMD_PPLEN;
184
185 /* Send init clock for CMD0 */
186 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
187 cmddata |= MMCCMD_INITCK;
188
189 switch (cmd->resp_type) {
190 case MMC_RSP_R1b:
191 cmddata |= MMCCMD_BSYEXP;
192 /* Fall-through */
193 case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
194 cmddata |= MMCCMD_RSPFMT_R1567;
195 break;
196 case MMC_RSP_R2:
197 cmddata |= MMCCMD_RSPFMT_R2;
198 break;
199 case MMC_RSP_R3: /* R3, R4 */
200 cmddata |= MMCCMD_RSPFMT_R3;
201 break;
202 }
203
204 set_val(®s->mmcim, 0);
205
206 if (data) {
207 /* clear previous data transfer if any and set new one */
208 bytes_left = (data->blocksize * data->blocks);
209
210 /* Reset FIFO - Always use 32 byte fifo threshold */
211 set_val(®s->mmcfifoctl,
212 (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
213
214 if (host->version == MMC_CTLR_VERSION_2)
215 cmddata |= MMCCMD_DMATRIG;
216
217 cmddata |= MMCCMD_WDATX;
218 if (data->flags == MMC_DATA_READ) {
219 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
220 } else if (data->flags == MMC_DATA_WRITE) {
221 set_val(®s->mmcfifoctl,
222 (MMCFIFOCTL_FIFOLEV |
223 MMCFIFOCTL_FIFODIR));
224 cmddata |= MMCCMD_DTRW;
225 }
226
227 set_val(®s->mmctod, 0xFFFF);
228 set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
229 set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
230
231 if (data->flags == MMC_DATA_WRITE) {
232 uint val;
233 data_buf = (char *)data->src;
234 /* For write, fill FIFO with data before issue of CMD */
235 for (i = 0; (i < fifo_words) && bytes_left; i++) {
236 memcpy((char *)&val, data_buf, 4);
237 set_val(®s->mmcdxr, val);
238 data_buf += 4;
239 bytes_left -= 4;
240 }
241 }
242 } else {
243 set_val(®s->mmcblen, 0);
244 set_val(®s->mmcnblk, 0);
245 }
246
247 set_val(®s->mmctor, 0x1FFF);
248
249 /* Send the command */
250 set_val(®s->mmcarghl, cmd->cmdarg);
251 set_val(®s->mmccmd, cmddata);
252
253 status_rdy = MMCST0_RSPDNE;
254 status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
255 MMCST0_CRCWR | MMCST0_CRCRD);
256 if (cmd->resp_type & MMC_RSP_CRC)
257 status_err |= MMCST0_CRCRS;
258
259 mmcstatus = get_val(®s->mmcst0);
260 err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
261 if (err)
262 return err;
263
264 /* For R1b wait for busy done */
265 if (cmd->resp_type == MMC_RSP_R1b)
266 dmmc_busy_wait(regs);
267
268 /* Collect response from controller for specific commands */
269 if (mmcstatus & MMCST0_RSPDNE) {
270 /* Copy the response to the response buffer */
271 if (cmd->resp_type & MMC_RSP_136) {
272 cmd->response[0] = get_val(®s->mmcrsp67);
273 cmd->response[1] = get_val(®s->mmcrsp45);
274 cmd->response[2] = get_val(®s->mmcrsp23);
275 cmd->response[3] = get_val(®s->mmcrsp01);
276 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
277 cmd->response[0] = get_val(®s->mmcrsp67);
278 }
279 }
280
281 if (data == NULL)
282 return 0;
283
284 if (data->flags == MMC_DATA_READ) {
285 /* check for DATDNE along with DRRDY as the controller might
286 * set the DATDNE without DRRDY for smaller transfers with
287 * less than FIFO threshold bytes
288 */
289 status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
290 status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
291 data_buf = data->dest;
292 } else {
293 status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
294 status_err = MMCST0_CRCWR;
295 }
296
297 /* Wait until all of the blocks are transferred */
298 while (bytes_left) {
299 err = dmmc_check_status(regs, &mmcstatus, status_rdy,
300 status_err);
301 if (err)
302 return err;
303
304 if (data->flags == MMC_DATA_READ) {
305 /*
306 * MMC controller sets the Data receive ready bit
307 * (DRRDY) in MMCST0 even before the entire FIFO is
308 * full. This results in erratic behavior if we start
309 * reading the FIFO soon after DRRDY. Wait for the
310 * FIFO full bit in MMCST1 for proper FIFO clearing.
311 */
312 if (bytes_left > fifo_bytes)
313 dmmc_wait_fifo_status(regs, 0x4a);
314 else if (bytes_left == fifo_bytes) {
315 dmmc_wait_fifo_status(regs, 0x40);
316 if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
317 udelay(600);
318 }
319
320 for (i = 0; bytes_left && (i < fifo_words); i++) {
321 cmddata = get_val(®s->mmcdrr);
322 memcpy(data_buf, (char *)&cmddata, 4);
323 data_buf += 4;
324 bytes_left -= 4;
325 }
326 } else {
327 /*
328 * MMC controller sets the Data transmit ready bit
329 * (DXRDY) in MMCST0 even before the entire FIFO is
330 * empty. This results in erratic behavior if we start
331 * writing the FIFO soon after DXRDY. Wait for the
332 * FIFO empty bit in MMCST1 for proper FIFO clearing.
333 */
334 dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
335 for (i = 0; bytes_left && (i < fifo_words); i++) {
336 memcpy((char *)&cmddata, data_buf, 4);
337 set_val(®s->mmcdxr, cmddata);
338 data_buf += 4;
339 bytes_left -= 4;
340 }
341 dmmc_busy_wait(regs);
342 }
343 }
344
345 err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
346 if (err)
347 return err;
348
349 return 0;
350 }
351
352 /* Initialize Davinci MMC controller */
353 #if !CONFIG_IS_ENABLED(DM_MMC)
354 static int dmmc_init(struct mmc *mmc)
355 {
356 struct davinci_mmc *host = mmc->priv;
357 #else
358 static int davinci_dm_mmc_init(struct udevice *dev)
359 {
360 struct davinci_mmc_priv *host = dev_get_priv(dev);
361 #endif
362 struct davinci_mmc_regs *regs = host->reg_base;
363
364 /* Clear status registers explicitly - soft reset doesn't clear it
365 * If Uboot is invoked from UBL with SDMMC Support, the status
366 * registers can have uncleared bits
367 */
368 get_val(®s->mmcst0);
369 get_val(®s->mmcst1);
370
371 /* Hold software reset */
372 set_bit(®s->mmcctl, MMCCTL_DATRST);
373 set_bit(®s->mmcctl, MMCCTL_CMDRST);
374 udelay(10);
375
376 set_val(®s->mmcclk, 0x0);
377 set_val(®s->mmctor, 0x1FFF);
378 set_val(®s->mmctod, 0xFFFF);
379
380 /* Clear software reset */
381 clear_bit(®s->mmcctl, MMCCTL_DATRST);
382 clear_bit(®s->mmcctl, MMCCTL_CMDRST);
383
384 udelay(10);
385
386 /* Reset FIFO - Always use the maximum fifo threshold */
387 set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
388 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
389
390 return 0;
391 }
392
393 /* Set buswidth or clock as indicated by the MMC framework */
394 #if !CONFIG_IS_ENABLED(DM_MMC)
395 static int dmmc_set_ios(struct mmc *mmc)
396 {
397 struct davinci_mmc *host = mmc->priv;
398 struct davinci_mmc_regs *regs = host->reg_base;
399 #else
400 static int davinci_mmc_set_ios(struct udevice *dev)
401 {
402 struct mmc *mmc = mmc_get_mmc_dev(dev);
403
404 struct davinci_mmc_priv *host = dev_get_priv(dev);
405 struct davinci_mmc_regs *regs = host->reg_base;
406 #endif
407 /* Set the bus width */
408 if (mmc->bus_width == 4)
409 set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
410 else
411 clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
412
413 /* Set clock speed */
414 if (mmc->clock) {
415 #if !CONFIG_IS_ENABLED(DM_MMC)
416 dmmc_set_clock(mmc, mmc->clock);
417 #else
418 davinci_mmc_set_clock(dev, mmc->clock);
419 #endif
420 }
421 return 0;
422 }
423
424 #if !CONFIG_IS_ENABLED(DM_MMC)
425 static const struct mmc_ops dmmc_ops = {
426 .send_cmd = dmmc_send_cmd,
427 .set_ios = dmmc_set_ios,
428 .init = dmmc_init,
429 };
430 #else
431
432 static int davinci_mmc_getcd(struct udevice *dev)
433 {
434 int value = -1;
435 #if CONFIG_IS_ENABLED(DM_GPIO)
436 struct davinci_mmc_priv *priv = dev_get_priv(dev);
437 value = dm_gpio_get_value(&priv->cd_gpio);
438 #endif
439 /* if no CD return as 1 */
440 if (value < 0)
441 return 1;
442
443 return value;
444 }
445
446 static int davinci_mmc_getwp(struct udevice *dev)
447 {
448 int value = -1;
449 #if CONFIG_IS_ENABLED(DM_GPIO)
450 struct davinci_mmc_priv *priv = dev_get_priv(dev);
451
452 value = dm_gpio_get_value(&priv->wp_gpio);
453 #endif
454 /* if no WP return as 0 */
455 if (value < 0)
456 return 0;
457
458 return value;
459 }
460
461 static const struct dm_mmc_ops davinci_mmc_ops = {
462 .send_cmd = davinci_mmc_send_cmd,
463 .set_ios = davinci_mmc_set_ios,
464 .get_cd = davinci_mmc_getcd,
465 .get_wp = davinci_mmc_getwp,
466 };
467 #endif
468
469 #if !CONFIG_IS_ENABLED(DM_MMC)
470 /* Called from board_mmc_init during startup. Can be called multiple times
471 * depending on the number of slots available on board and controller
472 */
473 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
474 {
475 host->cfg.name = "davinci";
476 host->cfg.ops = &dmmc_ops;
477 host->cfg.f_min = 200000;
478 host->cfg.f_max = 25000000;
479 host->cfg.voltages = host->voltages;
480 host->cfg.host_caps = host->host_caps;
481
482 host->cfg.b_max = DAVINCI_MAX_BLOCKS;
483
484 mmc_create(&host->cfg, host);
485
486 return 0;
487 }
488 #else
489
490
491 static int davinci_mmc_probe(struct udevice *dev)
492 {
493 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
494 struct davinci_mmc_plat *plat = dev_get_platdata(dev);
495 struct davinci_mmc_priv *priv = dev_get_priv(dev);
496 struct mmc_config *cfg = &plat->cfg;
497 struct davinci_of_data *data =
498 (struct davinci_of_data *)dev_get_driver_data(dev);
499 cfg->f_min = 200000;
500 cfg->f_max = 25000000;
501 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
502 cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
503 cfg->b_max = DAVINCI_MAX_BLOCKS;
504
505 if (data) {
506 cfg->name = data->name;
507 priv->version = data->version;
508 }
509
510 priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
511 priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
512
513 #if CONFIG_IS_ENABLED(DM_GPIO)
514 /* These GPIOs are optional */
515 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
516 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
517 #endif
518
519 upriv->mmc = &plat->mmc;
520
521 return davinci_dm_mmc_init(dev);
522 }
523
524 static int davinci_mmc_bind(struct udevice *dev)
525 {
526 struct davinci_mmc_plat *plat = dev_get_platdata(dev);
527
528 return mmc_bind(dev, &plat->mmc, &plat->cfg);
529 }
530
531
532 const struct davinci_of_data davinci_mmc_host_info[] = {
533 {
534 .name = "dm6441-mmc",
535 .version = MMC_CTLR_VERSION_1,
536 },
537 {
538 .name = "da830-mmc",
539 .version = MMC_CTLR_VERSION_2,
540 },
541 {},
542 };
543
544 static const struct udevice_id davinci_mmc_ids[] = {
545 {
546 .compatible = "ti,dm6441-mmc",
547 .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_1]
548 },
549 {
550 .compatible = "ti,da830-mmc",
551 .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_2]
552 },
553 {},
554 };
555
556 U_BOOT_DRIVER(davinci_mmc_drv) = {
557 .name = "davinci_mmc",
558 .id = UCLASS_MMC,
559 .of_match = davinci_mmc_ids,
560 #if CONFIG_BLK
561 .bind = davinci_mmc_bind,
562 #endif
563 .probe = davinci_mmc_probe,
564 .ops = &davinci_mmc_ops,
565 .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
566 .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
567 };
568 #endif
569