1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * bcm2835 sdhost driver. 4 * 5 * The 2835 has two SD controllers: The Arasan sdhci controller 6 * (supported by the iproc driver) and a custom sdhost controller 7 * (supported by this driver). 8 * 9 * The sdhci controller supports both sdcard and sdio. The sdhost 10 * controller supports the sdcard only, but has better performance. 11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with 12 * the sdhost controller allows to use the sdhci controller for wifi 13 * support. 14 * 15 * The configuration is done by devicetree via pin muxing. Both 16 * SD controller are available on the same pins (2 pin groups = pin 22 17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers 18 * at the same time with different pin groups. 19 * 20 * This code was ported to U-Boot by 21 * Alexander Graf <agraf@suse.de> 22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by 23 * Phil Elwell <phil@raspberrypi.org> 24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 25 * which is based on 26 * mmc-bcm2835.c by Gellert Weisz 27 * which is, in turn, based on 28 * sdhci-bcm2708.c by Broadcom 29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 30 * sdhci.c and sdhci-pci.c by Pierre Ossman 31 */ 32 #include <clk.h> 33 #include <common.h> 34 #include <dm.h> 35 #include <mmc.h> 36 #include <asm/arch/msg.h> 37 #include <asm/arch/mbox.h> 38 #include <asm/unaligned.h> 39 #include <linux/compat.h> 40 #include <linux/io.h> 41 #include <linux/iopoll.h> 42 #include <linux/sizes.h> 43 #include <mach/gpio.h> 44 #include <power/regulator.h> 45 46 #define msleep(a) udelay(a * 1000) 47 48 #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 49 #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 50 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 51 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 52 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 53 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 54 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 55 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 56 #define SDHSTS 0x20 /* SD host status - 11 R/W */ 57 #define SDVDD 0x30 /* SD card power control - 1 R/W */ 58 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 59 #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 60 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 61 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 62 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 63 64 #define SDCMD_NEW_FLAG 0x8000 65 #define SDCMD_FAIL_FLAG 0x4000 66 #define SDCMD_BUSYWAIT 0x800 67 #define SDCMD_NO_RESPONSE 0x400 68 #define SDCMD_LONG_RESPONSE 0x200 69 #define SDCMD_WRITE_CMD 0x80 70 #define SDCMD_READ_CMD 0x40 71 #define SDCMD_CMD_MASK 0x3f 72 73 #define SDCDIV_MAX_CDIV 0x7ff 74 75 #define SDHSTS_BUSY_IRPT 0x400 76 #define SDHSTS_BLOCK_IRPT 0x200 77 #define SDHSTS_SDIO_IRPT 0x100 78 #define SDHSTS_REW_TIME_OUT 0x80 79 #define SDHSTS_CMD_TIME_OUT 0x40 80 #define SDHSTS_CRC16_ERROR 0x20 81 #define SDHSTS_CRC7_ERROR 0x10 82 #define SDHSTS_FIFO_ERROR 0x08 83 #define SDHSTS_DATA_FLAG 0x01 84 85 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \ 86 SDHSTS_BLOCK_IRPT | \ 87 SDHSTS_SDIO_IRPT | \ 88 SDHSTS_REW_TIME_OUT | \ 89 SDHSTS_CMD_TIME_OUT | \ 90 SDHSTS_CRC16_ERROR | \ 91 SDHSTS_CRC7_ERROR | \ 92 SDHSTS_FIFO_ERROR) 93 94 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 95 SDHSTS_CRC16_ERROR | \ 96 SDHSTS_REW_TIME_OUT | \ 97 SDHSTS_FIFO_ERROR) 98 99 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 100 SDHSTS_TRANSFER_ERROR_MASK) 101 102 #define SDHCFG_BUSY_IRPT_EN BIT(10) 103 #define SDHCFG_BLOCK_IRPT_EN BIT(8) 104 #define SDHCFG_SDIO_IRPT_EN BIT(5) 105 #define SDHCFG_DATA_IRPT_EN BIT(4) 106 #define SDHCFG_SLOW_CARD BIT(3) 107 #define SDHCFG_WIDE_EXT_BUS BIT(2) 108 #define SDHCFG_WIDE_INT_BUS BIT(1) 109 #define SDHCFG_REL_CMD_LINE BIT(0) 110 111 #define SDVDD_POWER_OFF 0 112 #define SDVDD_POWER_ON 1 113 114 #define SDEDM_FORCE_DATA_MODE BIT(19) 115 #define SDEDM_CLOCK_PULSE BIT(20) 116 #define SDEDM_BYPASS BIT(21) 117 118 #define SDEDM_FIFO_FILL_SHIFT 4 119 #define SDEDM_FIFO_FILL_MASK 0x1f 120 static u32 edm_fifo_fill(u32 edm) 121 { 122 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK; 123 } 124 125 #define SDEDM_WRITE_THRESHOLD_SHIFT 9 126 #define SDEDM_READ_THRESHOLD_SHIFT 14 127 #define SDEDM_THRESHOLD_MASK 0x1f 128 129 #define SDEDM_FSM_MASK 0xf 130 #define SDEDM_FSM_IDENTMODE 0x0 131 #define SDEDM_FSM_DATAMODE 0x1 132 #define SDEDM_FSM_READDATA 0x2 133 #define SDEDM_FSM_WRITEDATA 0x3 134 #define SDEDM_FSM_READWAIT 0x4 135 #define SDEDM_FSM_READCRC 0x5 136 #define SDEDM_FSM_WRITECRC 0x6 137 #define SDEDM_FSM_WRITEWAIT1 0x7 138 #define SDEDM_FSM_POWERDOWN 0x8 139 #define SDEDM_FSM_POWERUP 0x9 140 #define SDEDM_FSM_WRITESTART1 0xa 141 #define SDEDM_FSM_WRITESTART2 0xb 142 #define SDEDM_FSM_GENPULSES 0xc 143 #define SDEDM_FSM_WRITEWAIT2 0xd 144 #define SDEDM_FSM_STARTPOWDOWN 0xf 145 146 #define SDDATA_FIFO_WORDS 16 147 148 #define FIFO_READ_THRESHOLD 4 149 #define FIFO_WRITE_THRESHOLD 4 150 #define SDDATA_FIFO_PIO_BURST 8 151 152 #define SDHST_TIMEOUT_MAX_USEC 100000 153 154 struct bcm2835_plat { 155 struct mmc_config cfg; 156 struct mmc mmc; 157 }; 158 159 struct bcm2835_host { 160 void __iomem *ioaddr; 161 u32 phys_addr; 162 163 int clock; /* Current clock speed */ 164 unsigned int max_clk; /* Max possible freq */ 165 unsigned int blocks; /* remaining PIO blocks */ 166 int irq; /* Device IRQ */ 167 168 u32 ns_per_fifo_word; 169 170 /* cached registers */ 171 u32 hcfg; 172 u32 cdiv; 173 174 struct mmc_cmd *cmd; /* Current command */ 175 struct mmc_data *data; /* Current data request */ 176 bool data_complete:1;/* Data finished before cmd */ 177 bool use_busy:1; /* Wait for busy interrupt */ 178 bool wait_data_complete:1; /* Wait for data */ 179 180 /* for threaded irq handler */ 181 bool irq_block; 182 bool irq_busy; 183 bool irq_data; 184 185 struct udevice *dev; 186 struct mmc *mmc; 187 struct bcm2835_plat *plat; 188 }; 189 190 static void bcm2835_dumpregs(struct bcm2835_host *host) 191 { 192 dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 193 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 194 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 195 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 196 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 197 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 198 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 199 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 200 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 201 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 202 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 203 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 204 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 205 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 206 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 207 dev_dbg(dev, "===========================================\n"); 208 } 209 210 static void bcm2835_reset_internal(struct bcm2835_host *host) 211 { 212 u32 temp; 213 214 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 215 writel(0, host->ioaddr + SDCMD); 216 writel(0, host->ioaddr + SDARG); 217 /* Set timeout to a big enough value so we don't hit it */ 218 writel(0xf00000, host->ioaddr + SDTOUT); 219 writel(0, host->ioaddr + SDCDIV); 220 /* Clear status register */ 221 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS); 222 writel(0, host->ioaddr + SDHCFG); 223 writel(0, host->ioaddr + SDHBCT); 224 writel(0, host->ioaddr + SDHBLC); 225 226 /* Limit fifo usage due to silicon bug */ 227 temp = readl(host->ioaddr + SDEDM); 228 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 229 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 230 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 231 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 232 writel(temp, host->ioaddr + SDEDM); 233 /* Wait for FIFO threshold to populate */ 234 msleep(20); 235 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 236 /* Wait for all components to go through power on cycle */ 237 msleep(20); 238 host->clock = 0; 239 writel(host->hcfg, host->ioaddr + SDHCFG); 240 writel(host->cdiv, host->ioaddr + SDCDIV); 241 } 242 243 static int bcm2835_finish_command(struct bcm2835_host *host); 244 245 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 246 { 247 int timediff; 248 u32 alternate_idle; 249 250 alternate_idle = (host->data->flags & MMC_DATA_READ) ? 251 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 252 253 timediff = 0; 254 255 while (1) { 256 u32 edm, fsm; 257 258 edm = readl(host->ioaddr + SDEDM); 259 fsm = edm & SDEDM_FSM_MASK; 260 261 if ((fsm == SDEDM_FSM_IDENTMODE) || 262 (fsm == SDEDM_FSM_DATAMODE)) 263 break; 264 if (fsm == alternate_idle) { 265 writel(edm | SDEDM_FORCE_DATA_MODE, 266 host->ioaddr + SDEDM); 267 break; 268 } 269 270 /* Error out after 100000 register reads (~1s) */ 271 if (timediff++ == 100000) { 272 dev_err(host->dev, 273 "wait_transfer_complete - still waiting after %d retries\n", 274 timediff); 275 bcm2835_dumpregs(host); 276 return; 277 } 278 } 279 } 280 281 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 282 { 283 struct mmc_data *data = host->data; 284 size_t blksize = data->blocksize; 285 int copy_words; 286 u32 hsts = 0; 287 u32 *buf; 288 289 if (blksize % sizeof(u32)) 290 return -EINVAL; 291 292 buf = is_read ? (u32 *)data->dest : (u32 *)data->src; 293 294 if (is_read) 295 data->dest += blksize; 296 else 297 data->src += blksize; 298 299 copy_words = blksize / sizeof(u32); 300 301 /* 302 * Copy all contents from/to the FIFO as far as it reaches, 303 * then wait for it to fill/empty again and rewind. 304 */ 305 while (copy_words) { 306 int burst_words, words; 307 u32 edm; 308 309 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 310 edm = readl(host->ioaddr + SDEDM); 311 if (is_read) 312 words = edm_fifo_fill(edm); 313 else 314 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm); 315 316 if (words < burst_words) { 317 int fsm_state = (edm & SDEDM_FSM_MASK); 318 319 if ((is_read && 320 (fsm_state != SDEDM_FSM_READDATA && 321 fsm_state != SDEDM_FSM_READWAIT && 322 fsm_state != SDEDM_FSM_READCRC)) || 323 (!is_read && 324 (fsm_state != SDEDM_FSM_WRITEDATA && 325 fsm_state != SDEDM_FSM_WRITESTART1 && 326 fsm_state != SDEDM_FSM_WRITESTART2))) { 327 hsts = readl(host->ioaddr + SDHSTS); 328 printf("fsm %x, hsts %08x\n", fsm_state, hsts); 329 if (hsts & SDHSTS_ERROR_MASK) 330 break; 331 } 332 333 continue; 334 } else if (words > copy_words) { 335 words = copy_words; 336 } 337 338 copy_words -= words; 339 340 /* Copy current chunk to/from the FIFO */ 341 while (words) { 342 if (is_read) 343 *(buf++) = readl(host->ioaddr + SDDATA); 344 else 345 writel(*(buf++), host->ioaddr + SDDATA); 346 words--; 347 } 348 } 349 350 return 0; 351 } 352 353 static int bcm2835_transfer_pio(struct bcm2835_host *host) 354 { 355 u32 sdhsts; 356 bool is_read; 357 int ret = 0; 358 359 is_read = (host->data->flags & MMC_DATA_READ) != 0; 360 ret = bcm2835_transfer_block_pio(host, is_read); 361 362 if (host->wait_data_complete) 363 bcm2835_wait_transfer_complete(host); 364 365 sdhsts = readl(host->ioaddr + SDHSTS); 366 if (sdhsts & (SDHSTS_CRC16_ERROR | 367 SDHSTS_CRC7_ERROR | 368 SDHSTS_FIFO_ERROR)) { 369 printf("%s transfer error - HSTS %08x\n", 370 is_read ? "read" : "write", sdhsts); 371 ret = -EILSEQ; 372 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 373 SDHSTS_REW_TIME_OUT))) { 374 printf("%s timeout error - HSTS %08x\n", 375 is_read ? "read" : "write", sdhsts); 376 ret = -ETIMEDOUT; 377 } 378 379 return ret; 380 } 381 382 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 383 { 384 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 385 SDHCFG_BUSY_IRPT_EN; 386 387 host->hcfg = (host->hcfg & ~all_irqs) | 388 SDHCFG_DATA_IRPT_EN | 389 SDHCFG_BUSY_IRPT_EN; 390 391 writel(host->hcfg, host->ioaddr + SDHCFG); 392 } 393 394 static 395 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd, 396 struct mmc_data *data) 397 { 398 WARN_ON(host->data); 399 400 host->data = data; 401 if (!data) 402 return; 403 404 host->wait_data_complete = cmd->cmdidx != MMC_CMD_READ_MULTIPLE_BLOCK; 405 host->data_complete = false; 406 407 /* Use PIO */ 408 host->blocks = data->blocks; 409 410 bcm2835_set_transfer_irqs(host); 411 412 writel(data->blocksize, host->ioaddr + SDHBCT); 413 writel(data->blocks, host->ioaddr + SDHBLC); 414 } 415 416 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host) 417 { 418 u32 value; 419 int ret; 420 int timeout_us = SDHST_TIMEOUT_MAX_USEC; 421 422 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 423 !(value & SDCMD_NEW_FLAG), timeout_us); 424 if (ret == -ETIMEDOUT) 425 printf("%s: timeout (%d us)\n", __func__, timeout_us); 426 427 return value; 428 } 429 430 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd, 431 struct mmc_data *data) 432 { 433 u32 sdcmd, sdhsts; 434 435 WARN_ON(host->cmd); 436 437 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) { 438 printf("unsupported response type!\n"); 439 return -EINVAL; 440 } 441 442 sdcmd = bcm2835_read_wait_sdcmd(host); 443 if (sdcmd & SDCMD_NEW_FLAG) { 444 printf("previous command never completed.\n"); 445 bcm2835_dumpregs(host); 446 return -EBUSY; 447 } 448 449 host->cmd = cmd; 450 451 /* Clear any error flags */ 452 sdhsts = readl(host->ioaddr + SDHSTS); 453 if (sdhsts & SDHSTS_ERROR_MASK) 454 writel(sdhsts, host->ioaddr + SDHSTS); 455 456 bcm2835_prepare_data(host, cmd, data); 457 458 writel(cmd->cmdarg, host->ioaddr + SDARG); 459 460 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK; 461 462 host->use_busy = false; 463 if (!(cmd->resp_type & MMC_RSP_PRESENT)) { 464 sdcmd |= SDCMD_NO_RESPONSE; 465 } else { 466 if (cmd->resp_type & MMC_RSP_136) 467 sdcmd |= SDCMD_LONG_RESPONSE; 468 if (cmd->resp_type & MMC_RSP_BUSY) { 469 sdcmd |= SDCMD_BUSYWAIT; 470 host->use_busy = true; 471 } 472 } 473 474 if (data) { 475 if (data->flags & MMC_DATA_WRITE) 476 sdcmd |= SDCMD_WRITE_CMD; 477 if (data->flags & MMC_DATA_READ) 478 sdcmd |= SDCMD_READ_CMD; 479 } 480 481 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 482 483 return 0; 484 } 485 486 static int bcm2835_transfer_complete(struct bcm2835_host *host) 487 { 488 int ret = 0; 489 490 WARN_ON(!host->data_complete); 491 492 host->data = NULL; 493 494 return ret; 495 } 496 497 static void bcm2835_finish_data(struct bcm2835_host *host) 498 { 499 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 500 writel(host->hcfg, host->ioaddr + SDHCFG); 501 502 host->data_complete = true; 503 504 if (host->cmd) { 505 /* Data managed to finish before the 506 * command completed. Make sure we do 507 * things in the proper order. 508 */ 509 dev_dbg(dev, "Finished early - HSTS %08x\n", 510 readl(host->ioaddr + SDHSTS)); 511 } else { 512 bcm2835_transfer_complete(host); 513 } 514 } 515 516 static int bcm2835_finish_command(struct bcm2835_host *host) 517 { 518 struct mmc_cmd *cmd = host->cmd; 519 u32 sdcmd; 520 int ret = 0; 521 522 sdcmd = bcm2835_read_wait_sdcmd(host); 523 524 /* Check for errors */ 525 if (sdcmd & SDCMD_NEW_FLAG) { 526 printf("command never completed.\n"); 527 bcm2835_dumpregs(host); 528 return -EIO; 529 } else if (sdcmd & SDCMD_FAIL_FLAG) { 530 u32 sdhsts = readl(host->ioaddr + SDHSTS); 531 532 /* Clear the errors */ 533 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 534 535 if (!(sdhsts & SDHSTS_CRC7_ERROR) || 536 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) { 537 if (sdhsts & SDHSTS_CMD_TIME_OUT) { 538 ret = -ETIMEDOUT; 539 } else { 540 printf("unexpected command %d error\n", 541 host->cmd->cmdidx); 542 bcm2835_dumpregs(host); 543 ret = -EILSEQ; 544 } 545 546 return ret; 547 } 548 } 549 550 if (cmd->resp_type & MMC_RSP_PRESENT) { 551 if (cmd->resp_type & MMC_RSP_136) { 552 int i; 553 554 for (i = 0; i < 4; i++) { 555 cmd->response[3 - i] = 556 readl(host->ioaddr + SDRSP0 + i * 4); 557 } 558 } else { 559 cmd->response[0] = readl(host->ioaddr + SDRSP0); 560 } 561 } 562 563 /* Processed actual command. */ 564 host->cmd = NULL; 565 if (host->data && host->data_complete) 566 ret = bcm2835_transfer_complete(host); 567 568 return ret; 569 } 570 571 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 572 { 573 int ret = -EINVAL; 574 575 if (!(intmask & SDHSTS_ERROR_MASK)) 576 return 0; 577 578 if (!host->cmd) 579 return -EINVAL; 580 581 printf("sdhost_busy_irq: intmask %08x\n", intmask); 582 if (intmask & SDHSTS_CRC7_ERROR) { 583 ret = -EILSEQ; 584 } else if (intmask & (SDHSTS_CRC16_ERROR | 585 SDHSTS_FIFO_ERROR)) { 586 ret = -EILSEQ; 587 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) { 588 ret = -ETIMEDOUT; 589 } 590 bcm2835_dumpregs(host); 591 return ret; 592 } 593 594 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 595 { 596 int ret = 0; 597 598 if (!host->data) 599 return 0; 600 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 601 ret = -EILSEQ; 602 if (intmask & SDHSTS_REW_TIME_OUT) 603 ret = -ETIMEDOUT; 604 605 if (ret) 606 printf("%s:%d %d\n", __func__, __LINE__, ret); 607 608 return ret; 609 } 610 611 static void bcm2835_busy_irq(struct bcm2835_host *host) 612 { 613 if (WARN_ON(!host->cmd)) { 614 bcm2835_dumpregs(host); 615 return; 616 } 617 618 if (WARN_ON(!host->use_busy)) { 619 bcm2835_dumpregs(host); 620 return; 621 } 622 host->use_busy = false; 623 624 bcm2835_finish_command(host); 625 } 626 627 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 628 { 629 int ret; 630 631 /* 632 * There are no dedicated data/space available interrupt 633 * status bits, so it is necessary to use the single shared 634 * data/space available FIFO status bits. It is therefore not 635 * an error to get here when there is no data transfer in 636 * progress. 637 */ 638 if (!host->data) 639 return; 640 641 ret = bcm2835_check_data_error(host, intmask); 642 if (ret) 643 goto finished; 644 645 if (host->data->flags & MMC_DATA_WRITE) { 646 /* Use the block interrupt for writes after the first block */ 647 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 648 host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 649 writel(host->hcfg, host->ioaddr + SDHCFG); 650 bcm2835_transfer_pio(host); 651 } else { 652 bcm2835_transfer_pio(host); 653 host->blocks--; 654 if ((host->blocks == 0)) 655 goto finished; 656 } 657 return; 658 659 finished: 660 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 661 writel(host->hcfg, host->ioaddr + SDHCFG); 662 } 663 664 static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 665 { 666 if (!host->data) 667 return; 668 if ((host->blocks == 0)) 669 bcm2835_finish_data(host); 670 } 671 672 static void bcm2835_block_irq(struct bcm2835_host *host) 673 { 674 if (WARN_ON(!host->data)) { 675 bcm2835_dumpregs(host); 676 return; 677 } 678 679 WARN_ON(!host->blocks); 680 if ((--host->blocks == 0)) 681 bcm2835_finish_data(host); 682 else 683 bcm2835_transfer_pio(host); 684 } 685 686 static irqreturn_t bcm2835_irq(int irq, void *dev_id) 687 { 688 irqreturn_t result = IRQ_NONE; 689 struct bcm2835_host *host = dev_id; 690 u32 intmask; 691 692 intmask = readl(host->ioaddr + SDHSTS); 693 694 writel(SDHSTS_BUSY_IRPT | 695 SDHSTS_BLOCK_IRPT | 696 SDHSTS_SDIO_IRPT | 697 SDHSTS_DATA_FLAG, 698 host->ioaddr + SDHSTS); 699 700 if (intmask & SDHSTS_BLOCK_IRPT) { 701 bcm2835_check_data_error(host, intmask); 702 host->irq_block = true; 703 result = IRQ_WAKE_THREAD; 704 } 705 706 if (intmask & SDHSTS_BUSY_IRPT) { 707 if (!bcm2835_check_cmd_error(host, intmask)) { 708 host->irq_busy = true; 709 result = IRQ_WAKE_THREAD; 710 } else { 711 result = IRQ_HANDLED; 712 } 713 } 714 715 /* There is no true data interrupt status bit, so it is 716 * necessary to qualify the data flag with the interrupt 717 * enable bit. 718 */ 719 if ((intmask & SDHSTS_DATA_FLAG) && 720 (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 721 bcm2835_data_irq(host, intmask); 722 host->irq_data = true; 723 result = IRQ_WAKE_THREAD; 724 } 725 726 return result; 727 } 728 729 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 730 { 731 struct bcm2835_host *host = dev_id; 732 733 if (host->irq_block) { 734 host->irq_block = false; 735 bcm2835_block_irq(host); 736 } 737 738 if (host->irq_busy) { 739 host->irq_busy = false; 740 bcm2835_busy_irq(host); 741 } 742 743 if (host->irq_data) { 744 host->irq_data = false; 745 bcm2835_data_threaded_irq(host); 746 } 747 748 return IRQ_HANDLED; 749 } 750 751 static void bcm2835_irq_poll(struct bcm2835_host *host) 752 { 753 u32 intmask; 754 755 while (1) { 756 intmask = readl(host->ioaddr + SDHSTS); 757 if (intmask & (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | 758 SDHSTS_SDIO_IRPT | SDHSTS_DATA_FLAG)) { 759 bcm2835_irq(0, host); 760 bcm2835_threaded_irq(0, host); 761 return; 762 } 763 } 764 } 765 766 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 767 { 768 int div; 769 770 /* The SDCDIV register has 11 bits, and holds (div - 2). But 771 * in data mode the max is 50MHz wihout a minimum, and only 772 * the bottom 3 bits are used. Since the switch over is 773 * automatic (unless we have marked the card as slow...), 774 * chosen values have to make sense in both modes. Ident mode 775 * must be 100-400KHz, so can range check the requested 776 * clock. CMD15 must be used to return to data mode, so this 777 * can be monitored. 778 * 779 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 780 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 781 * 782 * 623->400KHz/27.8MHz 783 * reset value (507)->491159/50MHz 784 * 785 * BUT, the 3-bit clock divisor in data mode is too small if 786 * the core clock is higher than 250MHz, so instead use the 787 * SLOW_CARD configuration bit to force the use of the ident 788 * clock divisor at all times. 789 */ 790 791 if (clock < 100000) { 792 /* Can't stop the clock, but make it as slow as possible 793 * to show willing 794 */ 795 host->cdiv = SDCDIV_MAX_CDIV; 796 writel(host->cdiv, host->ioaddr + SDCDIV); 797 return; 798 } 799 800 div = host->max_clk / clock; 801 if (div < 2) 802 div = 2; 803 if ((host->max_clk / div) > clock) 804 div++; 805 div -= 2; 806 807 if (div > SDCDIV_MAX_CDIV) 808 div = SDCDIV_MAX_CDIV; 809 810 clock = host->max_clk / (div + 2); 811 host->mmc->clock = clock; 812 813 /* Calibrate some delays */ 814 815 host->ns_per_fifo_word = (1000000000 / clock) * 816 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32); 817 818 host->cdiv = div; 819 writel(host->cdiv, host->ioaddr + SDCDIV); 820 821 /* Set the timeout to 500ms */ 822 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT); 823 } 824 825 static inline int is_power_of_2(u64 x) 826 { 827 return !(x & (x - 1)); 828 } 829 830 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 831 struct mmc_data *data) 832 { 833 struct bcm2835_host *host = dev_get_priv(dev); 834 u32 edm, fsm; 835 int ret = 0; 836 837 if (data && !is_power_of_2(data->blocksize)) { 838 printf("unsupported block size (%d bytes)\n", data->blocksize); 839 840 if (cmd) 841 return -EINVAL; 842 } 843 844 edm = readl(host->ioaddr + SDEDM); 845 fsm = edm & SDEDM_FSM_MASK; 846 847 if ((fsm != SDEDM_FSM_IDENTMODE) && 848 (fsm != SDEDM_FSM_DATAMODE) && 849 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { 850 printf("previous command (%d) not complete (EDM %08x)\n", 851 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm); 852 bcm2835_dumpregs(host); 853 854 if (cmd) 855 return -EILSEQ; 856 857 return 0; 858 } 859 860 if (cmd) { 861 ret = bcm2835_send_command(host, cmd, data); 862 if (!ret && !host->use_busy) 863 ret = bcm2835_finish_command(host); 864 } 865 866 /* Wait for completion of busy signal or data transfer */ 867 while (host->use_busy || host->data) 868 bcm2835_irq_poll(host); 869 870 return ret; 871 } 872 873 static int bcm2835_set_ios(struct udevice *dev) 874 { 875 struct bcm2835_host *host = dev_get_priv(dev); 876 struct mmc *mmc = mmc_get_mmc_dev(dev); 877 878 if (!mmc->clock || mmc->clock != host->clock) { 879 bcm2835_set_clock(host, mmc->clock); 880 host->clock = mmc->clock; 881 } 882 883 /* set bus width */ 884 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 885 if (mmc->bus_width == 4) 886 host->hcfg |= SDHCFG_WIDE_EXT_BUS; 887 888 host->hcfg |= SDHCFG_WIDE_INT_BUS; 889 890 /* Disable clever clock switching, to cope with fast core clocks */ 891 host->hcfg |= SDHCFG_SLOW_CARD; 892 893 writel(host->hcfg, host->ioaddr + SDHCFG); 894 895 return 0; 896 } 897 898 static void bcm2835_add_host(struct bcm2835_host *host) 899 { 900 struct mmc_config *cfg = &host->plat->cfg; 901 902 cfg->f_max = host->max_clk; 903 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; 904 cfg->b_max = 65535; 905 906 dev_dbg(dev, "f_max %d, f_min %d\n", 907 cfg->f_max, cfg->f_min); 908 909 /* host controller capabilities */ 910 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; 911 912 /* report supported voltage ranges */ 913 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 914 915 /* Set interrupt enables */ 916 host->hcfg = SDHCFG_BUSY_IRPT_EN; 917 918 bcm2835_reset_internal(host); 919 } 920 921 static int bcm2835_probe(struct udevice *dev) 922 { 923 struct bcm2835_plat *plat = dev_get_platdata(dev); 924 struct bcm2835_host *host = dev_get_priv(dev); 925 struct mmc *mmc = mmc_get_mmc_dev(dev); 926 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 927 928 host->dev = dev; 929 host->mmc = mmc; 930 host->plat = plat; 931 upriv->mmc = &plat->mmc; 932 plat->cfg.name = dev->name; 933 934 host->phys_addr = devfdt_get_addr(dev); 935 if (host->phys_addr == FDT_ADDR_T_NONE) 936 return -EINVAL; 937 938 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256); 939 if (!host->ioaddr) 940 return -ENOMEM; 941 942 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE); 943 944 bcm2835_add_host(host); 945 946 dev_dbg(dev, "%s -> OK\n", __func__); 947 948 return 0; 949 } 950 951 static const struct udevice_id bcm2835_match[] = { 952 { .compatible = "brcm,bcm2835-sdhost" }, 953 { } 954 }; 955 956 static const struct dm_mmc_ops bcm2835_ops = { 957 .send_cmd = bcm2835_send_cmd, 958 .set_ios = bcm2835_set_ios, 959 }; 960 961 static int bcm2835_bind(struct udevice *dev) 962 { 963 struct bcm2835_plat *plat = dev_get_platdata(dev); 964 965 return mmc_bind(dev, &plat->mmc, &plat->cfg); 966 } 967 968 U_BOOT_DRIVER(bcm2835_sdhost) = { 969 .name = "bcm2835-sdhost", 970 .id = UCLASS_MMC, 971 .of_match = bcm2835_match, 972 .bind = bcm2835_bind, 973 .probe = bcm2835_probe, 974 .priv_auto_alloc_size = sizeof(struct bcm2835_host), 975 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat), 976 .ops = &bcm2835_ops, 977 }; 978