1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * bcm2835 sdhost driver. 4 * 5 * The 2835 has two SD controllers: The Arasan sdhci controller 6 * (supported by the iproc driver) and a custom sdhost controller 7 * (supported by this driver). 8 * 9 * The sdhci controller supports both sdcard and sdio. The sdhost 10 * controller supports the sdcard only, but has better performance. 11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with 12 * the sdhost controller allows to use the sdhci controller for wifi 13 * support. 14 * 15 * The configuration is done by devicetree via pin muxing. Both 16 * SD controller are available on the same pins (2 pin groups = pin 22 17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers 18 * at the same time with different pin groups. 19 * 20 * This code was ported to U-Boot by 21 * Alexander Graf <agraf@suse.de> 22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by 23 * Phil Elwell <phil@raspberrypi.org> 24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 25 * which is based on 26 * mmc-bcm2835.c by Gellert Weisz 27 * which is, in turn, based on 28 * sdhci-bcm2708.c by Broadcom 29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 30 * sdhci.c and sdhci-pci.c by Pierre Ossman 31 */ 32 #include <clk.h> 33 #include <common.h> 34 #include <dm.h> 35 #include <mmc.h> 36 #include <asm/arch/msg.h> 37 #include <asm/arch/mbox.h> 38 #include <asm/unaligned.h> 39 #include <linux/compat.h> 40 #include <linux/io.h> 41 #include <linux/iopoll.h> 42 #include <linux/sizes.h> 43 #include <mach/gpio.h> 44 #include <power/regulator.h> 45 46 #define msleep(a) udelay(a * 1000) 47 48 #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 49 #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 50 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 51 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 52 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 53 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 54 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 55 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 56 #define SDHSTS 0x20 /* SD host status - 11 R/W */ 57 #define SDVDD 0x30 /* SD card power control - 1 R/W */ 58 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 59 #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 60 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 61 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 62 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 63 64 #define SDCMD_NEW_FLAG 0x8000 65 #define SDCMD_FAIL_FLAG 0x4000 66 #define SDCMD_BUSYWAIT 0x800 67 #define SDCMD_NO_RESPONSE 0x400 68 #define SDCMD_LONG_RESPONSE 0x200 69 #define SDCMD_WRITE_CMD 0x80 70 #define SDCMD_READ_CMD 0x40 71 #define SDCMD_CMD_MASK 0x3f 72 73 #define SDCDIV_MAX_CDIV 0x7ff 74 75 #define SDHSTS_BUSY_IRPT 0x400 76 #define SDHSTS_BLOCK_IRPT 0x200 77 #define SDHSTS_SDIO_IRPT 0x100 78 #define SDHSTS_REW_TIME_OUT 0x80 79 #define SDHSTS_CMD_TIME_OUT 0x40 80 #define SDHSTS_CRC16_ERROR 0x20 81 #define SDHSTS_CRC7_ERROR 0x10 82 #define SDHSTS_FIFO_ERROR 0x08 83 #define SDHSTS_DATA_FLAG 0x01 84 85 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \ 86 SDHSTS_BLOCK_IRPT | \ 87 SDHSTS_SDIO_IRPT | \ 88 SDHSTS_REW_TIME_OUT | \ 89 SDHSTS_CMD_TIME_OUT | \ 90 SDHSTS_CRC16_ERROR | \ 91 SDHSTS_CRC7_ERROR | \ 92 SDHSTS_FIFO_ERROR) 93 94 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 95 SDHSTS_CRC16_ERROR | \ 96 SDHSTS_REW_TIME_OUT | \ 97 SDHSTS_FIFO_ERROR) 98 99 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 100 SDHSTS_TRANSFER_ERROR_MASK) 101 102 #define SDHCFG_BUSY_IRPT_EN BIT(10) 103 #define SDHCFG_BLOCK_IRPT_EN BIT(8) 104 #define SDHCFG_SDIO_IRPT_EN BIT(5) 105 #define SDHCFG_DATA_IRPT_EN BIT(4) 106 #define SDHCFG_SLOW_CARD BIT(3) 107 #define SDHCFG_WIDE_EXT_BUS BIT(2) 108 #define SDHCFG_WIDE_INT_BUS BIT(1) 109 #define SDHCFG_REL_CMD_LINE BIT(0) 110 111 #define SDVDD_POWER_OFF 0 112 #define SDVDD_POWER_ON 1 113 114 #define SDEDM_FORCE_DATA_MODE BIT(19) 115 #define SDEDM_CLOCK_PULSE BIT(20) 116 #define SDEDM_BYPASS BIT(21) 117 118 #define SDEDM_FIFO_FILL_SHIFT 4 119 #define SDEDM_FIFO_FILL_MASK 0x1f 120 static u32 edm_fifo_fill(u32 edm) 121 { 122 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK; 123 } 124 125 #define SDEDM_WRITE_THRESHOLD_SHIFT 9 126 #define SDEDM_READ_THRESHOLD_SHIFT 14 127 #define SDEDM_THRESHOLD_MASK 0x1f 128 129 #define SDEDM_FSM_MASK 0xf 130 #define SDEDM_FSM_IDENTMODE 0x0 131 #define SDEDM_FSM_DATAMODE 0x1 132 #define SDEDM_FSM_READDATA 0x2 133 #define SDEDM_FSM_WRITEDATA 0x3 134 #define SDEDM_FSM_READWAIT 0x4 135 #define SDEDM_FSM_READCRC 0x5 136 #define SDEDM_FSM_WRITECRC 0x6 137 #define SDEDM_FSM_WRITEWAIT1 0x7 138 #define SDEDM_FSM_POWERDOWN 0x8 139 #define SDEDM_FSM_POWERUP 0x9 140 #define SDEDM_FSM_WRITESTART1 0xa 141 #define SDEDM_FSM_WRITESTART2 0xb 142 #define SDEDM_FSM_GENPULSES 0xc 143 #define SDEDM_FSM_WRITEWAIT2 0xd 144 #define SDEDM_FSM_STARTPOWDOWN 0xf 145 146 #define SDDATA_FIFO_WORDS 16 147 148 #define FIFO_READ_THRESHOLD 4 149 #define FIFO_WRITE_THRESHOLD 4 150 #define SDDATA_FIFO_PIO_BURST 8 151 152 #define SDHST_TIMEOUT_MAX_USEC 100000 153 154 struct bcm2835_plat { 155 struct mmc_config cfg; 156 struct mmc mmc; 157 }; 158 159 struct bcm2835_host { 160 void __iomem *ioaddr; 161 u32 phys_addr; 162 163 int clock; /* Current clock speed */ 164 unsigned int max_clk; /* Max possible freq */ 165 unsigned int blocks; /* remaining PIO blocks */ 166 167 u32 ns_per_fifo_word; 168 169 /* cached registers */ 170 u32 hcfg; 171 u32 cdiv; 172 173 struct mmc_cmd *cmd; /* Current command */ 174 struct mmc_data *data; /* Current data request */ 175 bool use_busy:1; /* Wait for busy interrupt */ 176 177 struct udevice *dev; 178 struct mmc *mmc; 179 struct bcm2835_plat *plat; 180 }; 181 182 static void bcm2835_dumpregs(struct bcm2835_host *host) 183 { 184 dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 185 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 186 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 187 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 188 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 189 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 190 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 191 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 192 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 193 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 194 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 195 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 196 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 197 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 198 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 199 dev_dbg(dev, "===========================================\n"); 200 } 201 202 static void bcm2835_reset_internal(struct bcm2835_host *host) 203 { 204 u32 temp; 205 206 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 207 writel(0, host->ioaddr + SDCMD); 208 writel(0, host->ioaddr + SDARG); 209 /* Set timeout to a big enough value so we don't hit it */ 210 writel(0xf00000, host->ioaddr + SDTOUT); 211 writel(0, host->ioaddr + SDCDIV); 212 /* Clear status register */ 213 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS); 214 writel(0, host->ioaddr + SDHCFG); 215 writel(0, host->ioaddr + SDHBCT); 216 writel(0, host->ioaddr + SDHBLC); 217 218 /* Limit fifo usage due to silicon bug */ 219 temp = readl(host->ioaddr + SDEDM); 220 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 221 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 222 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 223 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 224 writel(temp, host->ioaddr + SDEDM); 225 /* Wait for FIFO threshold to populate */ 226 msleep(20); 227 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 228 /* Wait for all components to go through power on cycle */ 229 msleep(20); 230 host->clock = 0; 231 writel(host->hcfg, host->ioaddr + SDHCFG); 232 writel(host->cdiv, host->ioaddr + SDCDIV); 233 } 234 235 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host) 236 { 237 int timediff = 0; 238 239 while (1) { 240 u32 edm, fsm; 241 242 edm = readl(host->ioaddr + SDEDM); 243 fsm = edm & SDEDM_FSM_MASK; 244 245 if ((fsm == SDEDM_FSM_IDENTMODE) || 246 (fsm == SDEDM_FSM_DATAMODE)) 247 break; 248 249 if ((fsm == SDEDM_FSM_READWAIT) || 250 (fsm == SDEDM_FSM_WRITESTART1) || 251 (fsm == SDEDM_FSM_READDATA)) { 252 writel(edm | SDEDM_FORCE_DATA_MODE, 253 host->ioaddr + SDEDM); 254 break; 255 } 256 257 /* Error out after 100000 register reads (~1s) */ 258 if (timediff++ == 100000) { 259 dev_err(host->dev, 260 "wait_transfer_complete - still waiting after %d retries\n", 261 timediff); 262 bcm2835_dumpregs(host); 263 return -ETIMEDOUT; 264 } 265 } 266 267 return 0; 268 } 269 270 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 271 { 272 struct mmc_data *data = host->data; 273 size_t blksize = data->blocksize; 274 int copy_words; 275 u32 hsts = 0; 276 u32 *buf; 277 278 if (blksize % sizeof(u32)) 279 return -EINVAL; 280 281 buf = is_read ? (u32 *)data->dest : (u32 *)data->src; 282 283 if (is_read) 284 data->dest += blksize; 285 else 286 data->src += blksize; 287 288 copy_words = blksize / sizeof(u32); 289 290 /* 291 * Copy all contents from/to the FIFO as far as it reaches, 292 * then wait for it to fill/empty again and rewind. 293 */ 294 while (copy_words) { 295 int burst_words, words; 296 u32 edm; 297 298 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 299 edm = readl(host->ioaddr + SDEDM); 300 if (is_read) 301 words = edm_fifo_fill(edm); 302 else 303 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm); 304 305 if (words < burst_words) { 306 int fsm_state = (edm & SDEDM_FSM_MASK); 307 308 if ((is_read && 309 (fsm_state != SDEDM_FSM_READDATA && 310 fsm_state != SDEDM_FSM_READWAIT && 311 fsm_state != SDEDM_FSM_READCRC)) || 312 (!is_read && 313 (fsm_state != SDEDM_FSM_WRITEDATA && 314 fsm_state != SDEDM_FSM_WRITEWAIT1 && 315 fsm_state != SDEDM_FSM_WRITEWAIT2 && 316 fsm_state != SDEDM_FSM_WRITECRC && 317 fsm_state != SDEDM_FSM_WRITESTART1 && 318 fsm_state != SDEDM_FSM_WRITESTART2))) { 319 hsts = readl(host->ioaddr + SDHSTS); 320 printf("fsm %x, hsts %08x\n", fsm_state, hsts); 321 if (hsts & SDHSTS_ERROR_MASK) 322 break; 323 } 324 325 continue; 326 } else if (words > copy_words) { 327 words = copy_words; 328 } 329 330 copy_words -= words; 331 332 /* Copy current chunk to/from the FIFO */ 333 while (words) { 334 if (is_read) 335 *(buf++) = readl(host->ioaddr + SDDATA); 336 else 337 writel(*(buf++), host->ioaddr + SDDATA); 338 words--; 339 } 340 } 341 342 return 0; 343 } 344 345 static int bcm2835_transfer_pio(struct bcm2835_host *host) 346 { 347 u32 sdhsts; 348 bool is_read; 349 int ret = 0; 350 351 is_read = (host->data->flags & MMC_DATA_READ) != 0; 352 ret = bcm2835_transfer_block_pio(host, is_read); 353 if (ret) 354 return ret; 355 356 sdhsts = readl(host->ioaddr + SDHSTS); 357 if (sdhsts & (SDHSTS_CRC16_ERROR | 358 SDHSTS_CRC7_ERROR | 359 SDHSTS_FIFO_ERROR)) { 360 printf("%s transfer error - HSTS %08x\n", 361 is_read ? "read" : "write", sdhsts); 362 ret = -EILSEQ; 363 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 364 SDHSTS_REW_TIME_OUT))) { 365 printf("%s timeout error - HSTS %08x\n", 366 is_read ? "read" : "write", sdhsts); 367 ret = -ETIMEDOUT; 368 } 369 370 return ret; 371 } 372 373 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd, 374 struct mmc_data *data) 375 { 376 WARN_ON(host->data); 377 378 host->data = data; 379 if (!data) 380 return; 381 382 /* Use PIO */ 383 host->blocks = data->blocks; 384 385 writel(data->blocksize, host->ioaddr + SDHBCT); 386 writel(data->blocks, host->ioaddr + SDHBLC); 387 } 388 389 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host) 390 { 391 u32 value; 392 int ret; 393 int timeout_us = SDHST_TIMEOUT_MAX_USEC; 394 395 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 396 !(value & SDCMD_NEW_FLAG), timeout_us); 397 if (ret == -ETIMEDOUT) 398 printf("%s: timeout (%d us)\n", __func__, timeout_us); 399 400 return value; 401 } 402 403 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd, 404 struct mmc_data *data) 405 { 406 u32 sdcmd, sdhsts; 407 408 WARN_ON(host->cmd); 409 410 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) { 411 printf("unsupported response type!\n"); 412 return -EINVAL; 413 } 414 415 sdcmd = bcm2835_read_wait_sdcmd(host); 416 if (sdcmd & SDCMD_NEW_FLAG) { 417 printf("previous command never completed.\n"); 418 bcm2835_dumpregs(host); 419 return -EBUSY; 420 } 421 422 host->cmd = cmd; 423 424 /* Clear any error flags */ 425 sdhsts = readl(host->ioaddr + SDHSTS); 426 if (sdhsts & SDHSTS_ERROR_MASK) 427 writel(sdhsts, host->ioaddr + SDHSTS); 428 429 bcm2835_prepare_data(host, cmd, data); 430 431 writel(cmd->cmdarg, host->ioaddr + SDARG); 432 433 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK; 434 435 host->use_busy = false; 436 if (!(cmd->resp_type & MMC_RSP_PRESENT)) { 437 sdcmd |= SDCMD_NO_RESPONSE; 438 } else { 439 if (cmd->resp_type & MMC_RSP_136) 440 sdcmd |= SDCMD_LONG_RESPONSE; 441 if (cmd->resp_type & MMC_RSP_BUSY) { 442 sdcmd |= SDCMD_BUSYWAIT; 443 host->use_busy = true; 444 } 445 } 446 447 if (data) { 448 if (data->flags & MMC_DATA_WRITE) 449 sdcmd |= SDCMD_WRITE_CMD; 450 if (data->flags & MMC_DATA_READ) 451 sdcmd |= SDCMD_READ_CMD; 452 } 453 454 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 455 456 return 0; 457 } 458 459 static int bcm2835_finish_command(struct bcm2835_host *host) 460 { 461 struct mmc_cmd *cmd = host->cmd; 462 u32 sdcmd; 463 int ret = 0; 464 465 sdcmd = bcm2835_read_wait_sdcmd(host); 466 467 /* Check for errors */ 468 if (sdcmd & SDCMD_NEW_FLAG) { 469 printf("command never completed.\n"); 470 bcm2835_dumpregs(host); 471 return -EIO; 472 } else if (sdcmd & SDCMD_FAIL_FLAG) { 473 u32 sdhsts = readl(host->ioaddr + SDHSTS); 474 475 /* Clear the errors */ 476 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 477 478 if (!(sdhsts & SDHSTS_CRC7_ERROR) || 479 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) { 480 if (sdhsts & SDHSTS_CMD_TIME_OUT) { 481 ret = -ETIMEDOUT; 482 } else { 483 printf("unexpected command %d error\n", 484 host->cmd->cmdidx); 485 bcm2835_dumpregs(host); 486 ret = -EILSEQ; 487 } 488 489 return ret; 490 } 491 } 492 493 if (cmd->resp_type & MMC_RSP_PRESENT) { 494 if (cmd->resp_type & MMC_RSP_136) { 495 int i; 496 497 for (i = 0; i < 4; i++) { 498 cmd->response[3 - i] = 499 readl(host->ioaddr + SDRSP0 + i * 4); 500 } 501 } else { 502 cmd->response[0] = readl(host->ioaddr + SDRSP0); 503 } 504 } 505 506 /* Processed actual command. */ 507 host->cmd = NULL; 508 509 return ret; 510 } 511 512 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 513 { 514 int ret = -EINVAL; 515 516 if (!(intmask & SDHSTS_ERROR_MASK)) 517 return 0; 518 519 if (!host->cmd) 520 return -EINVAL; 521 522 printf("sdhost_busy_irq: intmask %08x\n", intmask); 523 if (intmask & SDHSTS_CRC7_ERROR) { 524 ret = -EILSEQ; 525 } else if (intmask & (SDHSTS_CRC16_ERROR | 526 SDHSTS_FIFO_ERROR)) { 527 ret = -EILSEQ; 528 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) { 529 ret = -ETIMEDOUT; 530 } 531 bcm2835_dumpregs(host); 532 return ret; 533 } 534 535 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 536 { 537 int ret = 0; 538 539 if (!host->data) 540 return 0; 541 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 542 ret = -EILSEQ; 543 if (intmask & SDHSTS_REW_TIME_OUT) 544 ret = -ETIMEDOUT; 545 546 if (ret) 547 printf("%s:%d %d\n", __func__, __LINE__, ret); 548 549 return ret; 550 } 551 552 static int bcm2835_transmit(struct bcm2835_host *host) 553 { 554 u32 intmask = readl(host->ioaddr + SDHSTS); 555 int ret; 556 557 /* Check for errors */ 558 ret = bcm2835_check_data_error(host, intmask); 559 if (ret) 560 return ret; 561 562 ret = bcm2835_check_cmd_error(host, intmask); 563 if (ret) 564 return ret; 565 566 /* Handle wait for busy end */ 567 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) { 568 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS); 569 host->use_busy = false; 570 bcm2835_finish_command(host); 571 } 572 573 /* Handle PIO data transfer */ 574 if (host->data) { 575 ret = bcm2835_transfer_pio(host); 576 if (ret) 577 return ret; 578 host->blocks--; 579 if (host->blocks == 0) { 580 /* Wait for command to complete for real */ 581 ret = bcm2835_wait_transfer_complete(host); 582 if (ret) 583 return ret; 584 /* Transfer complete */ 585 host->data = NULL; 586 } 587 } 588 589 return 0; 590 } 591 592 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 593 { 594 int div; 595 596 /* The SDCDIV register has 11 bits, and holds (div - 2). But 597 * in data mode the max is 50MHz wihout a minimum, and only 598 * the bottom 3 bits are used. Since the switch over is 599 * automatic (unless we have marked the card as slow...), 600 * chosen values have to make sense in both modes. Ident mode 601 * must be 100-400KHz, so can range check the requested 602 * clock. CMD15 must be used to return to data mode, so this 603 * can be monitored. 604 * 605 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 606 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 607 * 608 * 623->400KHz/27.8MHz 609 * reset value (507)->491159/50MHz 610 * 611 * BUT, the 3-bit clock divisor in data mode is too small if 612 * the core clock is higher than 250MHz, so instead use the 613 * SLOW_CARD configuration bit to force the use of the ident 614 * clock divisor at all times. 615 */ 616 617 if (clock < 100000) { 618 /* Can't stop the clock, but make it as slow as possible 619 * to show willing 620 */ 621 host->cdiv = SDCDIV_MAX_CDIV; 622 writel(host->cdiv, host->ioaddr + SDCDIV); 623 return; 624 } 625 626 div = host->max_clk / clock; 627 if (div < 2) 628 div = 2; 629 if ((host->max_clk / div) > clock) 630 div++; 631 div -= 2; 632 633 if (div > SDCDIV_MAX_CDIV) 634 div = SDCDIV_MAX_CDIV; 635 636 clock = host->max_clk / (div + 2); 637 host->mmc->clock = clock; 638 639 /* Calibrate some delays */ 640 641 host->ns_per_fifo_word = (1000000000 / clock) * 642 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32); 643 644 host->cdiv = div; 645 writel(host->cdiv, host->ioaddr + SDCDIV); 646 647 /* Set the timeout to 500ms */ 648 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT); 649 } 650 651 static inline int is_power_of_2(u64 x) 652 { 653 return !(x & (x - 1)); 654 } 655 656 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 657 struct mmc_data *data) 658 { 659 struct bcm2835_host *host = dev_get_priv(dev); 660 u32 edm, fsm; 661 int ret = 0; 662 663 if (data && !is_power_of_2(data->blocksize)) { 664 printf("unsupported block size (%d bytes)\n", data->blocksize); 665 666 if (cmd) 667 return -EINVAL; 668 } 669 670 edm = readl(host->ioaddr + SDEDM); 671 fsm = edm & SDEDM_FSM_MASK; 672 673 if ((fsm != SDEDM_FSM_IDENTMODE) && 674 (fsm != SDEDM_FSM_DATAMODE) && 675 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { 676 printf("previous command (%d) not complete (EDM %08x)\n", 677 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm); 678 bcm2835_dumpregs(host); 679 680 if (cmd) 681 return -EILSEQ; 682 683 return 0; 684 } 685 686 if (cmd) { 687 ret = bcm2835_send_command(host, cmd, data); 688 if (!ret && !host->use_busy) 689 ret = bcm2835_finish_command(host); 690 } 691 692 /* Wait for completion of busy signal or data transfer */ 693 while (host->use_busy || host->data) { 694 ret = bcm2835_transmit(host); 695 if (ret) 696 break; 697 } 698 699 return ret; 700 } 701 702 static int bcm2835_set_ios(struct udevice *dev) 703 { 704 struct bcm2835_host *host = dev_get_priv(dev); 705 struct mmc *mmc = mmc_get_mmc_dev(dev); 706 707 if (!mmc->clock || mmc->clock != host->clock) { 708 bcm2835_set_clock(host, mmc->clock); 709 host->clock = mmc->clock; 710 } 711 712 /* set bus width */ 713 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 714 if (mmc->bus_width == 4) 715 host->hcfg |= SDHCFG_WIDE_EXT_BUS; 716 717 host->hcfg |= SDHCFG_WIDE_INT_BUS; 718 719 /* Disable clever clock switching, to cope with fast core clocks */ 720 host->hcfg |= SDHCFG_SLOW_CARD; 721 722 writel(host->hcfg, host->ioaddr + SDHCFG); 723 724 return 0; 725 } 726 727 static void bcm2835_add_host(struct bcm2835_host *host) 728 { 729 struct mmc_config *cfg = &host->plat->cfg; 730 731 cfg->f_max = host->max_clk; 732 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; 733 cfg->b_max = 65535; 734 735 dev_dbg(dev, "f_max %d, f_min %d\n", 736 cfg->f_max, cfg->f_min); 737 738 /* host controller capabilities */ 739 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; 740 741 /* report supported voltage ranges */ 742 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 743 744 /* Set interrupt enables */ 745 host->hcfg = SDHCFG_BUSY_IRPT_EN; 746 747 bcm2835_reset_internal(host); 748 } 749 750 static int bcm2835_probe(struct udevice *dev) 751 { 752 struct bcm2835_plat *plat = dev_get_platdata(dev); 753 struct bcm2835_host *host = dev_get_priv(dev); 754 struct mmc *mmc = mmc_get_mmc_dev(dev); 755 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 756 757 host->dev = dev; 758 host->mmc = mmc; 759 host->plat = plat; 760 upriv->mmc = &plat->mmc; 761 plat->cfg.name = dev->name; 762 763 host->phys_addr = devfdt_get_addr(dev); 764 if (host->phys_addr == FDT_ADDR_T_NONE) 765 return -EINVAL; 766 767 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256); 768 if (!host->ioaddr) 769 return -ENOMEM; 770 771 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE); 772 773 bcm2835_add_host(host); 774 775 dev_dbg(dev, "%s -> OK\n", __func__); 776 777 return 0; 778 } 779 780 static const struct udevice_id bcm2835_match[] = { 781 { .compatible = "brcm,bcm2835-sdhost" }, 782 { } 783 }; 784 785 static const struct dm_mmc_ops bcm2835_ops = { 786 .send_cmd = bcm2835_send_cmd, 787 .set_ios = bcm2835_set_ios, 788 }; 789 790 static int bcm2835_bind(struct udevice *dev) 791 { 792 struct bcm2835_plat *plat = dev_get_platdata(dev); 793 794 return mmc_bind(dev, &plat->mmc, &plat->cfg); 795 } 796 797 U_BOOT_DRIVER(bcm2835_sdhost) = { 798 .name = "bcm2835-sdhost", 799 .id = UCLASS_MMC, 800 .of_match = bcm2835_match, 801 .bind = bcm2835_bind, 802 .probe = bcm2835_probe, 803 .priv_auto_alloc_size = sizeof(struct bcm2835_host), 804 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat), 805 .ops = &bcm2835_ops, 806 }; 807