1 /* 2 * bcm2835 sdhost driver. 3 * 4 * The 2835 has two SD controllers: The Arasan sdhci controller 5 * (supported by the iproc driver) and a custom sdhost controller 6 * (supported by this driver). 7 * 8 * The sdhci controller supports both sdcard and sdio. The sdhost 9 * controller supports the sdcard only, but has better performance. 10 * Also note that the rpi3 has sdio wifi, so driving the sdcard with 11 * the sdhost controller allows to use the sdhci controller for wifi 12 * support. 13 * 14 * The configuration is done by devicetree via pin muxing. Both 15 * SD controller are available on the same pins (2 pin groups = pin 22 16 * to 27 + pin 48 to 53). So it's possible to use both SD controllers 17 * at the same time with different pin groups. 18 * 19 * This code was ported to U-Boot by 20 * Alexander Graf <agraf@suse.de> 21 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by 22 * Phil Elwell <phil@raspberrypi.org> 23 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 24 * which is based on 25 * mmc-bcm2835.c by Gellert Weisz 26 * which is, in turn, based on 27 * sdhci-bcm2708.c by Broadcom 28 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 29 * sdhci.c and sdhci-pci.c by Pierre Ossman 30 * 31 * SPDX-License-Identifier: GPL-2.0 32 */ 33 #include <clk.h> 34 #include <common.h> 35 #include <dm.h> 36 #include <mmc.h> 37 #include <asm/arch/msg.h> 38 #include <asm/arch/mbox.h> 39 #include <asm/unaligned.h> 40 #include <linux/compat.h> 41 #include <linux/io.h> 42 #include <linux/iopoll.h> 43 #include <linux/sizes.h> 44 #include <mach/gpio.h> 45 #include <power/regulator.h> 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 #define msleep(a) udelay(a * 1000) 50 51 #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 52 #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 53 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 54 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 55 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 56 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 57 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 58 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 59 #define SDHSTS 0x20 /* SD host status - 11 R/W */ 60 #define SDVDD 0x30 /* SD card power control - 1 R/W */ 61 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 62 #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 63 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 64 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 65 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 66 67 #define SDCMD_NEW_FLAG 0x8000 68 #define SDCMD_FAIL_FLAG 0x4000 69 #define SDCMD_BUSYWAIT 0x800 70 #define SDCMD_NO_RESPONSE 0x400 71 #define SDCMD_LONG_RESPONSE 0x200 72 #define SDCMD_WRITE_CMD 0x80 73 #define SDCMD_READ_CMD 0x40 74 #define SDCMD_CMD_MASK 0x3f 75 76 #define SDCDIV_MAX_CDIV 0x7ff 77 78 #define SDHSTS_BUSY_IRPT 0x400 79 #define SDHSTS_BLOCK_IRPT 0x200 80 #define SDHSTS_SDIO_IRPT 0x100 81 #define SDHSTS_REW_TIME_OUT 0x80 82 #define SDHSTS_CMD_TIME_OUT 0x40 83 #define SDHSTS_CRC16_ERROR 0x20 84 #define SDHSTS_CRC7_ERROR 0x10 85 #define SDHSTS_FIFO_ERROR 0x08 86 #define SDHSTS_DATA_FLAG 0x01 87 88 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \ 89 SDHSTS_BLOCK_IRPT | \ 90 SDHSTS_SDIO_IRPT | \ 91 SDHSTS_REW_TIME_OUT | \ 92 SDHSTS_CMD_TIME_OUT | \ 93 SDHSTS_CRC16_ERROR | \ 94 SDHSTS_CRC7_ERROR | \ 95 SDHSTS_FIFO_ERROR) 96 97 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 98 SDHSTS_CRC16_ERROR | \ 99 SDHSTS_REW_TIME_OUT | \ 100 SDHSTS_FIFO_ERROR) 101 102 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 103 SDHSTS_TRANSFER_ERROR_MASK) 104 105 #define SDHCFG_BUSY_IRPT_EN BIT(10) 106 #define SDHCFG_BLOCK_IRPT_EN BIT(8) 107 #define SDHCFG_SDIO_IRPT_EN BIT(5) 108 #define SDHCFG_DATA_IRPT_EN BIT(4) 109 #define SDHCFG_SLOW_CARD BIT(3) 110 #define SDHCFG_WIDE_EXT_BUS BIT(2) 111 #define SDHCFG_WIDE_INT_BUS BIT(1) 112 #define SDHCFG_REL_CMD_LINE BIT(0) 113 114 #define SDVDD_POWER_OFF 0 115 #define SDVDD_POWER_ON 1 116 117 #define SDEDM_FORCE_DATA_MODE BIT(19) 118 #define SDEDM_CLOCK_PULSE BIT(20) 119 #define SDEDM_BYPASS BIT(21) 120 121 #define SDEDM_FIFO_FILL_SHIFT 4 122 #define SDEDM_FIFO_FILL_MASK 0x1f 123 static u32 edm_fifo_fill(u32 edm) 124 { 125 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK; 126 } 127 128 #define SDEDM_WRITE_THRESHOLD_SHIFT 9 129 #define SDEDM_READ_THRESHOLD_SHIFT 14 130 #define SDEDM_THRESHOLD_MASK 0x1f 131 132 #define SDEDM_FSM_MASK 0xf 133 #define SDEDM_FSM_IDENTMODE 0x0 134 #define SDEDM_FSM_DATAMODE 0x1 135 #define SDEDM_FSM_READDATA 0x2 136 #define SDEDM_FSM_WRITEDATA 0x3 137 #define SDEDM_FSM_READWAIT 0x4 138 #define SDEDM_FSM_READCRC 0x5 139 #define SDEDM_FSM_WRITECRC 0x6 140 #define SDEDM_FSM_WRITEWAIT1 0x7 141 #define SDEDM_FSM_POWERDOWN 0x8 142 #define SDEDM_FSM_POWERUP 0x9 143 #define SDEDM_FSM_WRITESTART1 0xa 144 #define SDEDM_FSM_WRITESTART2 0xb 145 #define SDEDM_FSM_GENPULSES 0xc 146 #define SDEDM_FSM_WRITEWAIT2 0xd 147 #define SDEDM_FSM_STARTPOWDOWN 0xf 148 149 #define SDDATA_FIFO_WORDS 16 150 151 #define FIFO_READ_THRESHOLD 4 152 #define FIFO_WRITE_THRESHOLD 4 153 #define SDDATA_FIFO_PIO_BURST 8 154 155 #define SDHST_TIMEOUT_MAX_USEC 100000 156 157 struct bcm2835_plat { 158 struct mmc_config cfg; 159 struct mmc mmc; 160 }; 161 162 struct bcm2835_host { 163 void __iomem *ioaddr; 164 u32 phys_addr; 165 166 int clock; /* Current clock speed */ 167 unsigned int max_clk; /* Max possible freq */ 168 unsigned int blocks; /* remaining PIO blocks */ 169 int irq; /* Device IRQ */ 170 171 u32 ns_per_fifo_word; 172 173 /* cached registers */ 174 u32 hcfg; 175 u32 cdiv; 176 177 struct mmc_cmd *cmd; /* Current command */ 178 struct mmc_data *data; /* Current data request */ 179 bool data_complete:1;/* Data finished before cmd */ 180 bool use_busy:1; /* Wait for busy interrupt */ 181 bool wait_data_complete:1; /* Wait for data */ 182 183 /* for threaded irq handler */ 184 bool irq_block; 185 bool irq_busy; 186 bool irq_data; 187 188 struct udevice *dev; 189 struct mmc *mmc; 190 struct bcm2835_plat *plat; 191 }; 192 193 static void bcm2835_dumpregs(struct bcm2835_host *host) 194 { 195 dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 196 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 197 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 198 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 199 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 200 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 201 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 202 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 203 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 204 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 205 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 206 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 207 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 208 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 209 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 210 dev_dbg(dev, "===========================================\n"); 211 } 212 213 static void bcm2835_reset_internal(struct bcm2835_host *host) 214 { 215 u32 temp; 216 217 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 218 writel(0, host->ioaddr + SDCMD); 219 writel(0, host->ioaddr + SDARG); 220 /* Set timeout to a big enough value so we don't hit it */ 221 writel(0xf00000, host->ioaddr + SDTOUT); 222 writel(0, host->ioaddr + SDCDIV); 223 /* Clear status register */ 224 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS); 225 writel(0, host->ioaddr + SDHCFG); 226 writel(0, host->ioaddr + SDHBCT); 227 writel(0, host->ioaddr + SDHBLC); 228 229 /* Limit fifo usage due to silicon bug */ 230 temp = readl(host->ioaddr + SDEDM); 231 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 232 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 233 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 234 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 235 writel(temp, host->ioaddr + SDEDM); 236 /* Wait for FIFO threshold to populate */ 237 msleep(20); 238 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 239 /* Wait for all components to go through power on cycle */ 240 msleep(20); 241 host->clock = 0; 242 writel(host->hcfg, host->ioaddr + SDHCFG); 243 writel(host->cdiv, host->ioaddr + SDCDIV); 244 } 245 246 static int bcm2835_finish_command(struct bcm2835_host *host); 247 248 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 249 { 250 int timediff; 251 u32 alternate_idle; 252 253 alternate_idle = (host->data->flags & MMC_DATA_READ) ? 254 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 255 256 timediff = 0; 257 258 while (1) { 259 u32 edm, fsm; 260 261 edm = readl(host->ioaddr + SDEDM); 262 fsm = edm & SDEDM_FSM_MASK; 263 264 if ((fsm == SDEDM_FSM_IDENTMODE) || 265 (fsm == SDEDM_FSM_DATAMODE)) 266 break; 267 if (fsm == alternate_idle) { 268 writel(edm | SDEDM_FORCE_DATA_MODE, 269 host->ioaddr + SDEDM); 270 break; 271 } 272 273 /* Error out after 100000 register reads (~1s) */ 274 if (timediff++ == 100000) { 275 dev_err(host->dev, 276 "wait_transfer_complete - still waiting after %d retries\n", 277 timediff); 278 bcm2835_dumpregs(host); 279 return; 280 } 281 } 282 } 283 284 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 285 { 286 struct mmc_data *data = host->data; 287 size_t blksize = data->blocksize; 288 int copy_words; 289 u32 hsts = 0; 290 u32 *buf; 291 292 if (blksize % sizeof(u32)) 293 return -EINVAL; 294 295 buf = is_read ? (u32 *)data->dest : (u32 *)data->src; 296 297 if (is_read) 298 data->dest += blksize; 299 else 300 data->src += blksize; 301 302 copy_words = blksize / sizeof(u32); 303 304 /* 305 * Copy all contents from/to the FIFO as far as it reaches, 306 * then wait for it to fill/empty again and rewind. 307 */ 308 while (copy_words) { 309 int burst_words, words; 310 u32 edm; 311 312 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 313 edm = readl(host->ioaddr + SDEDM); 314 if (is_read) 315 words = edm_fifo_fill(edm); 316 else 317 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm); 318 319 if (words < burst_words) { 320 int fsm_state = (edm & SDEDM_FSM_MASK); 321 322 if ((is_read && 323 (fsm_state != SDEDM_FSM_READDATA && 324 fsm_state != SDEDM_FSM_READWAIT && 325 fsm_state != SDEDM_FSM_READCRC)) || 326 (!is_read && 327 (fsm_state != SDEDM_FSM_WRITEDATA && 328 fsm_state != SDEDM_FSM_WRITESTART1 && 329 fsm_state != SDEDM_FSM_WRITESTART2))) { 330 hsts = readl(host->ioaddr + SDHSTS); 331 printf("fsm %x, hsts %08x\n", fsm_state, hsts); 332 if (hsts & SDHSTS_ERROR_MASK) 333 break; 334 } 335 336 continue; 337 } else if (words > copy_words) { 338 words = copy_words; 339 } 340 341 copy_words -= words; 342 343 /* Copy current chunk to/from the FIFO */ 344 while (words) { 345 if (is_read) 346 *(buf++) = readl(host->ioaddr + SDDATA); 347 else 348 writel(*(buf++), host->ioaddr + SDDATA); 349 words--; 350 } 351 } 352 353 return 0; 354 } 355 356 static int bcm2835_transfer_pio(struct bcm2835_host *host) 357 { 358 u32 sdhsts; 359 bool is_read; 360 int ret = 0; 361 362 is_read = (host->data->flags & MMC_DATA_READ) != 0; 363 ret = bcm2835_transfer_block_pio(host, is_read); 364 365 if (host->wait_data_complete) 366 bcm2835_wait_transfer_complete(host); 367 368 sdhsts = readl(host->ioaddr + SDHSTS); 369 if (sdhsts & (SDHSTS_CRC16_ERROR | 370 SDHSTS_CRC7_ERROR | 371 SDHSTS_FIFO_ERROR)) { 372 printf("%s transfer error - HSTS %08x\n", 373 is_read ? "read" : "write", sdhsts); 374 ret = -EILSEQ; 375 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 376 SDHSTS_REW_TIME_OUT))) { 377 printf("%s timeout error - HSTS %08x\n", 378 is_read ? "read" : "write", sdhsts); 379 ret = -ETIMEDOUT; 380 } 381 382 return ret; 383 } 384 385 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 386 { 387 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 388 SDHCFG_BUSY_IRPT_EN; 389 390 host->hcfg = (host->hcfg & ~all_irqs) | 391 SDHCFG_DATA_IRPT_EN | 392 SDHCFG_BUSY_IRPT_EN; 393 394 writel(host->hcfg, host->ioaddr + SDHCFG); 395 } 396 397 static 398 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd, 399 struct mmc_data *data) 400 { 401 WARN_ON(host->data); 402 403 host->data = data; 404 if (!data) 405 return; 406 407 host->wait_data_complete = cmd->cmdidx != MMC_CMD_READ_MULTIPLE_BLOCK; 408 host->data_complete = false; 409 410 /* Use PIO */ 411 host->blocks = data->blocks; 412 413 bcm2835_set_transfer_irqs(host); 414 415 writel(data->blocksize, host->ioaddr + SDHBCT); 416 writel(data->blocks, host->ioaddr + SDHBLC); 417 } 418 419 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host) 420 { 421 u32 value; 422 int ret; 423 int timeout_us = SDHST_TIMEOUT_MAX_USEC; 424 425 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 426 !(value & SDCMD_NEW_FLAG), timeout_us); 427 if (ret == -ETIMEDOUT) 428 printf("%s: timeout (%d us)\n", __func__, timeout_us); 429 430 return value; 431 } 432 433 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd, 434 struct mmc_data *data) 435 { 436 u32 sdcmd, sdhsts; 437 438 WARN_ON(host->cmd); 439 440 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) { 441 printf("unsupported response type!\n"); 442 return -EINVAL; 443 } 444 445 sdcmd = bcm2835_read_wait_sdcmd(host); 446 if (sdcmd & SDCMD_NEW_FLAG) { 447 printf("previous command never completed.\n"); 448 bcm2835_dumpregs(host); 449 return -EBUSY; 450 } 451 452 host->cmd = cmd; 453 454 /* Clear any error flags */ 455 sdhsts = readl(host->ioaddr + SDHSTS); 456 if (sdhsts & SDHSTS_ERROR_MASK) 457 writel(sdhsts, host->ioaddr + SDHSTS); 458 459 bcm2835_prepare_data(host, cmd, data); 460 461 writel(cmd->cmdarg, host->ioaddr + SDARG); 462 463 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK; 464 465 host->use_busy = false; 466 if (!(cmd->resp_type & MMC_RSP_PRESENT)) { 467 sdcmd |= SDCMD_NO_RESPONSE; 468 } else { 469 if (cmd->resp_type & MMC_RSP_136) 470 sdcmd |= SDCMD_LONG_RESPONSE; 471 if (cmd->resp_type & MMC_RSP_BUSY) { 472 sdcmd |= SDCMD_BUSYWAIT; 473 host->use_busy = true; 474 } 475 } 476 477 if (data) { 478 if (data->flags & MMC_DATA_WRITE) 479 sdcmd |= SDCMD_WRITE_CMD; 480 if (data->flags & MMC_DATA_READ) 481 sdcmd |= SDCMD_READ_CMD; 482 } 483 484 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 485 486 return 0; 487 } 488 489 static int bcm2835_transfer_complete(struct bcm2835_host *host) 490 { 491 int ret = 0; 492 493 WARN_ON(!host->data_complete); 494 495 host->data = NULL; 496 497 return ret; 498 } 499 500 static void bcm2835_finish_data(struct bcm2835_host *host) 501 { 502 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 503 writel(host->hcfg, host->ioaddr + SDHCFG); 504 505 host->data_complete = true; 506 507 if (host->cmd) { 508 /* Data managed to finish before the 509 * command completed. Make sure we do 510 * things in the proper order. 511 */ 512 dev_dbg(dev, "Finished early - HSTS %08x\n", 513 readl(host->ioaddr + SDHSTS)); 514 } else { 515 bcm2835_transfer_complete(host); 516 } 517 } 518 519 static int bcm2835_finish_command(struct bcm2835_host *host) 520 { 521 struct mmc_cmd *cmd = host->cmd; 522 u32 sdcmd; 523 int ret = 0; 524 525 sdcmd = bcm2835_read_wait_sdcmd(host); 526 527 /* Check for errors */ 528 if (sdcmd & SDCMD_NEW_FLAG) { 529 printf("command never completed.\n"); 530 bcm2835_dumpregs(host); 531 return -EIO; 532 } else if (sdcmd & SDCMD_FAIL_FLAG) { 533 u32 sdhsts = readl(host->ioaddr + SDHSTS); 534 535 /* Clear the errors */ 536 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 537 538 if (!(sdhsts & SDHSTS_CRC7_ERROR) || 539 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) { 540 if (sdhsts & SDHSTS_CMD_TIME_OUT) { 541 ret = -ETIMEDOUT; 542 } else { 543 printf("unexpected command %d error\n", 544 host->cmd->cmdidx); 545 bcm2835_dumpregs(host); 546 ret = -EILSEQ; 547 } 548 549 return ret; 550 } 551 } 552 553 if (cmd->resp_type & MMC_RSP_PRESENT) { 554 if (cmd->resp_type & MMC_RSP_136) { 555 int i; 556 557 for (i = 0; i < 4; i++) { 558 cmd->response[3 - i] = 559 readl(host->ioaddr + SDRSP0 + i * 4); 560 } 561 } else { 562 cmd->response[0] = readl(host->ioaddr + SDRSP0); 563 } 564 } 565 566 /* Processed actual command. */ 567 host->cmd = NULL; 568 if (host->data && host->data_complete) 569 ret = bcm2835_transfer_complete(host); 570 571 return ret; 572 } 573 574 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 575 { 576 int ret = -EINVAL; 577 578 if (!(intmask & SDHSTS_ERROR_MASK)) 579 return 0; 580 581 if (!host->cmd) 582 return -EINVAL; 583 584 printf("sdhost_busy_irq: intmask %08x\n", intmask); 585 if (intmask & SDHSTS_CRC7_ERROR) { 586 ret = -EILSEQ; 587 } else if (intmask & (SDHSTS_CRC16_ERROR | 588 SDHSTS_FIFO_ERROR)) { 589 ret = -EILSEQ; 590 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) { 591 ret = -ETIMEDOUT; 592 } 593 bcm2835_dumpregs(host); 594 return ret; 595 } 596 597 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 598 { 599 int ret = 0; 600 601 if (!host->data) 602 return 0; 603 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 604 ret = -EILSEQ; 605 if (intmask & SDHSTS_REW_TIME_OUT) 606 ret = -ETIMEDOUT; 607 608 if (ret) 609 printf("%s:%d %d\n", __func__, __LINE__, ret); 610 611 return ret; 612 } 613 614 static void bcm2835_busy_irq(struct bcm2835_host *host) 615 { 616 if (WARN_ON(!host->cmd)) { 617 bcm2835_dumpregs(host); 618 return; 619 } 620 621 if (WARN_ON(!host->use_busy)) { 622 bcm2835_dumpregs(host); 623 return; 624 } 625 host->use_busy = false; 626 627 bcm2835_finish_command(host); 628 } 629 630 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 631 { 632 int ret; 633 634 /* 635 * There are no dedicated data/space available interrupt 636 * status bits, so it is necessary to use the single shared 637 * data/space available FIFO status bits. It is therefore not 638 * an error to get here when there is no data transfer in 639 * progress. 640 */ 641 if (!host->data) 642 return; 643 644 ret = bcm2835_check_data_error(host, intmask); 645 if (ret) 646 goto finished; 647 648 if (host->data->flags & MMC_DATA_WRITE) { 649 /* Use the block interrupt for writes after the first block */ 650 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 651 host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 652 writel(host->hcfg, host->ioaddr + SDHCFG); 653 bcm2835_transfer_pio(host); 654 } else { 655 bcm2835_transfer_pio(host); 656 host->blocks--; 657 if ((host->blocks == 0)) 658 goto finished; 659 } 660 return; 661 662 finished: 663 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 664 writel(host->hcfg, host->ioaddr + SDHCFG); 665 } 666 667 static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 668 { 669 if (!host->data) 670 return; 671 if ((host->blocks == 0)) 672 bcm2835_finish_data(host); 673 } 674 675 static void bcm2835_block_irq(struct bcm2835_host *host) 676 { 677 if (WARN_ON(!host->data)) { 678 bcm2835_dumpregs(host); 679 return; 680 } 681 682 WARN_ON(!host->blocks); 683 if ((--host->blocks == 0)) 684 bcm2835_finish_data(host); 685 else 686 bcm2835_transfer_pio(host); 687 } 688 689 static irqreturn_t bcm2835_irq(int irq, void *dev_id) 690 { 691 irqreturn_t result = IRQ_NONE; 692 struct bcm2835_host *host = dev_id; 693 u32 intmask; 694 695 intmask = readl(host->ioaddr + SDHSTS); 696 697 writel(SDHSTS_BUSY_IRPT | 698 SDHSTS_BLOCK_IRPT | 699 SDHSTS_SDIO_IRPT | 700 SDHSTS_DATA_FLAG, 701 host->ioaddr + SDHSTS); 702 703 if (intmask & SDHSTS_BLOCK_IRPT) { 704 bcm2835_check_data_error(host, intmask); 705 host->irq_block = true; 706 result = IRQ_WAKE_THREAD; 707 } 708 709 if (intmask & SDHSTS_BUSY_IRPT) { 710 if (!bcm2835_check_cmd_error(host, intmask)) { 711 host->irq_busy = true; 712 result = IRQ_WAKE_THREAD; 713 } else { 714 result = IRQ_HANDLED; 715 } 716 } 717 718 /* There is no true data interrupt status bit, so it is 719 * necessary to qualify the data flag with the interrupt 720 * enable bit. 721 */ 722 if ((intmask & SDHSTS_DATA_FLAG) && 723 (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 724 bcm2835_data_irq(host, intmask); 725 host->irq_data = true; 726 result = IRQ_WAKE_THREAD; 727 } 728 729 return result; 730 } 731 732 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 733 { 734 struct bcm2835_host *host = dev_id; 735 736 if (host->irq_block) { 737 host->irq_block = false; 738 bcm2835_block_irq(host); 739 } 740 741 if (host->irq_busy) { 742 host->irq_busy = false; 743 bcm2835_busy_irq(host); 744 } 745 746 if (host->irq_data) { 747 host->irq_data = false; 748 bcm2835_data_threaded_irq(host); 749 } 750 751 return IRQ_HANDLED; 752 } 753 754 static void bcm2835_irq_poll(struct bcm2835_host *host) 755 { 756 u32 intmask; 757 758 while (1) { 759 intmask = readl(host->ioaddr + SDHSTS); 760 if (intmask & (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | 761 SDHSTS_SDIO_IRPT | SDHSTS_DATA_FLAG)) { 762 bcm2835_irq(0, host); 763 bcm2835_threaded_irq(0, host); 764 return; 765 } 766 } 767 } 768 769 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 770 { 771 int div; 772 773 /* The SDCDIV register has 11 bits, and holds (div - 2). But 774 * in data mode the max is 50MHz wihout a minimum, and only 775 * the bottom 3 bits are used. Since the switch over is 776 * automatic (unless we have marked the card as slow...), 777 * chosen values have to make sense in both modes. Ident mode 778 * must be 100-400KHz, so can range check the requested 779 * clock. CMD15 must be used to return to data mode, so this 780 * can be monitored. 781 * 782 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 783 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 784 * 785 * 623->400KHz/27.8MHz 786 * reset value (507)->491159/50MHz 787 * 788 * BUT, the 3-bit clock divisor in data mode is too small if 789 * the core clock is higher than 250MHz, so instead use the 790 * SLOW_CARD configuration bit to force the use of the ident 791 * clock divisor at all times. 792 */ 793 794 if (clock < 100000) { 795 /* Can't stop the clock, but make it as slow as possible 796 * to show willing 797 */ 798 host->cdiv = SDCDIV_MAX_CDIV; 799 writel(host->cdiv, host->ioaddr + SDCDIV); 800 return; 801 } 802 803 div = host->max_clk / clock; 804 if (div < 2) 805 div = 2; 806 if ((host->max_clk / div) > clock) 807 div++; 808 div -= 2; 809 810 if (div > SDCDIV_MAX_CDIV) 811 div = SDCDIV_MAX_CDIV; 812 813 clock = host->max_clk / (div + 2); 814 host->mmc->clock = clock; 815 816 /* Calibrate some delays */ 817 818 host->ns_per_fifo_word = (1000000000 / clock) * 819 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32); 820 821 host->cdiv = div; 822 writel(host->cdiv, host->ioaddr + SDCDIV); 823 824 /* Set the timeout to 500ms */ 825 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT); 826 } 827 828 static inline int is_power_of_2(u64 x) 829 { 830 return !(x & (x - 1)); 831 } 832 833 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 834 struct mmc_data *data) 835 { 836 struct bcm2835_host *host = dev_get_priv(dev); 837 u32 edm, fsm; 838 int ret = 0; 839 840 if (data && !is_power_of_2(data->blocksize)) { 841 printf("unsupported block size (%d bytes)\n", data->blocksize); 842 843 if (cmd) 844 return -EINVAL; 845 } 846 847 edm = readl(host->ioaddr + SDEDM); 848 fsm = edm & SDEDM_FSM_MASK; 849 850 if ((fsm != SDEDM_FSM_IDENTMODE) && 851 (fsm != SDEDM_FSM_DATAMODE) && 852 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { 853 printf("previous command (%d) not complete (EDM %08x)\n", 854 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm); 855 bcm2835_dumpregs(host); 856 857 if (cmd) 858 return -EILSEQ; 859 860 return 0; 861 } 862 863 if (cmd) { 864 ret = bcm2835_send_command(host, cmd, data); 865 if (!ret && !host->use_busy) 866 ret = bcm2835_finish_command(host); 867 } 868 869 /* Wait for completion of busy signal or data transfer */ 870 while (host->use_busy || host->data) 871 bcm2835_irq_poll(host); 872 873 return ret; 874 } 875 876 static int bcm2835_set_ios(struct udevice *dev) 877 { 878 struct bcm2835_host *host = dev_get_priv(dev); 879 struct mmc *mmc = mmc_get_mmc_dev(dev); 880 881 if (!mmc->clock || mmc->clock != host->clock) { 882 bcm2835_set_clock(host, mmc->clock); 883 host->clock = mmc->clock; 884 } 885 886 /* set bus width */ 887 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 888 if (mmc->bus_width == 4) 889 host->hcfg |= SDHCFG_WIDE_EXT_BUS; 890 891 host->hcfg |= SDHCFG_WIDE_INT_BUS; 892 893 /* Disable clever clock switching, to cope with fast core clocks */ 894 host->hcfg |= SDHCFG_SLOW_CARD; 895 896 writel(host->hcfg, host->ioaddr + SDHCFG); 897 898 return 0; 899 } 900 901 static void bcm2835_add_host(struct bcm2835_host *host) 902 { 903 struct mmc_config *cfg = &host->plat->cfg; 904 905 cfg->f_max = host->max_clk; 906 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; 907 cfg->b_max = 65535; 908 909 dev_dbg(dev, "f_max %d, f_min %d\n", 910 cfg->f_max, cfg->f_min); 911 912 /* host controller capabilities */ 913 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; 914 915 /* report supported voltage ranges */ 916 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 917 918 /* Set interrupt enables */ 919 host->hcfg = SDHCFG_BUSY_IRPT_EN; 920 921 bcm2835_reset_internal(host); 922 } 923 924 static int bcm2835_probe(struct udevice *dev) 925 { 926 struct bcm2835_plat *plat = dev_get_platdata(dev); 927 struct bcm2835_host *host = dev_get_priv(dev); 928 struct mmc *mmc = mmc_get_mmc_dev(dev); 929 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 930 931 host->dev = dev; 932 host->mmc = mmc; 933 host->plat = plat; 934 upriv->mmc = &plat->mmc; 935 plat->cfg.name = dev->name; 936 937 host->phys_addr = devfdt_get_addr(dev); 938 if (host->phys_addr == FDT_ADDR_T_NONE) 939 return -EINVAL; 940 941 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256); 942 if (!host->ioaddr) 943 return -ENOMEM; 944 945 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE); 946 947 bcm2835_add_host(host); 948 949 dev_dbg(dev, "%s -> OK\n", __func__); 950 951 return 0; 952 } 953 954 static const struct udevice_id bcm2835_match[] = { 955 { .compatible = "brcm,bcm2835-sdhost" }, 956 { } 957 }; 958 959 static const struct dm_mmc_ops bcm2835_ops = { 960 .send_cmd = bcm2835_send_cmd, 961 .set_ios = bcm2835_set_ios, 962 }; 963 964 static int bcm2835_bind(struct udevice *dev) 965 { 966 struct bcm2835_plat *plat = dev_get_platdata(dev); 967 968 return mmc_bind(dev, &plat->mmc, &plat->cfg); 969 } 970 971 U_BOOT_DRIVER(bcm2835_sdhost) = { 972 .name = "bcm2835-sdhost", 973 .id = UCLASS_MMC, 974 .of_match = bcm2835_match, 975 .bind = bcm2835_bind, 976 .probe = bcm2835_probe, 977 .priv_auto_alloc_size = sizeof(struct bcm2835_host), 978 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat), 979 .ops = &bcm2835_ops, 980 }; 981