xref: /openbmc/u-boot/drivers/mmc/bcm2835_sdhci.c (revision 8faefadb7305b95d02df38bd2ea61429d59483e5)
1 /*
2  * This code was extracted from:
3  * git://github.com/gonzoua/u-boot-pi.git master
4  * and hence presumably (C) 2012 Oleksandr Tymoshenko
5  *
6  * Tweaks for U-Boot upstreaming
7  * (C) 2012 Stephen Warren
8  *
9  * Portions (e.g. read/write macros, concepts for back-to-back register write
10  * timing workarounds) obviously extracted from the Linux kernel at:
11  * https://github.com/raspberrypi/linux.git rpi-3.6.y
12  *
13  * The Linux kernel code has the following (c) and license, which is hence
14  * propagated to Oleksandr's tree and here:
15  *
16  * Support for SDHCI device on 2835
17  * Based on sdhci-bcm2708.c (c) 2010 Broadcom
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License version 2 as
21  * published by the Free Software Foundation.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31  */
32 
33 /* Supports:
34  * SDHCI platform device - Arasan SD controller in BCM2708
35  *
36  * Inspired by sdhci-pci.c, by Pierre Ossman
37  */
38 
39 #include <common.h>
40 #include <malloc.h>
41 #include <sdhci.h>
42 
43 /* 400KHz is max freq for card ID etc. Use that as min */
44 #define MIN_FREQ 400000
45 
46 struct bcm2835_sdhci_host {
47 	struct sdhci_host host;
48 	uint twoticks_delay;
49 	ulong last_write;
50 };
51 
52 static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host)
53 {
54 	return (struct bcm2835_sdhci_host *)host;
55 }
56 
57 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
58 						int reg)
59 {
60 	struct bcm2835_sdhci_host *bcm_host = to_bcm(host);
61 
62 	/*
63 	 * The Arasan has a bugette whereby it may lose the content of
64 	 * successive writes to registers that are within two SD-card clock
65 	 * cycles of each other (a clock domain crossing problem).
66 	 * It seems, however, that the data register does not have this problem.
67 	 * (Which is just as well - otherwise we'd have to nobble the DMA engine
68 	 * too)
69 	 */
70 	while (get_timer(bcm_host->last_write) < bcm_host->twoticks_delay)
71 		;
72 
73 	writel(val, host->ioaddr + reg);
74 	bcm_host->last_write = get_timer(0);
75 }
76 
77 static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
78 {
79 	return readl(host->ioaddr + reg);
80 }
81 
82 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
83 {
84 	bcm2835_sdhci_raw_writel(host, val, reg);
85 }
86 
87 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
88 {
89 	static u32 shadow;
90 	u32 oldval = (reg == SDHCI_COMMAND) ? shadow :
91 		bcm2835_sdhci_raw_readl(host, reg & ~3);
92 	u32 word_num = (reg >> 1) & 1;
93 	u32 word_shift = word_num * 16;
94 	u32 mask = 0xffff << word_shift;
95 	u32 newval = (oldval & ~mask) | (val << word_shift);
96 
97 	if (reg == SDHCI_TRANSFER_MODE)
98 		shadow = newval;
99 	else
100 		bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
101 }
102 
103 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
104 {
105 	u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3);
106 	u32 byte_num = reg & 3;
107 	u32 byte_shift = byte_num * 8;
108 	u32 mask = 0xff << byte_shift;
109 	u32 newval = (oldval & ~mask) | (val << byte_shift);
110 
111 	bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
112 }
113 
114 static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
115 {
116 	u32 val = bcm2835_sdhci_raw_readl(host, reg);
117 
118 	return val;
119 }
120 
121 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
122 {
123 	u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
124 	u32 word_num = (reg >> 1) & 1;
125 	u32 word_shift = word_num * 16;
126 	u32 word = (val >> word_shift) & 0xffff;
127 
128 	return word;
129 }
130 
131 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
132 {
133 	u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
134 	u32 byte_num = reg & 3;
135 	u32 byte_shift = byte_num * 8;
136 	u32 byte = (val >> byte_shift) & 0xff;
137 
138 	return byte;
139 }
140 
141 static const struct sdhci_ops bcm2835_ops = {
142 	.write_l = bcm2835_sdhci_writel,
143 	.write_w = bcm2835_sdhci_writew,
144 	.write_b = bcm2835_sdhci_writeb,
145 	.read_l = bcm2835_sdhci_readl,
146 	.read_w = bcm2835_sdhci_readw,
147 	.read_b = bcm2835_sdhci_readb,
148 };
149 
150 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq)
151 {
152 	struct bcm2835_sdhci_host *bcm_host;
153 	struct sdhci_host *host;
154 
155 	bcm_host = malloc(sizeof(*bcm_host));
156 	if (!bcm_host) {
157 		printf("sdhci_host malloc fail!\n");
158 		return 1;
159 	}
160 
161 	/*
162 	 * See the comments in bcm2835_sdhci_raw_writel().
163 	 *
164 	 * This should probably be dynamically calculated based on the actual
165 	 * frequency. However, this is the longest we'll have to wait, and
166 	 * doesn't seem to slow access down too much, so the added complexity
167 	 * doesn't seem worth it for now.
168 	 *
169 	 * 1/MIN_FREQ is (max) time per tick of eMMC clock.
170 	 * 2/MIN_FREQ is time for two ticks.
171 	 * Multiply by 1000000 to get uS per two ticks.
172 	 * +1 for hack rounding.
173 	 */
174 	bcm_host->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1;
175 	bcm_host->last_write = 0;
176 
177 	host = &bcm_host->host;
178 	host->name = "bcm2835_sdhci";
179 	host->ioaddr = (void *)regbase;
180 	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
181 		SDHCI_QUIRK_WAIT_SEND_CMD;
182 	host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
183 	host->ops = &bcm2835_ops;
184 
185 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
186 	add_sdhci(host, emmc_freq, MIN_FREQ);
187 
188 	return 0;
189 }
190