1 /* 2 * This code was extracted from: 3 * git://github.com/gonzoua/u-boot-pi.git master 4 * and hence presumably (C) 2012 Oleksandr Tymoshenko 5 * 6 * Tweaks for U-Boot upstreaming 7 * (C) 2012 Stephen Warren 8 * 9 * Portions (e.g. read/write macros, concepts for back-to-back register write 10 * timing workarounds) obviously extracted from the Linux kernel at: 11 * https://github.com/raspberrypi/linux.git rpi-3.6.y 12 * 13 * The Linux kernel code has the following (c) and license, which is hence 14 * propagated to Oleksandr's tree and here: 15 * 16 * Support for SDHCI device on 2835 17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32 33 /* Supports: 34 * SDHCI platform device - Arasan SD controller in BCM2708 35 * 36 * Inspired by sdhci-pci.c, by Pierre Ossman 37 */ 38 39 #include <common.h> 40 #include <malloc.h> 41 #include <sdhci.h> 42 #include <asm/arch/timer.h> 43 44 /* 400KHz is max freq for card ID etc. Use that as min */ 45 #define MIN_FREQ 400000 46 47 struct bcm2835_sdhci_host { 48 struct sdhci_host host; 49 uint twoticks_delay; 50 ulong last_write; 51 }; 52 53 static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host) 54 { 55 return (struct bcm2835_sdhci_host *)host; 56 } 57 58 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, 59 int reg) 60 { 61 struct bcm2835_sdhci_host *bcm_host = to_bcm(host); 62 63 /* 64 * The Arasan has a bugette whereby it may lose the content of 65 * successive writes to registers that are within two SD-card clock 66 * cycles of each other (a clock domain crossing problem). 67 * It seems, however, that the data register does not have this problem. 68 * (Which is just as well - otherwise we'd have to nobble the DMA engine 69 * too) 70 */ 71 while (get_timer_us(bcm_host->last_write) < bcm_host->twoticks_delay) 72 ; 73 74 writel(val, host->ioaddr + reg); 75 bcm_host->last_write = get_timer_us(0); 76 } 77 78 static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) 79 { 80 return readl(host->ioaddr + reg); 81 } 82 83 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 84 { 85 bcm2835_sdhci_raw_writel(host, val, reg); 86 } 87 88 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 89 { 90 static u32 shadow; 91 u32 oldval = (reg == SDHCI_COMMAND) ? shadow : 92 bcm2835_sdhci_raw_readl(host, reg & ~3); 93 u32 word_num = (reg >> 1) & 1; 94 u32 word_shift = word_num * 16; 95 u32 mask = 0xffff << word_shift; 96 u32 newval = (oldval & ~mask) | (val << word_shift); 97 98 if (reg == SDHCI_TRANSFER_MODE) 99 shadow = newval; 100 else 101 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 102 } 103 104 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 105 { 106 u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3); 107 u32 byte_num = reg & 3; 108 u32 byte_shift = byte_num * 8; 109 u32 mask = 0xff << byte_shift; 110 u32 newval = (oldval & ~mask) | (val << byte_shift); 111 112 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 113 } 114 115 static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) 116 { 117 u32 val = bcm2835_sdhci_raw_readl(host, reg); 118 119 return val; 120 } 121 122 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) 123 { 124 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 125 u32 word_num = (reg >> 1) & 1; 126 u32 word_shift = word_num * 16; 127 u32 word = (val >> word_shift) & 0xffff; 128 129 return word; 130 } 131 132 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) 133 { 134 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 135 u32 byte_num = reg & 3; 136 u32 byte_shift = byte_num * 8; 137 u32 byte = (val >> byte_shift) & 0xff; 138 139 return byte; 140 } 141 142 static const struct sdhci_ops bcm2835_ops = { 143 .write_l = bcm2835_sdhci_writel, 144 .write_w = bcm2835_sdhci_writew, 145 .write_b = bcm2835_sdhci_writeb, 146 .read_l = bcm2835_sdhci_readl, 147 .read_w = bcm2835_sdhci_readw, 148 .read_b = bcm2835_sdhci_readb, 149 }; 150 151 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq) 152 { 153 struct bcm2835_sdhci_host *bcm_host; 154 struct sdhci_host *host; 155 156 bcm_host = malloc(sizeof(*bcm_host)); 157 if (!bcm_host) { 158 printf("sdhci_host malloc fail!\n"); 159 return 1; 160 } 161 162 /* 163 * See the comments in bcm2835_sdhci_raw_writel(). 164 * 165 * This should probably be dynamically calculated based on the actual 166 * frequency. However, this is the longest we'll have to wait, and 167 * doesn't seem to slow access down too much, so the added complexity 168 * doesn't seem worth it for now. 169 * 170 * 1/MIN_FREQ is (max) time per tick of eMMC clock. 171 * 2/MIN_FREQ is time for two ticks. 172 * Multiply by 1000000 to get uS per two ticks. 173 * +1 for hack rounding. 174 */ 175 bcm_host->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1; 176 bcm_host->last_write = 0; 177 178 host = &bcm_host->host; 179 host->name = "bcm2835_sdhci"; 180 host->ioaddr = (void *)regbase; 181 host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | 182 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; 183 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 184 host->ops = &bcm2835_ops; 185 186 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 187 add_sdhci(host, emmc_freq, MIN_FREQ); 188 189 return 0; 190 } 191