1 /* 2 * This code was extracted from: 3 * git://github.com/gonzoua/u-boot-pi.git master 4 * and hence presumably (C) 2012 Oleksandr Tymoshenko 5 * 6 * Tweaks for U-Boot upstreaming 7 * (C) 2012 Stephen Warren 8 * 9 * Portions (e.g. read/write macros, concepts for back-to-back register write 10 * timing workarounds) obviously extracted from the Linux kernel at: 11 * https://github.com/raspberrypi/linux.git rpi-3.6.y 12 * 13 * The Linux kernel code has the following (c) and license, which is hence 14 * propagated to Oleksandr's tree and here: 15 * 16 * Support for SDHCI device on 2835 17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32 33 /* Supports: 34 * SDHCI platform device - Arasan SD controller in BCM2708 35 * 36 * Inspired by sdhci-pci.c, by Pierre Ossman 37 */ 38 39 #include <common.h> 40 #include <malloc.h> 41 #include <sdhci.h> 42 #include <mach/timer.h> 43 #include <mach/sdhci.h> 44 45 /* 400KHz is max freq for card ID etc. Use that as min */ 46 #define MIN_FREQ 400000 47 48 struct bcm2835_sdhci_host { 49 struct sdhci_host host; 50 uint twoticks_delay; 51 ulong last_write; 52 }; 53 54 static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host) 55 { 56 return (struct bcm2835_sdhci_host *)host; 57 } 58 59 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, 60 int reg) 61 { 62 struct bcm2835_sdhci_host *bcm_host = to_bcm(host); 63 64 /* 65 * The Arasan has a bugette whereby it may lose the content of 66 * successive writes to registers that are within two SD-card clock 67 * cycles of each other (a clock domain crossing problem). 68 * It seems, however, that the data register does not have this problem. 69 * (Which is just as well - otherwise we'd have to nobble the DMA engine 70 * too) 71 */ 72 while (timer_get_us() - bcm_host->last_write < bcm_host->twoticks_delay) 73 ; 74 75 writel(val, host->ioaddr + reg); 76 bcm_host->last_write = timer_get_us(); 77 } 78 79 static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) 80 { 81 return readl(host->ioaddr + reg); 82 } 83 84 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 85 { 86 bcm2835_sdhci_raw_writel(host, val, reg); 87 } 88 89 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 90 { 91 static u32 shadow; 92 u32 oldval = (reg == SDHCI_COMMAND) ? shadow : 93 bcm2835_sdhci_raw_readl(host, reg & ~3); 94 u32 word_num = (reg >> 1) & 1; 95 u32 word_shift = word_num * 16; 96 u32 mask = 0xffff << word_shift; 97 u32 newval = (oldval & ~mask) | (val << word_shift); 98 99 if (reg == SDHCI_TRANSFER_MODE) 100 shadow = newval; 101 else 102 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 103 } 104 105 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 106 { 107 u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3); 108 u32 byte_num = reg & 3; 109 u32 byte_shift = byte_num * 8; 110 u32 mask = 0xff << byte_shift; 111 u32 newval = (oldval & ~mask) | (val << byte_shift); 112 113 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 114 } 115 116 static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) 117 { 118 u32 val = bcm2835_sdhci_raw_readl(host, reg); 119 120 return val; 121 } 122 123 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) 124 { 125 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 126 u32 word_num = (reg >> 1) & 1; 127 u32 word_shift = word_num * 16; 128 u32 word = (val >> word_shift) & 0xffff; 129 130 return word; 131 } 132 133 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) 134 { 135 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 136 u32 byte_num = reg & 3; 137 u32 byte_shift = byte_num * 8; 138 u32 byte = (val >> byte_shift) & 0xff; 139 140 return byte; 141 } 142 143 static const struct sdhci_ops bcm2835_ops = { 144 .write_l = bcm2835_sdhci_writel, 145 .write_w = bcm2835_sdhci_writew, 146 .write_b = bcm2835_sdhci_writeb, 147 .read_l = bcm2835_sdhci_readl, 148 .read_w = bcm2835_sdhci_readw, 149 .read_b = bcm2835_sdhci_readb, 150 }; 151 152 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq) 153 { 154 struct bcm2835_sdhci_host *bcm_host; 155 struct sdhci_host *host; 156 157 bcm_host = calloc(1, sizeof(*bcm_host)); 158 if (!bcm_host) { 159 printf("sdhci_host calloc fail!\n"); 160 return -ENOMEM; 161 } 162 163 /* 164 * See the comments in bcm2835_sdhci_raw_writel(). 165 * 166 * This should probably be dynamically calculated based on the actual 167 * frequency. However, this is the longest we'll have to wait, and 168 * doesn't seem to slow access down too much, so the added complexity 169 * doesn't seem worth it for now. 170 * 171 * 1/MIN_FREQ is (max) time per tick of eMMC clock. 172 * 2/MIN_FREQ is time for two ticks. 173 * Multiply by 1000000 to get uS per two ticks. 174 * +1 for hack rounding. 175 */ 176 bcm_host->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1; 177 bcm_host->last_write = 0; 178 179 host = &bcm_host->host; 180 host->name = "bcm2835_sdhci"; 181 host->ioaddr = (void *)(unsigned long)regbase; 182 host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | 183 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; 184 host->max_clk = emmc_freq; 185 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 186 host->ops = &bcm2835_ops; 187 188 add_sdhci(host, 0, MIN_FREQ); 189 190 return 0; 191 } 192