1 /* 2 * This code was extracted from: 3 * git://github.com/gonzoua/u-boot-pi.git master 4 * and hence presumably (C) 2012 Oleksandr Tymoshenko 5 * 6 * Tweaks for U-Boot upstreaming 7 * (C) 2012 Stephen Warren 8 * 9 * Portions (e.g. read/write macros, concepts for back-to-back register write 10 * timing workarounds) obviously extracted from the Linux kernel at: 11 * https://github.com/raspberrypi/linux.git rpi-3.6.y 12 * 13 * The Linux kernel code has the following (c) and license, which is hence 14 * propagated to Oleksandr's tree and here: 15 * 16 * Support for SDHCI device on 2835 17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32 33 /* Supports: 34 * SDHCI platform device - Arasan SD controller in BCM2708 35 * 36 * Inspired by sdhci-pci.c, by Pierre Ossman 37 */ 38 39 #include <common.h> 40 #include <malloc.h> 41 #include <sdhci.h> 42 #include <mach/timer.h> 43 #include <mach/sdhci.h> 44 45 /* 400KHz is max freq for card ID etc. Use that as min */ 46 #define MIN_FREQ 400000 47 #define SDHCI_BUFFER 0x20 48 49 struct bcm2835_sdhci_host { 50 struct sdhci_host host; 51 uint twoticks_delay; 52 ulong last_write; 53 }; 54 55 static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host) 56 { 57 return (struct bcm2835_sdhci_host *)host; 58 } 59 60 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, 61 int reg) 62 { 63 struct bcm2835_sdhci_host *bcm_host = to_bcm(host); 64 65 /* 66 * The Arasan has a bugette whereby it may lose the content of 67 * successive writes to registers that are within two SD-card clock 68 * cycles of each other (a clock domain crossing problem). 69 * It seems, however, that the data register does not have this problem. 70 * (Which is just as well - otherwise we'd have to nobble the DMA engine 71 * too) 72 */ 73 if (reg != SDHCI_BUFFER) { 74 while (timer_get_us() - bcm_host->last_write < 75 bcm_host->twoticks_delay) 76 ; 77 } 78 79 writel(val, host->ioaddr + reg); 80 bcm_host->last_write = timer_get_us(); 81 } 82 83 static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) 84 { 85 return readl(host->ioaddr + reg); 86 } 87 88 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 89 { 90 bcm2835_sdhci_raw_writel(host, val, reg); 91 } 92 93 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 94 { 95 static u32 shadow; 96 u32 oldval = (reg == SDHCI_COMMAND) ? shadow : 97 bcm2835_sdhci_raw_readl(host, reg & ~3); 98 u32 word_num = (reg >> 1) & 1; 99 u32 word_shift = word_num * 16; 100 u32 mask = 0xffff << word_shift; 101 u32 newval = (oldval & ~mask) | (val << word_shift); 102 103 if (reg == SDHCI_TRANSFER_MODE) 104 shadow = newval; 105 else 106 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 107 } 108 109 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 110 { 111 u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3); 112 u32 byte_num = reg & 3; 113 u32 byte_shift = byte_num * 8; 114 u32 mask = 0xff << byte_shift; 115 u32 newval = (oldval & ~mask) | (val << byte_shift); 116 117 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 118 } 119 120 static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) 121 { 122 u32 val = bcm2835_sdhci_raw_readl(host, reg); 123 124 return val; 125 } 126 127 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) 128 { 129 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 130 u32 word_num = (reg >> 1) & 1; 131 u32 word_shift = word_num * 16; 132 u32 word = (val >> word_shift) & 0xffff; 133 134 return word; 135 } 136 137 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) 138 { 139 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 140 u32 byte_num = reg & 3; 141 u32 byte_shift = byte_num * 8; 142 u32 byte = (val >> byte_shift) & 0xff; 143 144 return byte; 145 } 146 147 static const struct sdhci_ops bcm2835_ops = { 148 .write_l = bcm2835_sdhci_writel, 149 .write_w = bcm2835_sdhci_writew, 150 .write_b = bcm2835_sdhci_writeb, 151 .read_l = bcm2835_sdhci_readl, 152 .read_w = bcm2835_sdhci_readw, 153 .read_b = bcm2835_sdhci_readb, 154 }; 155 156 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq) 157 { 158 struct bcm2835_sdhci_host *bcm_host; 159 struct sdhci_host *host; 160 161 bcm_host = calloc(1, sizeof(*bcm_host)); 162 if (!bcm_host) { 163 printf("sdhci_host calloc fail!\n"); 164 return -ENOMEM; 165 } 166 167 /* 168 * See the comments in bcm2835_sdhci_raw_writel(). 169 * 170 * This should probably be dynamically calculated based on the actual 171 * frequency. However, this is the longest we'll have to wait, and 172 * doesn't seem to slow access down too much, so the added complexity 173 * doesn't seem worth it for now. 174 * 175 * 1/MIN_FREQ is (max) time per tick of eMMC clock. 176 * 2/MIN_FREQ is time for two ticks. 177 * Multiply by 1000000 to get uS per two ticks. 178 * +1 for hack rounding. 179 */ 180 bcm_host->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1; 181 bcm_host->last_write = 0; 182 183 host = &bcm_host->host; 184 host->name = "bcm2835_sdhci"; 185 host->ioaddr = (void *)(unsigned long)regbase; 186 host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | 187 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; 188 host->max_clk = emmc_freq; 189 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 190 host->ops = &bcm2835_ops; 191 192 add_sdhci(host, 0, MIN_FREQ); 193 194 return 0; 195 } 196