1 /* 2 * Copyright (C) 2015 Atmel Corporation 3 * Wenyou.Yang <wenyou.yang@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <malloc.h> 12 #include <sdhci.h> 13 #include <asm/arch/clk.h> 14 15 #define ATMEL_SDHC_MIN_FREQ 400000 16 17 #ifndef CONFIG_DM_MMC 18 int atmel_sdhci_init(void *regbase, u32 id) 19 { 20 struct sdhci_host *host; 21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; 22 23 host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host)); 24 if (!host) { 25 printf("%s: sdhci_host calloc failed\n", __func__); 26 return -ENOMEM; 27 } 28 29 host->name = "atmel_sdhci"; 30 host->ioaddr = regbase; 31 host->quirks = 0; 32 max_clk = at91_get_periph_generated_clk(id); 33 if (!max_clk) { 34 printf("%s: Failed to get the proper clock\n", __func__); 35 free(host); 36 return -ENODEV; 37 } 38 39 add_sdhci(host, max_clk, min_clk); 40 41 return 0; 42 } 43 44 #else 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 struct atmel_sdhci_plat { 49 struct mmc_config cfg; 50 struct mmc mmc; 51 }; 52 53 static int atmel_sdhci_get_clk(struct udevice *dev, int index, struct clk *clk) 54 { 55 struct udevice *dev_clk; 56 int periph, ret; 57 58 ret = clk_get_by_index(dev, index, clk); 59 if (ret) 60 return ret; 61 62 periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1); 63 if (periph < 0) 64 return -EINVAL; 65 66 dev_clk = dev_get_parent(clk->dev); 67 ret = clk_request(dev_clk, clk); 68 if (ret) 69 return ret; 70 71 clk->id = periph; 72 73 return 0; 74 } 75 76 static int atmel_sdhci_probe(struct udevice *dev) 77 { 78 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 79 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 80 struct sdhci_host *host = dev_get_priv(dev); 81 u32 max_clk; 82 u32 caps, caps_1; 83 u32 clk_base, clk_mul; 84 ulong gck_rate; 85 struct clk clk; 86 int ret; 87 88 ret = atmel_sdhci_get_clk(dev, 0, &clk); 89 if (ret) 90 return ret; 91 92 ret = clk_enable(&clk); 93 if (ret) 94 return ret; 95 96 host->name = dev->name; 97 host->ioaddr = (void *)dev_get_addr(dev); 98 99 host->quirks = 0; 100 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 101 "bus-width", 4); 102 103 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 104 clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 105 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 106 clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 107 gck_rate = clk_base * 1000000 * (clk_mul + 1); 108 109 ret = atmel_sdhci_get_clk(dev, 1, &clk); 110 if (ret) 111 return ret; 112 113 ret = clk_set_rate(&clk, gck_rate); 114 if (ret) 115 return ret; 116 117 max_clk = clk_get_rate(&clk); 118 if (!max_clk) 119 return -EINVAL; 120 121 ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ); 122 if (ret) 123 return ret; 124 125 host->mmc = &plat->mmc; 126 host->mmc->dev = dev; 127 host->mmc->priv = host; 128 upriv->mmc = host->mmc; 129 130 clk_free(&clk); 131 132 return sdhci_probe(dev); 133 } 134 135 static int atmel_sdhci_bind(struct udevice *dev) 136 { 137 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 138 139 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 140 } 141 142 static const struct udevice_id atmel_sdhci_ids[] = { 143 { .compatible = "atmel,sama5d2-sdhci" }, 144 { } 145 }; 146 147 U_BOOT_DRIVER(atmel_sdhci_drv) = { 148 .name = "atmel_sdhci", 149 .id = UCLASS_MMC, 150 .of_match = atmel_sdhci_ids, 151 .ops = &sdhci_ops, 152 .bind = atmel_sdhci_bind, 153 .probe = atmel_sdhci_probe, 154 .priv_auto_alloc_size = sizeof(struct sdhci_host), 155 .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat), 156 }; 157 #endif 158