1 /* 2 * Copyright (C) 2015 Atmel Corporation 3 * Wenyou.Yang <wenyou.yang@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <malloc.h> 12 #include <sdhci.h> 13 #include <asm/arch/clk.h> 14 15 #define ATMEL_SDHC_MIN_FREQ 400000 16 17 #ifndef CONFIG_DM_MMC 18 int atmel_sdhci_init(void *regbase, u32 id) 19 { 20 struct sdhci_host *host; 21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; 22 23 host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host)); 24 if (!host) { 25 printf("%s: sdhci_host calloc failed\n", __func__); 26 return -ENOMEM; 27 } 28 29 host->name = "atmel_sdhci"; 30 host->ioaddr = regbase; 31 host->quirks = 0; 32 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 33 max_clk = at91_get_periph_generated_clk(id); 34 if (!max_clk) { 35 printf("%s: Failed to get the proper clock\n", __func__); 36 free(host); 37 return -ENODEV; 38 } 39 40 add_sdhci(host, max_clk, min_clk); 41 42 return 0; 43 } 44 45 #else 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 struct atmel_sdhci_plat { 50 struct mmc_config cfg; 51 struct mmc mmc; 52 }; 53 54 static int atmel_sdhci_get_clk(struct udevice *dev, int index, struct clk *clk) 55 { 56 struct udevice *dev_clk; 57 int periph, ret; 58 59 ret = clk_get_by_index(dev, index, clk); 60 if (ret) 61 return ret; 62 63 periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1); 64 if (periph < 0) 65 return -EINVAL; 66 67 dev_clk = dev_get_parent(clk->dev); 68 ret = clk_request(dev_clk, clk); 69 if (ret) 70 return ret; 71 72 clk->id = periph; 73 74 return 0; 75 } 76 77 static int atmel_sdhci_probe(struct udevice *dev) 78 { 79 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 80 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 81 struct sdhci_host *host = dev_get_priv(dev); 82 u32 max_clk; 83 u32 caps, caps_1; 84 u32 clk_base, clk_mul; 85 ulong gck_rate; 86 struct clk clk; 87 int ret; 88 89 ret = atmel_sdhci_get_clk(dev, 0, &clk); 90 if (ret) 91 return ret; 92 93 ret = clk_enable(&clk); 94 if (ret) 95 return ret; 96 97 host->name = dev->name; 98 host->ioaddr = (void *)dev_get_addr(dev); 99 100 host->quirks = 0; 101 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 102 "bus-width", 4); 103 104 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 105 clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 106 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 107 clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 108 gck_rate = clk_base * 1000000 * (clk_mul + 1); 109 110 ret = atmel_sdhci_get_clk(dev, 1, &clk); 111 if (ret) 112 return ret; 113 114 ret = clk_set_rate(&clk, gck_rate); 115 if (ret) 116 return ret; 117 118 max_clk = clk_get_rate(&clk); 119 if (!max_clk) 120 return -EINVAL; 121 122 ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ); 123 if (ret) 124 return ret; 125 126 host->mmc = &plat->mmc; 127 host->mmc->dev = dev; 128 host->mmc->priv = host; 129 upriv->mmc = host->mmc; 130 131 clk_free(&clk); 132 133 return sdhci_probe(dev); 134 } 135 136 static int atmel_sdhci_bind(struct udevice *dev) 137 { 138 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 139 140 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 141 } 142 143 static const struct udevice_id atmel_sdhci_ids[] = { 144 { .compatible = "atmel,sama5d2-sdhci" }, 145 { } 146 }; 147 148 U_BOOT_DRIVER(atmel_sdhci_drv) = { 149 .name = "atmel_sdhci", 150 .id = UCLASS_MMC, 151 .of_match = atmel_sdhci_ids, 152 .ops = &sdhci_ops, 153 .bind = atmel_sdhci_bind, 154 .probe = atmel_sdhci_probe, 155 .priv_auto_alloc_size = sizeof(struct sdhci_host), 156 .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat), 157 }; 158 #endif 159