1 /* 2 * Copyright (C) 2015 Atmel Corporation 3 * Wenyou.Yang <wenyou.yang@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <malloc.h> 12 #include <sdhci.h> 13 #include <asm/arch/clk.h> 14 15 #define ATMEL_SDHC_MIN_FREQ 400000 16 17 #ifndef CONFIG_DM_MMC 18 int atmel_sdhci_init(void *regbase, u32 id) 19 { 20 struct sdhci_host *host; 21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; 22 23 host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host)); 24 if (!host) { 25 printf("%s: sdhci_host calloc failed\n", __func__); 26 return -ENOMEM; 27 } 28 29 host->name = "atmel_sdhci"; 30 host->ioaddr = regbase; 31 host->quirks = 0; 32 max_clk = at91_get_periph_generated_clk(id); 33 if (!max_clk) { 34 printf("%s: Failed to get the proper clock\n", __func__); 35 free(host); 36 return -ENODEV; 37 } 38 39 add_sdhci(host, max_clk, min_clk); 40 41 return 0; 42 } 43 44 #else 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 struct atmel_sdhci_plat { 49 struct mmc_config cfg; 50 struct mmc mmc; 51 }; 52 53 static int atmel_sdhci_probe(struct udevice *dev) 54 { 55 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 56 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 57 struct sdhci_host *host = dev_get_priv(dev); 58 u32 max_clk; 59 u32 caps, caps_1; 60 u32 clk_base, clk_mul; 61 ulong gck_rate; 62 struct clk clk; 63 int ret; 64 65 ret = clk_get_by_index(dev, 0, &clk); 66 if (ret) 67 return ret; 68 69 ret = clk_enable(&clk); 70 if (ret) 71 return ret; 72 73 host->name = dev->name; 74 host->ioaddr = (void *)dev_get_addr(dev); 75 76 host->quirks = 0; 77 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 78 "bus-width", 4); 79 80 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 81 clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 82 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 83 clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 84 gck_rate = clk_base * 1000000 * (clk_mul + 1); 85 86 ret = clk_get_by_index(dev, 1, &clk); 87 if (ret) 88 return ret; 89 90 ret = clk_set_rate(&clk, gck_rate); 91 if (ret) 92 return ret; 93 94 max_clk = clk_get_rate(&clk); 95 if (!max_clk) 96 return -EINVAL; 97 98 ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ); 99 if (ret) 100 return ret; 101 102 host->mmc = &plat->mmc; 103 host->mmc->dev = dev; 104 host->mmc->priv = host; 105 upriv->mmc = host->mmc; 106 107 clk_free(&clk); 108 109 return sdhci_probe(dev); 110 } 111 112 static int atmel_sdhci_bind(struct udevice *dev) 113 { 114 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 115 116 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 117 } 118 119 static const struct udevice_id atmel_sdhci_ids[] = { 120 { .compatible = "atmel,sama5d2-sdhci" }, 121 { } 122 }; 123 124 U_BOOT_DRIVER(atmel_sdhci_drv) = { 125 .name = "atmel_sdhci", 126 .id = UCLASS_MMC, 127 .of_match = atmel_sdhci_ids, 128 .ops = &sdhci_ops, 129 .bind = atmel_sdhci_bind, 130 .probe = atmel_sdhci_probe, 131 .priv_auto_alloc_size = sizeof(struct sdhci_host), 132 .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat), 133 }; 134 #endif 135