1 /* 2 * Copyright (C) 2015 Atmel Corporation 3 * Wenyou.Yang <wenyou.yang@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <malloc.h> 12 #include <sdhci.h> 13 #include <asm/arch/clk.h> 14 15 #define ATMEL_SDHC_MIN_FREQ 400000 16 17 #ifndef CONFIG_DM_MMC 18 int atmel_sdhci_init(void *regbase, u32 id) 19 { 20 struct sdhci_host *host; 21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; 22 23 host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host)); 24 if (!host) { 25 printf("%s: sdhci_host calloc failed\n", __func__); 26 return -ENOMEM; 27 } 28 29 host->name = "atmel_sdhci"; 30 host->ioaddr = regbase; 31 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 32 max_clk = at91_get_periph_generated_clk(id); 33 if (!max_clk) { 34 printf("%s: Failed to get the proper clock\n", __func__); 35 free(host); 36 return -ENODEV; 37 } 38 host->max_clk = max_clk; 39 40 add_sdhci(host, 0, min_clk); 41 42 return 0; 43 } 44 45 #else 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 struct atmel_sdhci_plat { 50 struct mmc_config cfg; 51 struct mmc mmc; 52 }; 53 54 static int atmel_sdhci_probe(struct udevice *dev) 55 { 56 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 57 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 58 struct sdhci_host *host = dev_get_priv(dev); 59 u32 max_clk; 60 u32 caps, caps_1; 61 u32 clk_base, clk_mul; 62 ulong gck_rate; 63 struct clk clk; 64 int ret; 65 66 ret = clk_get_by_index(dev, 0, &clk); 67 if (ret) 68 return ret; 69 70 ret = clk_enable(&clk); 71 if (ret) 72 return ret; 73 74 host->name = dev->name; 75 host->ioaddr = (void *)devfdt_get_addr(dev); 76 77 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 78 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 79 "bus-width", 4); 80 81 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 82 clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 83 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 84 clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; 85 gck_rate = clk_base * 1000000 * (clk_mul + 1); 86 87 ret = clk_get_by_index(dev, 1, &clk); 88 if (ret) 89 return ret; 90 91 ret = clk_set_rate(&clk, gck_rate); 92 if (ret) 93 return ret; 94 95 max_clk = clk_get_rate(&clk); 96 if (!max_clk) 97 return -EINVAL; 98 99 host->max_clk = max_clk; 100 101 ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ); 102 if (ret) 103 return ret; 104 105 host->mmc = &plat->mmc; 106 host->mmc->dev = dev; 107 host->mmc->priv = host; 108 upriv->mmc = host->mmc; 109 110 clk_free(&clk); 111 112 return sdhci_probe(dev); 113 } 114 115 static int atmel_sdhci_bind(struct udevice *dev) 116 { 117 struct atmel_sdhci_plat *plat = dev_get_platdata(dev); 118 119 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 120 } 121 122 static const struct udevice_id atmel_sdhci_ids[] = { 123 { .compatible = "atmel,sama5d2-sdhci" }, 124 { } 125 }; 126 127 U_BOOT_DRIVER(atmel_sdhci_drv) = { 128 .name = "atmel_sdhci", 129 .id = UCLASS_MMC, 130 .of_match = atmel_sdhci_ids, 131 .ops = &sdhci_ops, 132 .bind = atmel_sdhci_bind, 133 .probe = atmel_sdhci_probe, 134 .priv_auto_alloc_size = sizeof(struct sdhci_host), 135 .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat), 136 }; 137 #endif 138