1 /* 2 * ARM PrimeCell MultiMedia Card Interface - PL180 3 * 4 * Copyright (C) ST-Ericsson SA 2010 5 * 6 * Author: Ulf Hansson <ulf.hansson@stericsson.com> 7 * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com> 8 * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __ARM_PL180_MMCI_H__ 14 #define __ARM_PL180_MMCI_H__ 15 16 #define COMMAND_REG_DELAY 300 17 #define DATA_REG_DELAY 1000 18 #define CLK_CHANGE_DELAY 2000 19 20 #define INIT_PWR 0xBF /* Power on, full power, not open drain */ 21 #define ARM_MCLK (100*1000*1000) 22 23 /* SDI Power Control register bits */ 24 #define SDI_PWR_PWRCTRL_MASK 0x00000003 25 #define SDI_PWR_PWRCTRL_ON 0x00000003 26 #define SDI_PWR_PWRCTRL_OFF 0x00000000 27 #define SDI_PWR_DAT2DIREN 0x00000004 28 #define SDI_PWR_CMDDIREN 0x00000008 29 #define SDI_PWR_DAT0DIREN 0x00000010 30 #define SDI_PWR_DAT31DIREN 0x00000020 31 #define SDI_PWR_OPD 0x00000040 32 #define SDI_PWR_FBCLKEN 0x00000080 33 #define SDI_PWR_DAT74DIREN 0x00000100 34 #define SDI_PWR_RSTEN 0x00000200 35 36 #define VOLTAGE_WINDOW_MMC 0x00FF8080 37 #define VOLTAGE_WINDOW_SD 0x80010000 38 39 /* SDI clock control register bits */ 40 #define SDI_CLKCR_CLKDIV_MASK 0x000000FF 41 #define SDI_CLKCR_CLKEN 0x00000100 42 #define SDI_CLKCR_PWRSAV 0x00000200 43 #define SDI_CLKCR_BYPASS 0x00000400 44 #define SDI_CLKCR_WIDBUS_MASK 0x00001800 45 #define SDI_CLKCR_WIDBUS_1 0x00000000 46 #define SDI_CLKCR_WIDBUS_4 0x00000800 47 /* V2 only */ 48 #define SDI_CLKCR_WIDBUS_8 0x00001000 49 #define SDI_CLKCR_NEDGE 0x00002000 50 #define SDI_CLKCR_HWFC_EN 0x00004000 51 52 #define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */ 53 #define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD 54 55 /* SDI command register bits */ 56 #define SDI_CMD_CMDINDEX_MASK 0x000000FF 57 #define SDI_CMD_WAITRESP 0x00000040 58 #define SDI_CMD_LONGRESP 0x00000080 59 #define SDI_CMD_WAITINT 0x00000100 60 #define SDI_CMD_WAITPEND 0x00000200 61 #define SDI_CMD_CPSMEN 0x00000400 62 #define SDI_CMD_SDIOSUSPEND 0x00000800 63 #define SDI_CMD_ENDCMDCOMPL 0x00001000 64 #define SDI_CMD_NIEN 0x00002000 65 #define SDI_CMD_CE_ATACMD 0x00004000 66 #define SDI_CMD_CBOOTMODEEN 0x00008000 67 68 #define SDI_DTIMER_DEFAULT 0xFFFF0000 69 70 /* SDI Status register bits */ 71 #define SDI_STA_CCRCFAIL 0x00000001 72 #define SDI_STA_DCRCFAIL 0x00000002 73 #define SDI_STA_CTIMEOUT 0x00000004 74 #define SDI_STA_DTIMEOUT 0x00000008 75 #define SDI_STA_TXUNDERR 0x00000010 76 #define SDI_STA_RXOVERR 0x00000020 77 #define SDI_STA_CMDREND 0x00000040 78 #define SDI_STA_CMDSENT 0x00000080 79 #define SDI_STA_DATAEND 0x00000100 80 #define SDI_STA_STBITERR 0x00000200 81 #define SDI_STA_DBCKEND 0x00000400 82 #define SDI_STA_CMDACT 0x00000800 83 #define SDI_STA_TXACT 0x00001000 84 #define SDI_STA_RXACT 0x00002000 85 #define SDI_STA_TXFIFOBW 0x00004000 86 #define SDI_STA_RXFIFOBR 0x00008000 87 #define SDI_STA_TXFIFOF 0x00010000 88 #define SDI_STA_RXFIFOF 0x00020000 89 #define SDI_STA_TXFIFOE 0x00040000 90 #define SDI_STA_RXFIFOE 0x00080000 91 #define SDI_STA_TXDAVL 0x00100000 92 #define SDI_STA_RXDAVL 0x00200000 93 #define SDI_STA_SDIOIT 0x00400000 94 #define SDI_STA_CEATAEND 0x00800000 95 #define SDI_STA_CARDBUSY 0x01000000 96 #define SDI_STA_BOOTMODE 0x02000000 97 #define SDI_STA_BOOTACKERR 0x04000000 98 #define SDI_STA_BOOTACKTIMEOUT 0x08000000 99 #define SDI_STA_RSTNEND 0x10000000 100 101 /* SDI Interrupt Clear register bits */ 102 #define SDI_ICR_MASK 0x1DC007FF 103 #define SDI_ICR_CCRCFAILC 0x00000001 104 #define SDI_ICR_DCRCFAILC 0x00000002 105 #define SDI_ICR_CTIMEOUTC 0x00000004 106 #define SDI_ICR_DTIMEOUTC 0x00000008 107 #define SDI_ICR_TXUNDERRC 0x00000010 108 #define SDI_ICR_RXOVERRC 0x00000020 109 #define SDI_ICR_CMDRENDC 0x00000040 110 #define SDI_ICR_CMDSENTC 0x00000080 111 #define SDI_ICR_DATAENDC 0x00000100 112 #define SDI_ICR_STBITERRC 0x00000200 113 #define SDI_ICR_DBCKENDC 0x00000400 114 #define SDI_ICR_SDIOITC 0x00400000 115 #define SDI_ICR_CEATAENDC 0x00800000 116 #define SDI_ICR_BUSYENDC 0x01000000 117 #define SDI_ICR_BOOTACKERRC 0x04000000 118 #define SDI_ICR_BOOTACKTIMEOUTC 0x08000000 119 #define SDI_ICR_RSTNENDC 0x10000000 120 121 #define SDI_MASK0_MASK 0x1FFFFFFF 122 123 /* SDI Data control register bits */ 124 #define SDI_DCTRL_DTEN 0x00000001 125 #define SDI_DCTRL_DTDIR_IN 0x00000002 126 #define SDI_DCTRL_DTMODE_STREAM 0x00000004 127 #define SDI_DCTRL_DMAEN 0x00000008 128 #define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0 129 #define SDI_DCTRL_RWSTART 0x00000100 130 #define SDI_DCTRL_RWSTOP 0x00000200 131 #define SDI_DCTRL_RWMOD 0x00000200 132 #define SDI_DCTRL_SDIOEN 0x00000800 133 #define SDI_DCTRL_DMAREQCTL 0x00001000 134 #define SDI_DCTRL_DBOOTMODEEN 0x00002000 135 #define SDI_DCTRL_BUSYMODE 0x00004000 136 #define SDI_DCTRL_DDR_MODE 0x00008000 137 #define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000 138 #define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16 139 140 #define SDI_FIFO_BURST_SIZE 8 141 142 struct sdi_registers { 143 u32 power; /* 0x00*/ 144 u32 clock; /* 0x04*/ 145 u32 argument; /* 0x08*/ 146 u32 command; /* 0x0c*/ 147 u32 respcommand; /* 0x10*/ 148 u32 response0; /* 0x14*/ 149 u32 response1; /* 0x18*/ 150 u32 response2; /* 0x1c*/ 151 u32 response3; /* 0x20*/ 152 u32 datatimer; /* 0x24*/ 153 u32 datalength; /* 0x28*/ 154 u32 datactrl; /* 0x2c*/ 155 u32 datacount; /* 0x30*/ 156 u32 status; /* 0x34*/ 157 u32 status_clear; /* 0x38*/ 158 u32 mask0; /* 0x3c*/ 159 u32 mask1; /* 0x40*/ 160 u32 card_select; /* 0x44*/ 161 u32 fifo_count; /* 0x48*/ 162 u32 padding1[(0x80-0x4C)>>2]; 163 u32 fifo; /* 0x80*/ 164 u32 padding2[(0xFE0-0x84)>>2]; 165 u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/ 166 u32 periph_id1; /* 0xFE4*/ 167 u32 periph_id2; /* 0xFE8*/ 168 u32 periph_id3; /* 0xFEC*/ 169 u32 pcell_id0; /* 0xFF0*/ 170 u32 pcell_id1; /* 0xFF4*/ 171 u32 pcell_id2; /* 0xFF8*/ 172 u32 pcell_id3; /* 0xFFC*/ 173 }; 174 175 struct pl180_mmc_host { 176 struct sdi_registers *base; 177 char name[32]; 178 unsigned int b_max; 179 unsigned int voltages; 180 unsigned int caps; 181 unsigned int clock_in; 182 unsigned int clock_min; 183 unsigned int clock_max; 184 unsigned int clkdiv_init; 185 unsigned int pwr_init; 186 int version2; 187 }; 188 189 int arm_pl180_mmci_init(struct pl180_mmc_host *); 190 191 #endif 192