1 /* 2 * ARM PrimeCell MultiMedia Card Interface - PL180 3 * 4 * Copyright (C) ST-Ericsson SA 2010 5 * 6 * Author: Ulf Hansson <ulf.hansson@stericsson.com> 7 * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com> 8 * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __ARM_PL180_MMCI_H__ 27 #define __ARM_PL180_MMCI_H__ 28 29 #define COMMAND_REG_DELAY 300 30 #define DATA_REG_DELAY 1000 31 #define CLK_CHANGE_DELAY 2000 32 33 #define INIT_PWR 0xBF /* Power on, full power, not open drain */ 34 #define ARM_MCLK (100*1000*1000) 35 36 /* SDI Power Control register bits */ 37 #define SDI_PWR_PWRCTRL_MASK 0x00000003 38 #define SDI_PWR_PWRCTRL_ON 0x00000003 39 #define SDI_PWR_PWRCTRL_OFF 0x00000000 40 #define SDI_PWR_DAT2DIREN 0x00000004 41 #define SDI_PWR_CMDDIREN 0x00000008 42 #define SDI_PWR_DAT0DIREN 0x00000010 43 #define SDI_PWR_DAT31DIREN 0x00000020 44 #define SDI_PWR_OPD 0x00000040 45 #define SDI_PWR_FBCLKEN 0x00000080 46 #define SDI_PWR_DAT74DIREN 0x00000100 47 #define SDI_PWR_RSTEN 0x00000200 48 49 #define VOLTAGE_WINDOW_MMC 0x00FF8080 50 #define VOLTAGE_WINDOW_SD 0x80010000 51 52 /* SDI clock control register bits */ 53 #define SDI_CLKCR_CLKDIV_MASK 0x000000FF 54 #define SDI_CLKCR_CLKEN 0x00000100 55 #define SDI_CLKCR_PWRSAV 0x00000200 56 #define SDI_CLKCR_BYPASS 0x00000400 57 #define SDI_CLKCR_WIDBUS_MASK 0x00001800 58 #define SDI_CLKCR_WIDBUS_1 0x00000000 59 #define SDI_CLKCR_WIDBUS_4 0x00000800 60 /* V2 only */ 61 #define SDI_CLKCR_WIDBUS_8 0x00001000 62 #define SDI_CLKCR_NEDGE 0x00002000 63 #define SDI_CLKCR_HWFC_EN 0x00004000 64 65 #define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */ 66 #define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD 67 68 /* SDI command register bits */ 69 #define SDI_CMD_CMDINDEX_MASK 0x000000FF 70 #define SDI_CMD_WAITRESP 0x00000040 71 #define SDI_CMD_LONGRESP 0x00000080 72 #define SDI_CMD_WAITINT 0x00000100 73 #define SDI_CMD_WAITPEND 0x00000200 74 #define SDI_CMD_CPSMEN 0x00000400 75 #define SDI_CMD_SDIOSUSPEND 0x00000800 76 #define SDI_CMD_ENDCMDCOMPL 0x00001000 77 #define SDI_CMD_NIEN 0x00002000 78 #define SDI_CMD_CE_ATACMD 0x00004000 79 #define SDI_CMD_CBOOTMODEEN 0x00008000 80 81 #define SDI_DTIMER_DEFAULT 0xFFFF0000 82 83 /* SDI Status register bits */ 84 #define SDI_STA_CCRCFAIL 0x00000001 85 #define SDI_STA_DCRCFAIL 0x00000002 86 #define SDI_STA_CTIMEOUT 0x00000004 87 #define SDI_STA_DTIMEOUT 0x00000008 88 #define SDI_STA_TXUNDERR 0x00000010 89 #define SDI_STA_RXOVERR 0x00000020 90 #define SDI_STA_CMDREND 0x00000040 91 #define SDI_STA_CMDSENT 0x00000080 92 #define SDI_STA_DATAEND 0x00000100 93 #define SDI_STA_STBITERR 0x00000200 94 #define SDI_STA_DBCKEND 0x00000400 95 #define SDI_STA_CMDACT 0x00000800 96 #define SDI_STA_TXACT 0x00001000 97 #define SDI_STA_RXACT 0x00002000 98 #define SDI_STA_TXFIFOBW 0x00004000 99 #define SDI_STA_RXFIFOBR 0x00008000 100 #define SDI_STA_TXFIFOF 0x00010000 101 #define SDI_STA_RXFIFOF 0x00020000 102 #define SDI_STA_TXFIFOE 0x00040000 103 #define SDI_STA_RXFIFOE 0x00080000 104 #define SDI_STA_TXDAVL 0x00100000 105 #define SDI_STA_RXDAVL 0x00200000 106 #define SDI_STA_SDIOIT 0x00400000 107 #define SDI_STA_CEATAEND 0x00800000 108 #define SDI_STA_CARDBUSY 0x01000000 109 #define SDI_STA_BOOTMODE 0x02000000 110 #define SDI_STA_BOOTACKERR 0x04000000 111 #define SDI_STA_BOOTACKTIMEOUT 0x08000000 112 #define SDI_STA_RSTNEND 0x10000000 113 114 /* SDI Interrupt Clear register bits */ 115 #define SDI_ICR_MASK 0x1DC007FF 116 #define SDI_ICR_CCRCFAILC 0x00000001 117 #define SDI_ICR_DCRCFAILC 0x00000002 118 #define SDI_ICR_CTIMEOUTC 0x00000004 119 #define SDI_ICR_DTIMEOUTC 0x00000008 120 #define SDI_ICR_TXUNDERRC 0x00000010 121 #define SDI_ICR_RXOVERRC 0x00000020 122 #define SDI_ICR_CMDRENDC 0x00000040 123 #define SDI_ICR_CMDSENTC 0x00000080 124 #define SDI_ICR_DATAENDC 0x00000100 125 #define SDI_ICR_STBITERRC 0x00000200 126 #define SDI_ICR_DBCKENDC 0x00000400 127 #define SDI_ICR_SDIOITC 0x00400000 128 #define SDI_ICR_CEATAENDC 0x00800000 129 #define SDI_ICR_BUSYENDC 0x01000000 130 #define SDI_ICR_BOOTACKERRC 0x04000000 131 #define SDI_ICR_BOOTACKTIMEOUTC 0x08000000 132 #define SDI_ICR_RSTNENDC 0x10000000 133 134 #define SDI_MASK0_MASK 0x1FFFFFFF 135 136 /* SDI Data control register bits */ 137 #define SDI_DCTRL_DTEN 0x00000001 138 #define SDI_DCTRL_DTDIR_IN 0x00000002 139 #define SDI_DCTRL_DTMODE_STREAM 0x00000004 140 #define SDI_DCTRL_DMAEN 0x00000008 141 #define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0 142 #define SDI_DCTRL_RWSTART 0x00000100 143 #define SDI_DCTRL_RWSTOP 0x00000200 144 #define SDI_DCTRL_RWMOD 0x00000200 145 #define SDI_DCTRL_SDIOEN 0x00000800 146 #define SDI_DCTRL_DMAREQCTL 0x00001000 147 #define SDI_DCTRL_DBOOTMODEEN 0x00002000 148 #define SDI_DCTRL_BUSYMODE 0x00004000 149 #define SDI_DCTRL_DDR_MODE 0x00008000 150 #define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000 151 #define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16 152 153 #define SDI_FIFO_BURST_SIZE 8 154 155 struct sdi_registers { 156 u32 power; /* 0x00*/ 157 u32 clock; /* 0x04*/ 158 u32 argument; /* 0x08*/ 159 u32 command; /* 0x0c*/ 160 u32 respcommand; /* 0x10*/ 161 u32 response0; /* 0x14*/ 162 u32 response1; /* 0x18*/ 163 u32 response2; /* 0x1c*/ 164 u32 response3; /* 0x20*/ 165 u32 datatimer; /* 0x24*/ 166 u32 datalength; /* 0x28*/ 167 u32 datactrl; /* 0x2c*/ 168 u32 datacount; /* 0x30*/ 169 u32 status; /* 0x34*/ 170 u32 status_clear; /* 0x38*/ 171 u32 mask0; /* 0x3c*/ 172 u32 mask1; /* 0x40*/ 173 u32 card_select; /* 0x44*/ 174 u32 fifo_count; /* 0x48*/ 175 u32 padding1[(0x80-0x4C)>>2]; 176 u32 fifo; /* 0x80*/ 177 u32 padding2[(0xFE0-0x84)>>2]; 178 u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/ 179 u32 periph_id1; /* 0xFE4*/ 180 u32 periph_id2; /* 0xFE8*/ 181 u32 periph_id3; /* 0xFEC*/ 182 u32 pcell_id0; /* 0xFF0*/ 183 u32 pcell_id1; /* 0xFF4*/ 184 u32 pcell_id2; /* 0xFF8*/ 185 u32 pcell_id3; /* 0xFFC*/ 186 }; 187 188 struct pl180_mmc_host { 189 struct sdi_registers *base; 190 char name[32]; 191 unsigned int b_max; 192 unsigned int voltages; 193 unsigned int caps; 194 unsigned int clock_in; 195 unsigned int clock_min; 196 unsigned int clock_max; 197 unsigned int clkdiv_init; 198 unsigned int pwr_init; 199 int version2; 200 }; 201 202 int arm_pl180_mmci_init(struct pl180_mmc_host *); 203 204 #endif 205