123b93e1dSMatt Waddel /* 223b93e1dSMatt Waddel * ARM PrimeCell MultiMedia Card Interface - PL180 323b93e1dSMatt Waddel * 423b93e1dSMatt Waddel * Copyright (C) ST-Ericsson SA 2010 523b93e1dSMatt Waddel * 623b93e1dSMatt Waddel * Author: Ulf Hansson <ulf.hansson@stericsson.com> 723b93e1dSMatt Waddel * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com> 823b93e1dSMatt Waddel * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org> 923b93e1dSMatt Waddel * 1023b93e1dSMatt Waddel * This program is free software; you can redistribute it and/or 1123b93e1dSMatt Waddel * modify it under the terms of the GNU General Public License as 1223b93e1dSMatt Waddel * published by the Free Software Foundation; either version 2 of 1323b93e1dSMatt Waddel * the License, or (at your option) any later version. 1423b93e1dSMatt Waddel * 1523b93e1dSMatt Waddel * This program is distributed in the hope that it will be useful, 1623b93e1dSMatt Waddel * but WITHOUT ANY WARRANTY; without even the implied warranty of 1723b93e1dSMatt Waddel * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1823b93e1dSMatt Waddel * GNU General Public License for more details. 1923b93e1dSMatt Waddel * 2023b93e1dSMatt Waddel * You should have received a copy of the GNU General Public License 2123b93e1dSMatt Waddel * along with this program; if not, write to the Free Software 2223b93e1dSMatt Waddel * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2323b93e1dSMatt Waddel * MA 02111-1307 USA 2423b93e1dSMatt Waddel */ 2523b93e1dSMatt Waddel 2623b93e1dSMatt Waddel #ifndef __ARM_PL180_MMCI_H__ 2723b93e1dSMatt Waddel #define __ARM_PL180_MMCI_H__ 2823b93e1dSMatt Waddel 2923b93e1dSMatt Waddel #define COMMAND_REG_DELAY 300 3023b93e1dSMatt Waddel #define DATA_REG_DELAY 1000 3123b93e1dSMatt Waddel #define CLK_CHANGE_DELAY 2000 3223b93e1dSMatt Waddel 3323b93e1dSMatt Waddel #define INIT_PWR 0xBF /* Power on, full power, not open drain */ 3423b93e1dSMatt Waddel #define ARM_MCLK (100*1000*1000) 3523b93e1dSMatt Waddel 3623b93e1dSMatt Waddel /* SDI Power Control register bits */ 3723b93e1dSMatt Waddel #define SDI_PWR_PWRCTRL_MASK 0x00000003 3823b93e1dSMatt Waddel #define SDI_PWR_PWRCTRL_ON 0x00000003 3923b93e1dSMatt Waddel #define SDI_PWR_PWRCTRL_OFF 0x00000000 4023b93e1dSMatt Waddel #define SDI_PWR_DAT2DIREN 0x00000004 4123b93e1dSMatt Waddel #define SDI_PWR_CMDDIREN 0x00000008 4223b93e1dSMatt Waddel #define SDI_PWR_DAT0DIREN 0x00000010 4323b93e1dSMatt Waddel #define SDI_PWR_DAT31DIREN 0x00000020 4423b93e1dSMatt Waddel #define SDI_PWR_OPD 0x00000040 4523b93e1dSMatt Waddel #define SDI_PWR_FBCLKEN 0x00000080 4623b93e1dSMatt Waddel #define SDI_PWR_DAT74DIREN 0x00000100 4723b93e1dSMatt Waddel #define SDI_PWR_RSTEN 0x00000200 4823b93e1dSMatt Waddel 4923b93e1dSMatt Waddel #define VOLTAGE_WINDOW_MMC 0x00FF8080 5023b93e1dSMatt Waddel #define VOLTAGE_WINDOW_SD 0x80010000 5123b93e1dSMatt Waddel 5223b93e1dSMatt Waddel /* SDI clock control register bits */ 5323b93e1dSMatt Waddel #define SDI_CLKCR_CLKDIV_MASK 0x000000FF 5423b93e1dSMatt Waddel #define SDI_CLKCR_CLKEN 0x00000100 5523b93e1dSMatt Waddel #define SDI_CLKCR_PWRSAV 0x00000200 5623b93e1dSMatt Waddel #define SDI_CLKCR_BYPASS 0x00000400 5723b93e1dSMatt Waddel #define SDI_CLKCR_WIDBUS_MASK 0x00001800 5823b93e1dSMatt Waddel #define SDI_CLKCR_WIDBUS_1 0x00000000 5923b93e1dSMatt Waddel #define SDI_CLKCR_WIDBUS_4 0x00000800 60*10ed93dcSJohn Rigby /* V2 only */ 61*10ed93dcSJohn Rigby #define SDI_CLKCR_WIDBUS_8 0x00001000 62*10ed93dcSJohn Rigby #define SDI_CLKCR_NEDGE 0x00002000 63*10ed93dcSJohn Rigby #define SDI_CLKCR_HWFC_EN 0x00004000 6423b93e1dSMatt Waddel 65*10ed93dcSJohn Rigby #define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */ 66*10ed93dcSJohn Rigby #define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD 6723b93e1dSMatt Waddel 6823b93e1dSMatt Waddel /* SDI command register bits */ 6923b93e1dSMatt Waddel #define SDI_CMD_CMDINDEX_MASK 0x000000FF 7023b93e1dSMatt Waddel #define SDI_CMD_WAITRESP 0x00000040 7123b93e1dSMatt Waddel #define SDI_CMD_LONGRESP 0x00000080 7223b93e1dSMatt Waddel #define SDI_CMD_WAITINT 0x00000100 7323b93e1dSMatt Waddel #define SDI_CMD_WAITPEND 0x00000200 7423b93e1dSMatt Waddel #define SDI_CMD_CPSMEN 0x00000400 7523b93e1dSMatt Waddel #define SDI_CMD_SDIOSUSPEND 0x00000800 7623b93e1dSMatt Waddel #define SDI_CMD_ENDCMDCOMPL 0x00001000 7723b93e1dSMatt Waddel #define SDI_CMD_NIEN 0x00002000 7823b93e1dSMatt Waddel #define SDI_CMD_CE_ATACMD 0x00004000 7923b93e1dSMatt Waddel #define SDI_CMD_CBOOTMODEEN 0x00008000 8023b93e1dSMatt Waddel 8123b93e1dSMatt Waddel #define SDI_DTIMER_DEFAULT 0xFFFF0000 8223b93e1dSMatt Waddel 8323b93e1dSMatt Waddel /* SDI Status register bits */ 8423b93e1dSMatt Waddel #define SDI_STA_CCRCFAIL 0x00000001 8523b93e1dSMatt Waddel #define SDI_STA_DCRCFAIL 0x00000002 8623b93e1dSMatt Waddel #define SDI_STA_CTIMEOUT 0x00000004 8723b93e1dSMatt Waddel #define SDI_STA_DTIMEOUT 0x00000008 8823b93e1dSMatt Waddel #define SDI_STA_TXUNDERR 0x00000010 8923b93e1dSMatt Waddel #define SDI_STA_RXOVERR 0x00000020 9023b93e1dSMatt Waddel #define SDI_STA_CMDREND 0x00000040 9123b93e1dSMatt Waddel #define SDI_STA_CMDSENT 0x00000080 9223b93e1dSMatt Waddel #define SDI_STA_DATAEND 0x00000100 9323b93e1dSMatt Waddel #define SDI_STA_STBITERR 0x00000200 9423b93e1dSMatt Waddel #define SDI_STA_DBCKEND 0x00000400 9523b93e1dSMatt Waddel #define SDI_STA_CMDACT 0x00000800 9623b93e1dSMatt Waddel #define SDI_STA_TXACT 0x00001000 9723b93e1dSMatt Waddel #define SDI_STA_RXACT 0x00002000 9823b93e1dSMatt Waddel #define SDI_STA_TXFIFOBW 0x00004000 9923b93e1dSMatt Waddel #define SDI_STA_RXFIFOBR 0x00008000 10023b93e1dSMatt Waddel #define SDI_STA_TXFIFOF 0x00010000 10123b93e1dSMatt Waddel #define SDI_STA_RXFIFOF 0x00020000 10223b93e1dSMatt Waddel #define SDI_STA_TXFIFOE 0x00040000 10323b93e1dSMatt Waddel #define SDI_STA_RXFIFOE 0x00080000 10423b93e1dSMatt Waddel #define SDI_STA_TXDAVL 0x00100000 10523b93e1dSMatt Waddel #define SDI_STA_RXDAVL 0x00200000 10623b93e1dSMatt Waddel #define SDI_STA_SDIOIT 0x00400000 10723b93e1dSMatt Waddel #define SDI_STA_CEATAEND 0x00800000 10823b93e1dSMatt Waddel #define SDI_STA_CARDBUSY 0x01000000 10923b93e1dSMatt Waddel #define SDI_STA_BOOTMODE 0x02000000 11023b93e1dSMatt Waddel #define SDI_STA_BOOTACKERR 0x04000000 11123b93e1dSMatt Waddel #define SDI_STA_BOOTACKTIMEOUT 0x08000000 11223b93e1dSMatt Waddel #define SDI_STA_RSTNEND 0x10000000 11323b93e1dSMatt Waddel 11423b93e1dSMatt Waddel /* SDI Interrupt Clear register bits */ 11523b93e1dSMatt Waddel #define SDI_ICR_MASK 0x1DC007FF 11623b93e1dSMatt Waddel #define SDI_ICR_CCRCFAILC 0x00000001 11723b93e1dSMatt Waddel #define SDI_ICR_DCRCFAILC 0x00000002 11823b93e1dSMatt Waddel #define SDI_ICR_CTIMEOUTC 0x00000004 11923b93e1dSMatt Waddel #define SDI_ICR_DTIMEOUTC 0x00000008 12023b93e1dSMatt Waddel #define SDI_ICR_TXUNDERRC 0x00000010 12123b93e1dSMatt Waddel #define SDI_ICR_RXOVERRC 0x00000020 12223b93e1dSMatt Waddel #define SDI_ICR_CMDRENDC 0x00000040 12323b93e1dSMatt Waddel #define SDI_ICR_CMDSENTC 0x00000080 12423b93e1dSMatt Waddel #define SDI_ICR_DATAENDC 0x00000100 12523b93e1dSMatt Waddel #define SDI_ICR_STBITERRC 0x00000200 12623b93e1dSMatt Waddel #define SDI_ICR_DBCKENDC 0x00000400 12723b93e1dSMatt Waddel #define SDI_ICR_SDIOITC 0x00400000 12823b93e1dSMatt Waddel #define SDI_ICR_CEATAENDC 0x00800000 12923b93e1dSMatt Waddel #define SDI_ICR_BUSYENDC 0x01000000 13023b93e1dSMatt Waddel #define SDI_ICR_BOOTACKERRC 0x04000000 13123b93e1dSMatt Waddel #define SDI_ICR_BOOTACKTIMEOUTC 0x08000000 13223b93e1dSMatt Waddel #define SDI_ICR_RSTNENDC 0x10000000 13323b93e1dSMatt Waddel 13423b93e1dSMatt Waddel #define SDI_MASK0_MASK 0x1FFFFFFF 13523b93e1dSMatt Waddel 13623b93e1dSMatt Waddel /* SDI Data control register bits */ 13723b93e1dSMatt Waddel #define SDI_DCTRL_DTEN 0x00000001 13823b93e1dSMatt Waddel #define SDI_DCTRL_DTDIR_IN 0x00000002 13923b93e1dSMatt Waddel #define SDI_DCTRL_DTMODE_STREAM 0x00000004 14023b93e1dSMatt Waddel #define SDI_DCTRL_DMAEN 0x00000008 14123b93e1dSMatt Waddel #define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0 14223b93e1dSMatt Waddel #define SDI_DCTRL_RWSTART 0x00000100 14323b93e1dSMatt Waddel #define SDI_DCTRL_RWSTOP 0x00000200 14423b93e1dSMatt Waddel #define SDI_DCTRL_RWMOD 0x00000200 14523b93e1dSMatt Waddel #define SDI_DCTRL_SDIOEN 0x00000800 14623b93e1dSMatt Waddel #define SDI_DCTRL_DMAREQCTL 0x00001000 14723b93e1dSMatt Waddel #define SDI_DCTRL_DBOOTMODEEN 0x00002000 14823b93e1dSMatt Waddel #define SDI_DCTRL_BUSYMODE 0x00004000 14923b93e1dSMatt Waddel #define SDI_DCTRL_DDR_MODE 0x00008000 150*10ed93dcSJohn Rigby #define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000 151*10ed93dcSJohn Rigby #define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16 15223b93e1dSMatt Waddel 15323b93e1dSMatt Waddel #define SDI_FIFO_BURST_SIZE 8 15423b93e1dSMatt Waddel 15523b93e1dSMatt Waddel struct sdi_registers { 15623b93e1dSMatt Waddel u32 power; /* 0x00*/ 15723b93e1dSMatt Waddel u32 clock; /* 0x04*/ 15823b93e1dSMatt Waddel u32 argument; /* 0x08*/ 15923b93e1dSMatt Waddel u32 command; /* 0x0c*/ 16023b93e1dSMatt Waddel u32 respcommand; /* 0x10*/ 16123b93e1dSMatt Waddel u32 response0; /* 0x14*/ 16223b93e1dSMatt Waddel u32 response1; /* 0x18*/ 16323b93e1dSMatt Waddel u32 response2; /* 0x1c*/ 16423b93e1dSMatt Waddel u32 response3; /* 0x20*/ 16523b93e1dSMatt Waddel u32 datatimer; /* 0x24*/ 16623b93e1dSMatt Waddel u32 datalength; /* 0x28*/ 16723b93e1dSMatt Waddel u32 datactrl; /* 0x2c*/ 16823b93e1dSMatt Waddel u32 datacount; /* 0x30*/ 16923b93e1dSMatt Waddel u32 status; /* 0x34*/ 17023b93e1dSMatt Waddel u32 status_clear; /* 0x38*/ 17123b93e1dSMatt Waddel u32 mask0; /* 0x3c*/ 17223b93e1dSMatt Waddel u32 mask1; /* 0x40*/ 17323b93e1dSMatt Waddel u32 card_select; /* 0x44*/ 17423b93e1dSMatt Waddel u32 fifo_count; /* 0x48*/ 17523b93e1dSMatt Waddel u32 padding1[(0x80-0x4C)>>2]; 17623b93e1dSMatt Waddel u32 fifo; /* 0x80*/ 17723b93e1dSMatt Waddel u32 padding2[(0xFE0-0x84)>>2]; 17823b93e1dSMatt Waddel u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/ 17923b93e1dSMatt Waddel u32 periph_id1; /* 0xFE4*/ 18023b93e1dSMatt Waddel u32 periph_id2; /* 0xFE8*/ 18123b93e1dSMatt Waddel u32 periph_id3; /* 0xFEC*/ 18223b93e1dSMatt Waddel u32 pcell_id0; /* 0xFF0*/ 18323b93e1dSMatt Waddel u32 pcell_id1; /* 0xFF4*/ 18423b93e1dSMatt Waddel u32 pcell_id2; /* 0xFF8*/ 18523b93e1dSMatt Waddel u32 pcell_id3; /* 0xFFC*/ 18623b93e1dSMatt Waddel }; 18723b93e1dSMatt Waddel 188*10ed93dcSJohn Rigby struct pl180_mmc_host { 189*10ed93dcSJohn Rigby struct sdi_registers *base; 190*10ed93dcSJohn Rigby char name[32]; 191*10ed93dcSJohn Rigby unsigned int b_max; 192*10ed93dcSJohn Rigby unsigned int voltages; 193*10ed93dcSJohn Rigby unsigned int caps; 194*10ed93dcSJohn Rigby unsigned int clock_in; 195*10ed93dcSJohn Rigby unsigned int clock_min; 196*10ed93dcSJohn Rigby unsigned int clock_max; 197*10ed93dcSJohn Rigby unsigned int clkdiv_init; 198*10ed93dcSJohn Rigby unsigned int pwr_init; 199*10ed93dcSJohn Rigby int version2; 200*10ed93dcSJohn Rigby }; 201*10ed93dcSJohn Rigby 202*10ed93dcSJohn Rigby int arm_pl180_mmci_init(struct pl180_mmc_host *); 203*10ed93dcSJohn Rigby 20423b93e1dSMatt Waddel #endif 205