xref: /openbmc/u-boot/drivers/misc/mxs_ocotp.c (revision cbd2fba1) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Freescale i.MX28 OCOTP Driver
4  *
5  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
6  *
7  * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
8  *       used in i.MX6 . While these blocks are very similar at the first
9  *       glance, by digging deeper, one will notice differences (like the
10  *       tight dependence on MXS power block, some completely new registers
11  *       etc.) which would make common driver an ifdef nightmare :-(
12  */
13 
14 #include <common.h>
15 #include <fuse.h>
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/sys_proto.h>
21 
22 #define MXS_OCOTP_TIMEOUT	100000
23 
24 static struct mxs_ocotp_regs *ocotp_regs =
25 	(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
26 static struct mxs_power_regs *power_regs =
27 	(struct mxs_power_regs *)MXS_POWER_BASE;
28 static struct mxs_clkctrl_regs *clkctrl_regs =
29 	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
30 
31 static int mxs_ocotp_wait_busy_clear(void)
32 {
33 	uint32_t reg;
34 	int timeout = MXS_OCOTP_TIMEOUT;
35 
36 	while (--timeout) {
37 		reg = readl(&ocotp_regs->hw_ocotp_ctrl);
38 		if (!(reg & OCOTP_CTRL_BUSY))
39 			break;
40 		udelay(10);
41 	}
42 
43 	if (!timeout)
44 		return -EINVAL;
45 
46 	/* Wait a little as per FSL datasheet's 'write postamble' section. */
47 	udelay(10);
48 
49 	return 0;
50 }
51 
52 static void mxs_ocotp_clear_error(void)
53 {
54 	writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr);
55 }
56 
57 static int mxs_ocotp_read_bank_open(bool open)
58 {
59 	int ret = 0;
60 
61 	if (open) {
62 		writel(OCOTP_CTRL_RD_BANK_OPEN,
63 		       &ocotp_regs->hw_ocotp_ctrl_set);
64 
65 		/*
66 		 * Wait before polling the BUSY bit, since the BUSY bit might
67 		 * be asserted only after a few HCLK cycles and if we were to
68 		 * poll immediatelly, we could miss the busy bit.
69 		 */
70 		udelay(10);
71 		ret = mxs_ocotp_wait_busy_clear();
72 	} else {
73 		writel(OCOTP_CTRL_RD_BANK_OPEN,
74 		       &ocotp_regs->hw_ocotp_ctrl_clr);
75 	}
76 
77 	return ret;
78 }
79 
80 static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val)
81 {
82 	uint32_t scale_val;
83 
84 	if (enter) {
85 		/*
86 		 * Enter the fuse programming VDDIO voltage setup. We start
87 		 * scaling the voltage from it's current value down to 2.8V
88 		 * which is the one and only correct voltage for programming
89 		 * the OCOTP fuses (according to datasheet).
90 		 */
91 		scale_val = readl(&power_regs->hw_power_vddioctrl);
92 		scale_val &= POWER_VDDIOCTRL_TRG_MASK;
93 
94 		/* Return the original voltage. */
95 		*val = scale_val;
96 
97 		/*
98 		 * Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
99 		 * the value 0x0 should be 2.8V, but that's not the case on
100 		 * most designs due to load etc., so we play safe. Undervolt
101 		 * can actually cause incorrect programming of the fuses and
102 		 * or reboots of the board.
103 		 */
104 		while (scale_val > 2) {
105 			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
106 					POWER_VDDIOCTRL_TRG_MASK, --scale_val);
107 			udelay(500);
108 		}
109 	} else {
110 		/* Start scaling VDDIO up to original value . */
111 		for (scale_val = 2; scale_val <= *val; scale_val++) {
112 			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
113 					POWER_VDDIOCTRL_TRG_MASK, scale_val);
114 			udelay(500);
115 		}
116 	}
117 
118 	mdelay(10);
119 }
120 
121 static int mxs_ocotp_wait_hclk_ready(void)
122 {
123 	uint32_t reg, timeout = MXS_OCOTP_TIMEOUT;
124 
125 	while (--timeout) {
126 		reg = readl(&clkctrl_regs->hw_clkctrl_hbus);
127 		if (!(reg & CLKCTRL_HBUS_ASM_BUSY))
128 			break;
129 	}
130 
131 	if (!timeout)
132 		return -EINVAL;
133 
134 	return 0;
135 }
136 
137 static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
138 {
139 	uint32_t scale_val;
140 	int ret;
141 
142 	ret = mxs_ocotp_wait_hclk_ready();
143 	if (ret)
144 		return ret;
145 
146 	/* Set CPU bypass */
147 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
148 	       &clkctrl_regs->hw_clkctrl_clkseq_set);
149 
150 	if (enter) {
151 		/* Return the original HCLK clock speed. */
152 		*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
153 		*val &= CLKCTRL_HBUS_DIV_MASK;
154 		*val >>= CLKCTRL_HBUS_DIV_OFFSET;
155 
156 		/* Scale the HCLK to 454/19 = 23.9 MHz . */
157 		scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
158 		scale_val &= CLKCTRL_HBUS_DIV_MASK;
159 	} else {
160 		/* Scale the HCLK back to original frequency. */
161 		scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET;
162 		scale_val &= CLKCTRL_HBUS_DIV_MASK;
163 	}
164 
165 	writel(CLKCTRL_HBUS_DIV_MASK,
166 	       &clkctrl_regs->hw_clkctrl_hbus_set);
167 	writel(scale_val,
168 	       &clkctrl_regs->hw_clkctrl_hbus_clr);
169 
170 	mdelay(10);
171 
172 	ret = mxs_ocotp_wait_hclk_ready();
173 	if (ret)
174 		return ret;
175 
176 	/* Disable CPU bypass */
177 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
178 	       &clkctrl_regs->hw_clkctrl_clkseq_clr);
179 
180 	mdelay(10);
181 
182 	return 0;
183 }
184 
185 static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
186 {
187 	uint32_t hclk_val, vddio_val;
188 	int ret;
189 
190 	mxs_ocotp_clear_error();
191 
192 	/* Make sure the banks are closed for reading. */
193 	ret = mxs_ocotp_read_bank_open(0);
194 	if (ret) {
195 		puts("Failed closing banks for reading!\n");
196 		return ret;
197 	}
198 
199 	ret = mxs_ocotp_scale_hclk(1, &hclk_val);
200 	if (ret) {
201 		puts("Failed scaling down the HCLK!\n");
202 		return ret;
203 	}
204 	mxs_ocotp_scale_vddio(1, &vddio_val);
205 
206 	ret = mxs_ocotp_wait_busy_clear();
207 	if (ret) {
208 		puts("Failed waiting for ready state!\n");
209 		goto fail;
210 	}
211 
212 	/* Program the fuse address */
213 	writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl);
214 
215 	/* Program the data. */
216 	writel(mask, &ocotp_regs->hw_ocotp_data);
217 
218 	udelay(10);
219 
220 	ret = mxs_ocotp_wait_busy_clear();
221 	if (ret) {
222 		puts("Failed waiting for ready state!\n");
223 		goto fail;
224 	}
225 
226 	/* Check for errors */
227 	if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
228 		puts("Failed writing fuses!\n");
229 		ret = -EPERM;
230 		goto fail;
231 	}
232 
233 fail:
234 	mxs_ocotp_scale_vddio(0, &vddio_val);
235 	if (mxs_ocotp_scale_hclk(0, &hclk_val))
236 		puts("Failed scaling up the HCLK!\n");
237 
238 	return ret;
239 }
240 
241 static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val)
242 {
243 	int ret;
244 
245 	/* Register offset from CUST0 */
246 	reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4);
247 
248 	ret = mxs_ocotp_wait_busy_clear();
249 	if (ret) {
250 		puts("Failed waiting for ready state!\n");
251 		return ret;
252 	}
253 
254 	mxs_ocotp_clear_error();
255 
256 	ret = mxs_ocotp_read_bank_open(1);
257 	if (ret) {
258 		puts("Failed opening banks for reading!\n");
259 		return ret;
260 	}
261 
262 	*val = readl(reg);
263 
264 	ret = mxs_ocotp_read_bank_open(0);
265 	if (ret) {
266 		puts("Failed closing banks for reading!\n");
267 		return ret;
268 	}
269 
270 	return ret;
271 }
272 
273 static int mxs_ocotp_valid(u32 bank, u32 word)
274 {
275 	if (bank > 4)
276 		return -EINVAL;
277 	if (word > 7)
278 		return -EINVAL;
279 	return 0;
280 }
281 
282 /*
283  * The 'fuse' command API
284  */
285 int fuse_read(u32 bank, u32 word, u32 *val)
286 {
287 	int ret;
288 
289 	ret = mxs_ocotp_valid(bank, word);
290 	if (ret)
291 		return ret;
292 
293 	return mxs_ocotp_read_fuse((bank << 3) | word, val);
294 }
295 
296 int fuse_prog(u32 bank, u32 word, u32 val)
297 {
298 	int ret;
299 
300 	ret = mxs_ocotp_valid(bank, word);
301 	if (ret)
302 		return ret;
303 
304 	return mxs_ocotp_write_fuse((bank << 3) | word, val);
305 }
306 
307 int fuse_sense(u32 bank, u32 word, u32 *val)
308 {
309 	/* We do not support sensing :-( */
310 	return -EINVAL;
311 }
312 
313 int fuse_override(u32 bank, u32 word, u32 val)
314 {
315 	/* We do not support overriding :-( */
316 	return -EINVAL;
317 }
318