1 /* 2 * (C) Copyright 2013 ADVANSEE 3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> 4 * 5 * Based on Dirk Behme's 6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c, 7 * which is based on Freescale's 8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6, 9 * which is: 10 * Copyright (C) 2011 Freescale Semiconductor, Inc. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <fuse.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/imx-regs.h> 21 #include <asm/mach-imx/sys_proto.h> 22 23 #define BO_CTRL_WR_UNLOCK 16 24 #define BM_CTRL_WR_UNLOCK 0xffff0000 25 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77 26 #define BM_CTRL_ERROR 0x00000200 27 #define BM_CTRL_BUSY 0x00000100 28 #define BO_CTRL_ADDR 0 29 #ifdef CONFIG_MX7 30 #define BM_CTRL_ADDR 0x0000000f 31 #define BM_CTRL_RELOAD 0x00000400 32 #elif defined(CONFIG_MX7ULP) 33 #define BM_CTRL_ADDR 0x000000FF 34 #define BM_CTRL_RELOAD 0x00000400 35 #define BM_OUT_STATUS_DED 0x00000400 36 #define BM_OUT_STATUS_LOCKED 0x00000800 37 #define BM_OUT_STATUS_PROGFAIL 0x00001000 38 #else 39 #define BM_CTRL_ADDR 0x0000007f 40 #endif 41 42 #ifdef CONFIG_MX7 43 #define BO_TIMING_FSOURCE 12 44 #define BM_TIMING_FSOURCE 0x0007f000 45 #define BV_TIMING_FSOURCE_NS 1001 46 #define BO_TIMING_PROG 0 47 #define BM_TIMING_PROG 0x00000fff 48 #define BV_TIMING_PROG_US 10 49 #else 50 #define BO_TIMING_STROBE_READ 16 51 #define BM_TIMING_STROBE_READ 0x003f0000 52 #define BV_TIMING_STROBE_READ_NS 37 53 #define BO_TIMING_RELAX 12 54 #define BM_TIMING_RELAX 0x0000f000 55 #define BV_TIMING_RELAX_NS 17 56 #define BO_TIMING_STROBE_PROG 0 57 #define BM_TIMING_STROBE_PROG 0x00000fff 58 #define BV_TIMING_STROBE_PROG_US 10 59 #endif 60 61 #define BM_READ_CTRL_READ_FUSE 0x00000001 62 63 #define BF(value, field) (((value) << BO_##field) & BM_##field) 64 65 #define WRITE_POSTAMBLE_US 2 66 67 #if defined(CONFIG_MX6) || defined(CONFIG_VF610) 68 #define FUSE_BANK_SIZE 0x80 69 #ifdef CONFIG_MX6SL 70 #define FUSE_BANKS 8 71 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) 72 #define FUSE_BANKS 9 73 #else 74 #define FUSE_BANKS 16 75 #endif 76 #elif defined CONFIG_MX7 77 #define FUSE_BANK_SIZE 0x40 78 #define FUSE_BANKS 16 79 #elif defined(CONFIG_MX7ULP) 80 #define FUSE_BANK_SIZE 0x80 81 #define FUSE_BANKS 31 82 #else 83 #error "Unsupported architecture\n" 84 #endif 85 86 #if defined(CONFIG_MX6) 87 88 /* 89 * There is a hole in shadow registers address map of size 0x100 90 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, 91 * iMX6UL, i.MX6ULL and i.MX6SLL. 92 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, 93 * we should account for this hole in address space. 94 * 95 * Similar hole exists between bank 14 and bank 15 of size 96 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. 97 * Note: iMX6SL has only 0-7 banks and there is no hole. 98 * Note: iMX6UL doesn't have this one. 99 * 100 * This function is to covert user input to physical bank index. 101 * Only needed when read fuse, because we use register offset, so 102 * need to calculate real register offset. 103 * When write, no need to consider hole, always use the bank/word 104 * index from fuse map. 105 */ 106 u32 fuse_bank_physical(int index) 107 { 108 u32 phy_index; 109 110 if (is_mx6sl() || is_mx7ulp()) { 111 phy_index = index; 112 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { 113 if ((is_mx6ull() || is_mx6sll()) && index == 8) 114 index = 7; 115 116 if (index >= 6) 117 phy_index = fuse_bank_physical(5) + (index - 6) + 3; 118 else 119 phy_index = index; 120 } else { 121 if (index >= 15) 122 phy_index = fuse_bank_physical(14) + (index - 15) + 2; 123 else if (index >= 6) 124 phy_index = fuse_bank_physical(5) + (index - 6) + 3; 125 else 126 phy_index = index; 127 } 128 return phy_index; 129 } 130 131 u32 fuse_word_physical(u32 bank, u32 word_index) 132 { 133 if (is_mx6ull() || is_mx6sll()) { 134 if (bank == 8) 135 word_index = word_index + 4; 136 } 137 138 return word_index; 139 } 140 #else 141 u32 fuse_bank_physical(int index) 142 { 143 return index; 144 } 145 146 u32 fuse_word_physical(u32 bank, u32 word_index) 147 { 148 return word_index; 149 } 150 151 #endif 152 153 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) 154 { 155 while (readl(®s->ctrl) & BM_CTRL_BUSY) 156 udelay(delay_us); 157 } 158 159 static void clear_error(struct ocotp_regs *regs) 160 { 161 writel(BM_CTRL_ERROR, ®s->ctrl_clr); 162 } 163 164 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, 165 int assert, const char *caller) 166 { 167 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; 168 169 if (bank >= FUSE_BANKS || 170 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || 171 !assert) { 172 printf("mxc_ocotp %s(): Invalid argument\n", caller); 173 return -EINVAL; 174 } 175 176 if (is_mx6ull() || is_mx6sll()) { 177 if ((bank == 7 || bank == 8) && 178 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { 179 printf("mxc_ocotp %s(): Invalid argument\n", caller); 180 return -EINVAL; 181 } 182 } 183 184 enable_ocotp_clk(1); 185 186 wait_busy(*regs, 1); 187 clear_error(*regs); 188 189 return 0; 190 } 191 192 static int finish_access(struct ocotp_regs *regs, const char *caller) 193 { 194 u32 err; 195 196 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); 197 clear_error(regs); 198 199 #ifdef CONFIG_MX7ULP 200 /* Need to power down the OTP memory */ 201 writel(1, ®s->pdn); 202 #endif 203 if (err) { 204 printf("mxc_ocotp %s(): Access protect error\n", caller); 205 return -EIO; 206 } 207 208 return 0; 209 } 210 211 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, 212 const char *caller) 213 { 214 return prepare_access(regs, bank, word, val != NULL, caller); 215 } 216 217 int fuse_read(u32 bank, u32 word, u32 *val) 218 { 219 struct ocotp_regs *regs; 220 int ret; 221 u32 phy_bank; 222 u32 phy_word; 223 224 ret = prepare_read(®s, bank, word, val, __func__); 225 if (ret) 226 return ret; 227 228 phy_bank = fuse_bank_physical(bank); 229 phy_word = fuse_word_physical(bank, word); 230 231 *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); 232 233 #ifdef CONFIG_MX7ULP 234 if (readl(®s->out_status) & BM_OUT_STATUS_DED) { 235 writel(BM_OUT_STATUS_DED, ®s->out_status_clr); 236 printf("mxc_ocotp %s(): fuse read wrong\n", __func__); 237 return -EIO; 238 } 239 #endif 240 return finish_access(regs, __func__); 241 } 242 243 #ifdef CONFIG_MX7 244 static void set_timing(struct ocotp_regs *regs) 245 { 246 u32 ipg_clk; 247 u32 fsource, prog; 248 u32 timing; 249 250 ipg_clk = mxc_get_clock(MXC_IPG_CLK); 251 252 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS, 253 + 1000000) + 1; 254 prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1; 255 256 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); 257 258 clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, 259 timing); 260 } 261 #elif defined(CONFIG_MX7ULP) 262 static void set_timing(struct ocotp_regs *regs) 263 { 264 /* No timing set for MX7ULP */ 265 } 266 267 #else 268 static void set_timing(struct ocotp_regs *regs) 269 { 270 u32 ipg_clk; 271 u32 relax, strobe_read, strobe_prog; 272 u32 timing; 273 274 ipg_clk = mxc_get_clock(MXC_IPG_CLK); 275 276 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; 277 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, 278 1000000000) + 2 * (relax + 1) - 1; 279 strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, 280 1000000) + 2 * (relax + 1) - 1; 281 282 timing = BF(strobe_read, TIMING_STROBE_READ) | 283 BF(relax, TIMING_RELAX) | 284 BF(strobe_prog, TIMING_STROBE_PROG); 285 286 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | 287 BM_TIMING_STROBE_PROG, timing); 288 } 289 #endif 290 291 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, 292 int write) 293 { 294 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; 295 #ifdef CONFIG_MX7 296 u32 addr = bank; 297 #else 298 u32 addr; 299 /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ 300 if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) { 301 bank = bank - 1; 302 word += 4; 303 } 304 addr = bank << 3 | word; 305 #endif 306 307 set_timing(regs); 308 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, 309 BF(wr_unlock, CTRL_WR_UNLOCK) | 310 BF(addr, CTRL_ADDR)); 311 } 312 313 int fuse_sense(u32 bank, u32 word, u32 *val) 314 { 315 struct ocotp_regs *regs; 316 int ret; 317 318 ret = prepare_read(®s, bank, word, val, __func__); 319 if (ret) 320 return ret; 321 322 setup_direct_access(regs, bank, word, false); 323 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl); 324 wait_busy(regs, 1); 325 #ifdef CONFIG_MX7 326 *val = readl((®s->read_fuse_data0) + (word << 2)); 327 #else 328 *val = readl(®s->read_fuse_data); 329 #endif 330 331 #ifdef CONFIG_MX7ULP 332 if (readl(®s->out_status) & BM_OUT_STATUS_DED) { 333 writel(BM_OUT_STATUS_DED, ®s->out_status_clr); 334 printf("mxc_ocotp %s(): fuse read wrong\n", __func__); 335 return -EIO; 336 } 337 #endif 338 339 return finish_access(regs, __func__); 340 } 341 342 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, 343 const char *caller) 344 { 345 #ifdef CONFIG_MX7ULP 346 u32 val; 347 int ret; 348 349 /* Only bank 0 and 1 are redundancy mode, others are ECC mode */ 350 if (bank != 0 && bank != 1) { 351 ret = fuse_sense(bank, word, &val); 352 if (ret) 353 return ret; 354 355 if (val != 0) { 356 printf("mxc_ocotp: The word has been programmed, no more write\n"); 357 return -EPERM; 358 } 359 } 360 #endif 361 362 return prepare_access(regs, bank, word, true, caller); 363 } 364 365 int fuse_prog(u32 bank, u32 word, u32 val) 366 { 367 struct ocotp_regs *regs; 368 int ret; 369 370 ret = prepare_write(®s, bank, word, __func__); 371 if (ret) 372 return ret; 373 374 setup_direct_access(regs, bank, word, true); 375 #ifdef CONFIG_MX7 376 switch (word) { 377 case 0: 378 writel(0, ®s->data1); 379 writel(0, ®s->data2); 380 writel(0, ®s->data3); 381 writel(val, ®s->data0); 382 break; 383 case 1: 384 writel(val, ®s->data1); 385 writel(0, ®s->data2); 386 writel(0, ®s->data3); 387 writel(0, ®s->data0); 388 break; 389 case 2: 390 writel(0, ®s->data1); 391 writel(val, ®s->data2); 392 writel(0, ®s->data3); 393 writel(0, ®s->data0); 394 break; 395 case 3: 396 writel(0, ®s->data1); 397 writel(0, ®s->data2); 398 writel(val, ®s->data3); 399 writel(0, ®s->data0); 400 break; 401 } 402 wait_busy(regs, BV_TIMING_PROG_US); 403 #else 404 writel(val, ®s->data); 405 wait_busy(regs, BV_TIMING_STROBE_PROG_US); 406 #endif 407 udelay(WRITE_POSTAMBLE_US); 408 409 #ifdef CONFIG_MX7ULP 410 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { 411 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); 412 printf("mxc_ocotp %s(): fuse write is failed\n", __func__); 413 return -EIO; 414 } 415 #endif 416 417 return finish_access(regs, __func__); 418 } 419 420 int fuse_override(u32 bank, u32 word, u32 val) 421 { 422 struct ocotp_regs *regs; 423 int ret; 424 u32 phy_bank; 425 u32 phy_word; 426 427 ret = prepare_write(®s, bank, word, __func__); 428 if (ret) 429 return ret; 430 431 phy_bank = fuse_bank_physical(bank); 432 phy_word = fuse_word_physical(bank, word); 433 434 writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); 435 436 #ifdef CONFIG_MX7ULP 437 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { 438 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); 439 printf("mxc_ocotp %s(): fuse write is failed\n", __func__); 440 return -EIO; 441 } 442 #endif 443 444 return finish_access(regs, __func__); 445 } 446